Making interconnections by curving conducting elements under a microelectronic device such as a chip

Abstract

A method of making connection elements for a microelectronic device is provided, including foil ling a conducting layer on a support on which there is at least one conducting pad located on a front face of the support opposite a back face thereof, the conducting layer including a first conducting portion in contact with at least one conducting pad, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support being located between the front and back faces and forming a non-zero angle with the front face; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face; and after the thinning, bending the free conducting end projecting from the back face.

Claims

1. A method of making one or several connection elements for a microelectronic device, comprising: forming a conducting layer on a support on which there are one or several conducting pads located on a front face of the support opposite a back face thereof, the conducting layer comprising a first conducting portion in contact with at least one conducting pad located on the front face, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support, the at least one given wall being located between the front face and the back face and forming a non-zero angle with the front face of the support; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face of the support; and after the thinning of the support, bending the free conducting end projecting from the back face of the support.

2. The method according to claim 1, wherein the support comprises at least one trench opening up at a front face thereof, the at least one given wall being a lateral wall of the at least one trench.

3. The method according to claim 2, wherein the at least one trench comprises a bottom located between the front face and the back face of the support, the thinning being performed to reach the bottom of the trench.

4. The method according to claim 1, wherein the support comprises at least one trench opening up on a front face thereof, the at least one given wall being a lateral wall of the at least one trench, the conducting layer being deposited in a bottom and on lateral walls of the at least one trench.

5. The method according to claim 1, wherein the at least one given wall is coated with an insulating layer before formation of the conducting layer.

6. The method according to claim 1, wherein the support comprises at least one trench opening up on a front face thereof, the at least one given wall being a lateral wall of the at least one trench, the lateral wall forming an angle of less than 90 with the front face.

7. The method according to claim 1, further comprising, between the forming of the conducting layer and the thinning of the support, transferring a backing substrate or a backing layer on the front face of the support.

8. The method according to claim 1, wherein the support comprises at least one trench opening up on a front face thereof, a first electronic chip, and a second electronic chip, the at least one trench being located between the first electronic chip and the second electronic chip, the method further comprising, after the thinning of the support, separating the first electronic chip and the second electronic chip.

9. The method according to claim 1, wherein the support comprises at least one trench opening up on a front face thereof, the method further comprising, between the forming of the conducting layer and the thinning of the support, forming conducting patterns in the conducting layer.

10. The method according to claim 9, wherein the at least one given wall is a lateral wall of the at least one trench, the method further comprising locally removing the conducting layer to define discontiguous conducting elements along the lateral wall of the at least one trench.

11. The method according to claim 1, wherein the free conducting end is bent to bring the free conducting end towards the back face.

12. The method according to claim 1, wherein the bending is performed at least partly by addition of heat.

13. The method according to claim 12, wherein the conducting layer is formed from a stack of at least one first material and at least one second material in contact with the at least one first material and having a coefficient of thermal expansion that is greater than that of the at least one first material.

14. The method according to claim 1, wherein the bending: includes mechanical pressurisation of the free conducting end against an inclined lateral flank of a cavity against which the support bears, and/or is performed using a gripping device configured to heat the support while applying the heat in contact with another support.

15. The method according to claim 1, wherein the support comprises at least one trench opening up on a front face thereof, the at least one trench delimiting a chip located in the support, the at least one given wall being a lateral wall of the at least one trench, the method further comprising, after the thinning: separating the chip by cutting along the at least one trench, and assembling the chip on a structure provided with at least one conducting pad, such that the free conducting end projecting from the back face of the support is brought into contact with the at least one conducting pad.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) This invention will be better understood after reading the description of example embodiments given purely for information and that are in no way limitative with reference to the appended drawings on which:

(2) FIG. 1 illustrates an assembly and connection step between a chip and a support based on a technique according to prior art;

(3) FIGS. 2A-2F are cross-sectional views illustrating a method aimed at forming conducting elements connected to the front face of a support and provided with a free conducting end at the back face of the support;

(4) FIGS. 3A-3E are top views illustrating a method according to one embodiment of this invention;

(5) FIGS. 4A-4H are three-quarter views illustrating a method according to one embodiment of this invention;

(6) FIGS. 5A-5B illustrate a method of bending the free conducting end of conducting elements;

(7) FIGS. 6A-6B illustrate an assembly of the conducting end of conducting elements projecting from the back face of a support with another device, after bending;

(8) FIGS. 7A-7D illustrate a variant embodiment in which a chip or support gripping device is configured to heat conducting elements on this chip or this support so as to curve them and then pressurise them in contact with another device;

(9) FIG. 8 illustrates a variant embodiment of the method according to the invention for which the initial device is a reconstituted support;

(10) FIG. 9 illustrates a variant embodiment of the method according to the invention in which holes are formed along lateral walls of the trenches in order to separate conducting zones formed on these walls;

(11) FIGS. 10A-10B illustrate a variant embodiment of the method according to the invention in which connection elements passing through the lateral edges of a chip are formed directly on the chip before it is thinned;

(12) FIGS. 11 and 12 illustrate assemblies of chips with lateral edges making an acute angle with their front face, the connection between a first chip and a second chip being made by means of connection elements running along the lateral edges of the first chip;

(13) FIGS. 13A-13E illustrate a method making a chip with lateral edges making an acute angle with its front face and provided with conducting elements extending on its lateral edges;

(14) Identical, similar or equivalent parts of the different figures have the same numeric references to facilitate comparison between the different figures.

(15) The different parts shown on the figures are not necessarily all at the same scale, to make the figures more easily understandable.

(16) Furthermore, in the following description, terms that are dependent on the orientation such as lateral, front, back, bottom, etc. of a structure should be understood assuming that the structure is oriented as shown on the figures.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

(17) An example of the method according to one embodiment of this invention for use of a device comprising one or several connection elements projecting from the back face of a support and connected to one or several corresponding conducting pads located on the front face of this support will now be described with reference to FIGS. 2A-2F, 3A-3E, 4A-4H that shown cross-sectional views, top views, and three-quarter views respectively of the device during manufacturing.

(18) The description starts with reference to FIGS. 3A and 4A that illustrate a possible initial device for the method in the form of a support 1 composed of a plate 2 or a substrate 2, for example based on a semiconductor material. The support 1 may comprise elements 1.1, 1.2, 1.3 that will be separated from each other, for example such as electronic chips or integrated circuits or electronic components that may or may not be identical to each other.

(19) As illustrated on FIG. 2A, the support 1 may also be provided with one or several active parts of chips provided with discontiguous conducting pads 4a, 4b, 4c respectively, on one of the front faces that will be denoted the front face F1.

(20) One or several trenches 7a, 7b are firstly made through the front face of the support 1 (FIGS. 2A and 3B). The trenches 7a, 7b delimit the elements 1.1, 1.2, 1.3 of the support that will be separated from each other. In one embodiment illustrated on FIG. 4B, the trenches 7a, 7b may be formed by sawing.

(21) The trenches 7a, 7b are preferably made such that they do not pass through the entire thickness of the support 1. In this description, the thickness is a dimension measured between the front face F1 and a face called the back face F2 opposite the front face, along a direction parallel to the vector z of an orthogonal coordinate system [O; x; y; z].

(22) The trenches 7a, 7b thus comprise a bottom 8 located in the thickness of the support 1 and lateral walls 9 that extend in a direction making a non-zero angle with the front face and/or the back face of the support. In the particular example in FIG. 2A, the lateral walls 9 of the trenches 7a, 7b extend along a direction orthogonal to the front face F1 and the back face F2 of the support 1. However, the angle between the lateral

(23) walls 9 and the front face F1 or the back face F2 may be different from 90.

(24) The next step is to form an insulating layer 11 on the front face of the support 1. In the particular example illustrated on FIG. 2B, the insulating layer 11 made is distributed so as to cover the bottom 8 and the lateral walls 9 of the trenches 7a, 7b.

(25) Some regions of the conducting pads 4a, 4b, 4c may also be coated. The insulating layer 11 comprises openings exposing other regions of active parts of chips, and particularly the conducting pads 4a, 4b, 4c. For example, such a discontinuous insulating layer 11 could be made using deposition and photolithography steps. For example, the insulating layer 11 may be based on an inorganic dielectric material or a polymer to make it more flexible.

(26) The next step is to form a conducting layer 14 on the front face F1 of the support 1. The conducting layer 14 made can be discontinuous and formed from distinct conducting zones, in other words discontiguous zones with no connection between them.

(27) One possible method for making this conducting layer 14 is to make a preliminary deposit of a germination layer 14a for example based on Ti and Cu on the front face F1 of the support 1 (FIGS. 3C and 4C). For example, this deposition can be made by PVD (Physical Vapour Deposition).

(28) Masking elements 17, for example based on photosensitive resin, are then formed for example by photolithography, on zones of the germination layer 14a located facing the active parts of each of the chips (FIGS. 3D, 4D).

(29) A metallic layer 14b, for example based on copper, is then formed by metallisation of exposed regions of the germination layer 14a that are not protected by masking elements 17 (FIG. 2C).

(30) The masking elements 17 are then removed (FIG. 4E), and the areas of the germination layer 14a that are not covered by the metallic layer 14b are then etched (FIG. 4F). Patterns can be made in the conducting layer 14, for example by etching or laser ablation.

(31) The conducting layer 14 thus made comprises a conducting portion 14.1 in contact with a conducting pad 4a located on the front face of the support, the conducting portion 14.1 extending on the front face and being connected to another conducting portion 14.2 that extends on a wall that makes a non-zero angle with the front face.

(32) In the example embodiment in FIG. 2C, the other conducting portion 14.2 extends along a lateral wall 9 of the trench 7a and may be connected to a conducting portion 14.3 coating the bottom 8 of the trench 7a, itself connected to a conducting portion 14.4 located along another lateral wall 9 of the trench 7a.

(33) Thus, in the example given in FIG. 2C, the conducting layer 14 made is distributed so as to cover the bottom 8 and the lateral walls 9 of the trenches 7a, 7b, and said other regions of the active parts of chips and particularly of conducting pads 4a, 4b, 4c exposed through openings 12 provided in the insulating layer 11.

(34) Other arrangements in which the conducting layer 14 partially covers the trenches 7a, 7b and/or covers a lateral wall F3 of the support 1 can also be provided. As a variant, the conducting portion 14.3 at the bottom of the trench is not necessarily made, if a deposition is made under oblique incidence.

(35) The next step is thinning of the support 1 from its back face F2. In the example embodiment illustrated on FIGS. 2D and 4G, this thinning is done so as to reach the bottom 8 of the trenches 7a, 7b.

(36) In this case, a portion 14.3 of the conducting layer 14 located at the bottom of the trenches can be deleted. The conducting portions 14.2 and 14.4 of the conducting layer located on the lateral walls of the trenches are then separated from each other.

(37) As illustrated in the particular example embodiment in FIG. 2D, a so-called mechanical backing layer 23 added on prior to thinning may be applied on the front face F1 of the support 1 in order to keep elements 1.1, 1.2, 1.3 of the support 1 together and/or to prevent breakage of the support 1 during thinning. As a variant, a handle substrate may be provided to make the mechanical backing.

(38) An example method of making this thinning includes a grinding step of the support.

(39) Thinning may then be continued as illustrated on FIG. 2E, so as to release the ends 15a, 15b of conducting portions 14.2, 14.4 formed on the lateral walls of trenches. These free conducting 15a, 15b project from the back face F2 of the support 1 and are not in contact with the support 1. This additional removal of a portion of the support 1 at its back face F2 may for example be made by etching. Fluorinated plasma etching may be possible, for example if the support 1 is based on silicon.

(40) The conducting ends 15a, 15b thus released may then be connected to conducting zones of another support.

(41) After the support 1 has been thinned at its back face and the ends 15a, 15b of the conducting portions have been released, the chips or integrated circuits or components 1.1, 1.2, 1.3 can be released from the support 1.

(42) Separation may include removal of the backing layer 23. This removal may be made particularly by a mechanical action, for example by peeling off this layer 23.

(43) An additional cut of the support 1 may then be made to separate the chips 1.1, 1.2, 1.3 from each other. This cut may be made along cut planes that cross the trenches 7a and 7b and extend orthogonally to the trenches 7a, 7b.

(44) Cut planes on FIGS. 2F and 3E are shown by dashed lines.

(45) In one example embodiment illustrated on FIG. 4H, this separation is made by sawing.

(46) Finally, the result obtained is chips 1.1, 1.2, 1.3 provided with distinct connection elements 16a, 16b located on the front face F1 of the chips and that extend on each side of the chips along their lateral walls F3 or lateral edges F3. The connection elements 16a, 16b comprise ends 15a, 15b projecting beyond the back face F2 and that can be connected with another device or another support.

(47) An example of a process like that described above is particularly suitable for the production of connection elements on a support 1 or thin chips 1.1, 1.2, 1.3, for example between 50 and 200 m thick.

(48) A variant of the method that has just been described allows for the use of a reconstituted support as the initial device, as described for example in document WO 2008/155231 and comprising a wafer 80 or a board based on glass or polymer silicon provided with cavities inside which chips 1.1, 1.2, 1.3 or components or integrated circuits are housed and are attached to the wafer by means of an adhesive 84.

(49) In the example embodiment illustrated on FIG. 4H, the connection elements 16a, 16b formed on the chips 1.1, 1.2, 1.3 extend along the entire length L (measured parallel to the coordinate system [O; x; y; z]) of their edges or lateral flanks.

(50) As a variant, connection elements 16a or 16b that extend along only a portion of the lateral edges of a chip 1.2 or 1.3 can be made by forming holes 91 in the lateral walls of the trenches after metallisation of the trenches and before the step to separate chips 1.2, 1.3.

(51) Such a variant is illustrated on FIG. 9 that shows a top view of a trench 7b separating the lateral edges of the two chips 1.2 and 1.3. Several discontiguous connection elements 16a, 16a, 16a or 16b, 16b, 16b that are not connected to each other can thus be made on the lateral edges of each chip.

(52) According to another example embodiment, independent and discontiguous connection elements 16a 16a, 16a can be defined running along the same side wall of a trench, for example by laser ablation.

(53) It would also be possible to facilitate assembly and connection of a chip 1.1 with a different backing once the support has been cut, by bending the free conducting ends 15a, 15b of the connection elements.

(54) A method of bending the free conducting ends 15a, 15b projecting from the back face of a chip 1.2 or an integrated circuit 1.2 once the support 1 has been cut out is illustrated on FIGS. 5A-5B.

(55) In this example, this bend is made so as to bring the conducting ends 15a, 15b of the connection elements 16a, 16b towards the back face F2 of the chip 1.2. This is done by bringing these free conducting ends 15a, 15b into contact under pressure with the inclined lateral flanks 53 of a cavity 51 formed in a support 50. This support 50 then acts as a press, against which the chip 1.2 is pressed.

(56) The chip 1.2 may be gripped and forced into contact with the support 50 by means of a robot-controlled unit of the type commonly called pick and place.

(57) Once the curved conducting ends 15a, 15b are under the chip 1.2, this chip 1.2 can be assembled with another device such as a Printed circuit board (PCB) or a PCB inserter or another identical or different chip.

(58) FIGS. 6A-6B illustrate an example of such an assembly type in which the free conducting ends 15a, 15b partially curved towards the back face F2 of the chip are then pressed in contact with the conducting ends 65a, 65b of an interconnection substrate 60. The result is that the connecting elements 16a, 16b of the chip 1.2 are brought into electrical contract with the conducting areas 65a, 65b of the substrate 60, and the conducting ends 15a, 15b are brought into mechanical contact with the back face of the chip 1.2.

(59) The result obtained is thus a compact assembly and a connection between the substrate 60 and the chip 1.2.

(60) As a variant or in combination with a mechanical action, the conducting ends 15a, 15b may be bent by the addition of heat.

(61) In this case, the conducting ends 15a, 15b can advantageously be formed from a stack of conducting materials in contact with each other and with different coefficients of thermal expansion.

(62) A Ti and Cu stack can for example be made to form a conducting layer 14 based on which the conducting ends 15a, 15b are formed, given that the ratio between the coefficients of thermal expansion of these materials is of the order of 2.

(63) In using a conducting layer 14 composed of a bilayer with the properties of a bimetallic strip, a partial curvature effect can be obtained at the free conducting ends 15a, 15b when sufficient heat is added. For example for a Ti/Cu bimetallic strip, the temperature is preferably set to more than 100 C., for example equal to 200 C. or more.

(64) It would also be possible to adapt the method of making the conducting layer 14 to facilitate bending of the conducting ends 15a, 15b, particularly when the conducting layer 14 is formed from a stack of different materials.

(65) The different methods mentioned above to facilitate bending can be combined.

(66) FIGS. 7A-7D illustrate an example of an assembly between the chip 1.2 and a support 60 making use of a device 100 configured to take the chip 1.2 (FIG. 7A), and then heat the chip 1.2 so as to cause a curvature between the conducting ends 15a, 15b (FIG. 7B), apply pressure between the chip 1.2 and the conducting areas 65a, 65b of the substrate 60 while continuing to input heat (FIG. 7C).

(67) Soldering is possible depending on the nature of the materials to be assembled. Once the assembly and the connection between the chip 1.2 and the substrate 60 have been made, the device 100 releases the chip (FIG. 7D).

(68) For example, the device 100 used may be a pick and place type robot fitted with heating gripping means.

(69) FIGS. 10A, 10B illustrate another variant embodiment in which the connection elements 16a, 16b are formed on a previously cut individual chip 1.2. The connection elements 16a, 16b located on the front face of the chip extend on each side of the chip along the lateral edges or lateral walls F3 of the chip (FIG. 10A). The next step is to thin the chip 1.2 at its back face F2, so as to release the ends of the connection elements 16a, 16b from the chip 1.2 (FIG. 10B).

(70) On FIG. 11, a superposition of chips 1.1, 1.2, 1.3 has been made in which each chip 1.1, 1.2, 1.3 is provided with connection elements 16a, 16b on its front face and that extend on each side of the chip along the lateral edges or lateral walls F.sub.3 of the chip. In this particular embodiment, the lateral edges or lateral walls F.sub.3 of the chips 1.1, 1.2, 1.3 make an angle less than 90, for example between 75 and 85 with their front face F.sub.1.

(71) The cross-section of the chips 1.1, 1.2, 1.3 may be approximately in the shape of a trapezium in which the largest base is the front face F.sub.1 of the chip and the smallest base is the back face F.sub.2 of the chip.

(72) The fact that there is an acute angle between a lateral edge F.sub.3 of a chip 1.1 and its front face F.sub.1 can facilitate the connection between a connection element 16a, 16b that extends on its front face F.sub.1 and on a lateral edge F.sub.3 and a conducting zone of another device that is placed facing the back edge of the face F.sub.2 of the chip 1.1.

(73) In the particular embodiment shown in FIG. 11, the free ends 15a, 15b of the connection elements 16a, 16b of a chip 1.1 are thus connected to other connection elements 16a, 16b of another chip 1.2 on the front face of this other chip 1.2. In this case the free ends 15a, 15b of the connection elements 16a, 16b of a chip 1.1 are connected without necessarily being bent towards the back face F.sub.2 of this chip 1.1.

(74) FIG. 12 illustrates a more compact assembly, in this case with the ends 15a, 15b of the connection elements 16a, 16b of a chip 1.1 that are folded and that extend along a portion of the back face F.sub.2 of this chip 1.1.

(75) An example method of making the chips 1.1, 1.2, 1.3 with inclined lateral edges as illustrated on FIG. 11 or 12 will now be described with reference to FIGS. 13A-13E.

(76) The method can be started using the same starting device as in the example method described above with reference to FIGS. 2A-2F.

(77) One or several trenches 77a, 77b are firstly made through the front face F1 of the support 1 (FIG. 2A). In this example, the trenches 77a, 77b comprise a bottom 8 located in the thickness of the support 1 and lateral walls 9 that extend in a direction making an angle less than 90 with the front face F.sub.1 of the support. Thus, the bottom 8 of the trenches 77a, 77b is wider than their opening. The trenches 77a, 77b delimit separation zones between chips 1.1, 1.2, 1.3.

(78) When the support 1 is semiconducting and for example based on silicon, the trenches 77a, 77b can be made for example using a method of the type described in document U.S. Pat. No. 5,501,893 or in the High aspect ratio Bosch etching of sub 0.25 m trenches for hyperintegration document by Wang et al., Journal of Vacuum Science and Technology B 25, 1376 (2007).

(79) The next step is to form the insulating layer 11 on some areas of the front face of the support 1. The insulating layer 11 in this example covers the bottom 8 and the lateral walls 79 of the trenches 77a, 77b (FIG. 13B).

(80) The next step is to form a conducting layer 14 on some regions of the front face F.sub.1 of the support 1 that are not covered by masking elements 17 formed beforehand for example by photolithography. The conducting layer 14 in this example coats the bottom 8 and the lateral walls 79 of the trenches 77a, 77b (FIG. 13C).

(81) The conducting layer 14 thus made comprises a conducting portion 14.1 in contact with a conducting pad 4a located on the front face of the support, the conducting portion 14.1 extending on the front face and being connected to another conducting portion 14.2 that extends on a wall that makes an acute angle with the front face.

(82) The next step is thinning of the support 1 at its back face F2. In the example embodiment illustrated on FIGS. 13C and 13D, this thinning is done so as to reach and eliminate the bottom 8 of the trenches 77a, 77b.

(83) A mechanical backing means, for example in the form of a handle substrate or a deposited layer 23 can be formed on the front face F1 of the support 1 before thinning so that this step can be done without damaging the support 1.

(84) The thinning step may then be prolonged or may also include etching, as illustrated on FIG. 13E, so as to release the ends 15a, 15b of conducting portions formed on the lateral walls of trenches 77a, 77b. These free conducting ends 15a, 15b project from the back face F2 of the support 1 and are not in contact with the support 1. The conducting ends 15a, 15b thus released may then be connected to conducting zones of another support, for example a substrate or another chip.

(85) The support may be cut before assembly with another support, so as to dissociate the chips 1.1, 1.2, 1.3. This cut is advantageously made along trenches 77a, a lateral wall of a trench then forming a lateral edge of a chip.