Fabrication method for digital etching of nanometer-scale level structures
09997555 ยท 2018-06-12
Assignee
Inventors
- Marc Christophersen (Berwyn Heights, MD, US)
- Bernard F. Phlips (Great Falls, VA, US)
- Michael K. Yetzbacher (Burke, VA, US)
Cpc classification
H01L27/14625
ELECTRICITY
G02B5/1857
PHYSICS
International classification
H01L21/00
ELECTRICITY
H01L21/02
ELECTRICITY
H01L21/311
ELECTRICITY
H01L27/00
ELECTRICITY
Abstract
A device includes a surface profile optical element, including a substrate and a plurality of bi-layer stacks on the substrate. Each bi-layer stack of the plurality of bi-layer stacks includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch-stop layer and a bulk layer. The etch stop layer includes an etch stop layer index of refraction. The bulk layer includes a bulk layer index of refraction. A ratio of the etch stop layer index of retraction and the bulk layer index of refraction is between 0.75 and 1.25.
Claims
1. A device comprising: a surface profile optical element comprising a substrate and a plurality of bi-layer stacks on said substrate, each bi-layer stack of said plurality of bi-layer stacks comprising a plurality of bi-layers, each bi-layer of said plurality of bi-layers comprising an etch-stop layer and a bulk layer, said etch stop layer comprising an etch stop layer index of refraction, said bulk layer comprising a bulk layer index of refraction, a ratio of said etch stop layer index of refraction and said bulk layer index of refraction being between 0.75 and 1.25, wherein said plurality of bi-layer stacks comprise a top surface roughness less than 10 nm root mean squared.
2. The device according to claim 1, wherein said substrate comprises one of a focal plane array, a CMOS imager, a CCD array, and a semiconductor device, wherein said surface profile optical element comprises one of a wavefront coding element, an aspheric optical element, and a diffractive optical element.
3. The device according to claim 1, wherein said substrate is transparent.
4. The device according to claim 1, wherein said etch stop layer comprises alumina, and said bulk layer comprises a silicon-based dielectric.
5. The device according to claim 1, wherein at least one bi-layer stack of said plurality of bi-layer stacks comprises a thickness greater than 200 nm.
6. The device according to claim 1, further comprising a beamsplitter, said beamsplitter comprising said surface profile optical element.
7. The device according to claim 1, further comprising: an integrated-display glass comprising said surface profile optical element.
8. The device according to claim 7, wherein said integrated-display glass comprises one of a window, a windshield, a helmet, and an eyeglass.
9. The device according to claim 1, further comprising a beam shaper, said beam shaper comprising said surface profile optical element.
10. The device according to claim 9, wherein said beam shaper comprises a Fresnel lens.
11. The device according to claim 9, wherein said beam shaper comprises a phase shift photomask mold master.
12. The device according to claim 9, wherein said beam shaper comprises a wavefront distortion corrector plate.
13. The device according to claim 1, further comprising: a lens, wherein said surface profile optical element is operably connected to said lens.
14. The device according to claim 13, wherein said lens comprises an optical transfer function, wherein said surface profile optical element comprises a wavefront coded surface for said lens, said wavefront coded surface modifying the optical transfer function.
15. The device according to claim 13, further comprising: a spiral phase plate comprising said surface profile optical element.
16. The device cording to claim 13, further comprising: a phase contrast microscopy phase mask comprising said surface profile optical element.
17. A method of fabricating a multiple-step, surface profile optical element, the method comprising: depositing a bi-layer stack on a substrate, the bi-layer stack comprising a plurality of bi-layers, each bi-layer of the plurality of bi-layers comprising an etch stop layer and a bulk layer, wherein the etch stop layer and the bulk layer have respective indices of refraction that approximate each other, forming a three-dimensional photoresist structure by using gray-tone lithography; plasma etching the three-dimensional photoresist into the bi-layer stack, thereby generating an etched bi-layer stack; and chemically etching the etched bi-layer stack with a first chemical etchant so as to generate a multiple-step, surface profile optical element, wherein the first chemical etchant stops at the etch stop layer.
18. The method according to claim 17, further comprising: providing the multi-step, surface profile optical element as a mold master; applying a coating onto the mold master; solidifying the coating, and removing the solidified coating thereby generating a surface profile optical element-imprinted mold.
19. The method according to claim 18, wherein said coating includes at least one of a polymer, a plastic, a ceramic, and a glass.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF THE INVENTION
(22) The invention relates to micro-fabrication of surface profile optical elements, such as precise standard wavefront coding elements, standard aspheric optical elements, and standard diffractive optical elements.
(23) Wavefront coding (WC) or phase masking is a technique used to engineer or otherwise alter the point spread function of an optical imaging system, or to change the angular sensitivity profile of an instrument. It has often been applied to make instruments more insensitive to optical aberrations such as defocus. It has also been commonly used to exclude on-axis light from a bright source by using a spiral phase plate (SPP), thereby, allowing observation of for example, extra-solar planets.
(24) Aspheric optical elements are known to have advantages relative to spherical optics in reduced aberrations, fewer optical elements, but are expensive to manufacture. The manufacture of aspheres (or aspheric lens) is usually through precision molding or polishing, or through diamond machining. The surface quality that can be achieved for aspheric elements is less than that which can be achieved for spheric elements, due to the difficulty of fabricating a material with arbitrary surface profile. The use of aspheric elements in high-performance optical designs is now standard in the industry, despite their cost relative to spherical elements.
(25) Diffractive optical elements are thin phase elements that are designed to, by means of interference and diffraction, produce arbitrary distributions of light or to aid in the design of optical systems. Diffractive lenses can be used, for example, to reduce the number of elements in conventional lens systems and eliminate the need for exotic materials in correcting chromatic aberrations. Applications of DOEs range from fiber optic communication to laser beam shaping.
(26) All of the optical elements mentioned above have in common the use of material thicknesses to control the phase of a transmitted or reflected beam.
(27) An embodiment of the invention includes a device that is described as follows, as shown by way of illustration in
(28) Optionally, as shown by way of illustration in
(29) Optionally, substrate is transparent.
(30) Optionally, the plurality of bi-layer stacks 20 includes a top surface roughness less than 10 nm root mean squared (rms).
(31) Optionally, the etch stop layer 40 includes alumina, and the bulk layer 50 includes a silicon-based dielectric, such as silicon dioxide and silicon nitride.
(32) Optionally, at least one bi-layer stack of the plurality of bi-layer stacks 20 includes a thickness greater than 200 nm.
(33) Optionally, as shown by way of illustration in
(34) Optionally, as shown by way of illustration in
(35) Optionally, as shown by way of illustration in
(36) Optionally, as shown by way of illustration in
(37) Optionally, as shown by way of illustration in
(38) Optionally, as shown by way of illustration in
(39) Another embodiment of the invention includes a method of fabricating a multiple-step, surface profile optical element. The method is described as follows, with reference by way of illustration only to
(40) Optionally, the multi-step, surface profile optical element is provided as a mold master, as shown by way of illustration in
(41) As to the mold master, an embodiment of the invention provides for the micro-fabrication of a mold-master with a low surface roughness. Under optimized molding conditions, this low roughness will transfer to the final workpiece.
(42) Another embodiment of the invention includes a method of fabrication and is describes as follows, with reference by way of illustration to
(43) 1) stack deposition;
(44) 2) gray-tone lithography;
(45) 3) structure transfer; and
(46) 4) selective chemical etching.
(47) A stack of materials is deposited by standard thin film deposition techniques, e.g., low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or sputtering. The stack includes two materials: A and B. Material A is always deposited on top of Material B. The stack includes multiple A-B bi-layers. One of ordinary skill in the art will readily recognize that Material A and Material B must be selected such that their electrical properties match the application of the device constructed according to this embodiment of the invention. One or both materials of the stack (e.g. B) additionally act as an etch stop, as described below. For example, silicon oxide (SiO.sub.2) and alumina (Al.sub.2O.sub.3) are used as Materials A and B for the bi-layers for a particular application. Both materials are deposited by ALD with 15 nm and 5 nm thicknesses. As another example, PECVD-deposited silicon dioxide (SiO.sub.2) and silicon nitride (Si.sub.3N.sub.4) are alternatively used as bi-layer materials for a different application. The number of design levels is determined by the number of bi-layers within the stack and the geometry of the gray-tone photoresist structure.
(48) As to the choice of bi-layer materials, although the discussion above includes alumina/silicon dioxide and silicon nitride/silicon dioxide as material combinations for our bi-layer stack, one of ordinary skill in the art will readily recognize the utility of alternative material combinations for alternative applications. For example, a different dielectric material (e.g. a metal oxide) is optionally used for alternative applications. As another example, conducting layers are optionally used for alternative applications. The only common requirement for the material combinations is that one material can be selectively etched with respect to the other one.
(49) As described above, standard gray-tone lithography is ideal for the fabrication of 3D microstructures. The developed photoresist is then processed, for example by standard etching, to reproduce a scaled version of the 3D microstructure on the substrate. As the etch proceeds, the photoresist mask slowly erodes, exposing the underlying dielectric to the high etch rate plasma. After transferring the gray-tone resist into the stack a standard chemical etch is performed. The standard chemical selectively only etches one material of the bi-layer (e.g. if Material A is etched, Material B is not). This selective chemical etch step will transform the 3D microstructure into distinct steps. For example, vapor HF (hydrofluoric acid) is used to etch SiO.sub.2 selectively over the alumina (with an etch time of 30 sec for a 15 nm SiO.sub.2 layer). This leads to digitally distinct steps at a resolution controlled by the deposition of the bi-layer stack.
(50) Because the last process step is a highly selective chemical etch, the top surface roughness for 3D microstructures fabricated according to this embodiment of the invention is extremely low. For example, an illustrative 3D microstructure as measured with atomic force microscopy (AFM) evidences distinct levels of 0.3 nm rms surface roughness with controlled 3D features.
(51) In another example of a method according to this embodiment of the invention, the gray-tone lithography uses a Novolak resist (AZ P4330 Clariant, 3 m thick). According to a standard soft-bake procedure, the wafer, or substrate, is heated to 100 C. for 60 s on a hotplate to remove solvents from the resist prior to UV exposure. Diffuser-based gray-tone lithography is used with a 15 second exposure time. According to standard development procedures, the standard resist is developed using the standard puddle method. 1:4 de-ionized (DI) water to 400K AZ developer is used for 40 sec and is followed by a thorough DI water rise. After development, the resist is hard-baked at 150 C. for 120 seconds. The hard-bake makes the resist more resistant during a subsequent reactive-ion etching (RIE) etching step.
(52) The gray-tone resist patterns are transferred into the stack via an inductively coupled plasma (ICP) RIE etch step. The ICP etch was performed using an Oxford 100 fluorine etcher (30 sccm CF.sub.4, 20 mTorr, 20 W FW power, 500 W ICP power, 90 min etch time).
(53) Vapor HF (hydrofluoric acid) is used for the chemical etching (e.g., using a Primaxx Etch System). Vapor HF only etches the silicon oxide and leaves the alumina intact. Hydrofluoric acid's reaction with SiO.sub.2 forms water acting as a catalyst which will cause aqueous HF to etch the alumina. Commercial HF vapor etch systems minimize the formation of HF(aqu.) by injecting alcohol into the system. Optionally, diluted phosphoric acid etch steps (70 C) are added. The phosphoric acid etches the alumina layer.
(54) For an oxide/nitride stack, boiling phosphoric acid is used to etch the nitride layer. The SiO.sub.2 is again etched using vapor HF.
(55) As to chemical etching, although the discussion above includes the use of vapor HF to perform the selective chemical etching, one of ordinary skill in the art will readily recognize the utility of alternative standard wet or dry (e.g., reactive ion etch or ion-milling) etching techniques.
(56) As to gray-tone lithography, although the discussion above includes a HEBS mask and diffuser based gray-tone lithography, one of ordinary skill in the art will readily recognize the utility of alternative standard ways to generate a 3D resist profile.
(57) As to multiple lithography etching step cycles, one of ordinary skill in the art will readily recognize the utility of multiple lithography etching step cycles on a bi-layer stack. After the last etch step, the chemical etch step would generate a surface with a low surface roughness.
(58) Although a particular feature of the disclosure may have been illustrated and/or described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms including, includes, having, has, with, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term comprising.
(59) This written description sets forth the best mode of the invention and provides examples to describe the invention and to enable a person of ordinary skill in the art to make and use the invention. This written description does not limit the invention to the precise terms set forth. Thus, while the invention has been described in detail with reference to the examples set forth above, those of ordinary skill in the art may effect alterations, modifications and variations to the examples without departing from the scope of the invention.
(60) These and other implementations are within the scope of the following claims.