Semiconductor device with optical and electrical vias
09995894 ยท 2018-06-12
Assignee
Inventors
Cpc classification
G02B6/43
PHYSICS
H01L2224/16225
ELECTRICITY
G02B6/13
PHYSICS
H01L31/16
ELECTRICITY
H05K2201/0939
ELECTRICITY
H05K1/0274
ELECTRICITY
H05K1/115
ELECTRICITY
H05K2201/09581
ELECTRICITY
H01L23/481
ELECTRICITY
H01L23/522
ELECTRICITY
H05K1/116
ELECTRICITY
H05K3/429
ELECTRICITY
H05K2201/09518
ELECTRICITY
International classification
H01L23/48
ELECTRICITY
H01L21/00
ELECTRICITY
H05K1/11
ELECTRICITY
G02B6/13
PHYSICS
H01L31/16
ELECTRICITY
Abstract
The method comprises providing a semiconductor substrate, which has a main surface and an opposite further main surface, arranging a contact pad above the further main surface, forming a through-substrate via from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through-substrate via above the contact pad, arranging a hollow metal via layer in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer in the further through-substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.
Claims
1. A method of producing a semiconductor device with optical via and electrical via, comprising: providing a semiconductor substrate having a main surface and an opposite further main surface with a contact pad arranged below the further main surface; forming a through-substrate via from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through-substrate via from the main surface to the further main surface the contact pad; arranging a hollow metal via layer in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer in the further through-substrate via, the further metal via layer contacting the contact pad; and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.
2. The method of claim 1, wherein the metal via layer is formed having a thickness in the through-substrate via; and the further metal via layer is formed having a further thickness in the further through-substrate via, so that the thickness and the further thickness are the same.
3. The method of claim 1, further comprising: forming a dielectric sidewall layer for the through-substrate via and, by the same method step together with the dielectric sidewall layer, forming a further dielectric sidewall layer for the further through-substrate via; arranging the metal via layer on the dielectric sidewall layer, so that the dielectric sidewall layer insulates the metal via layer from the semiconductor substrate; and arranging the further metal via layer on the further dielectric sidewall layer, so that the further dielectric sidewall layer insulates the metal via layer from the semiconductor substrate.
4. The method of claim 3, wherein an arrangement of the metal via layer and the dielectric sidewall layer in the through-substrate via is similar to an arrangement of the further metal via layer and the further dielectric sidewall layer in the further through-substrate via.
5. The method of claim 1, further comprising: arranging a dielectric cover layer on the metal via layer, the dielectric cover layer laterally surrounding the through-substrate via.
6. The method of claim 1, further comprising: arranging a dielectric layer covering the further metal via layer in the further through-substrate via.
7. The method of claim 6, wherein the dielectric layer is arranged without filling the further through-substrate via.
8. The method of claim 1, wherein the through-substrate via is formed in the shape of a hollow cylinder surrounding a semiconductor pillar of the substrate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1)
(2)
(3)
(4)
(5)
(6)
DETAILED DESCRIPTION
(7)
(8) A metal wiring 7 is embedded in the dielectric layer 2, and a further metal wiring 8 is embedded in the further dielectric layer 3. The wirings 7, 8 may comprise one or more structured metallization layers and vertical interconnections and may serve as electrical connections of terminals of electronic components integrated in the substrate 1. A top metal layer 9 forms a contact for an external electrical connection of a through-substrate via 14, which is provided as an electrical interconnection through the substrate 1. The electrical through-substrate via 14 comprises a further metal via layer 15, which is optionally insulated form the semiconductor material of the substrate 1 by a further dielectric sidewall layer 16. The further metal via layer 15 is electrically connected with a contact pad 19, which is arranged on the further dielectric layer 3 or embedded in the further dielectric layer 3. The contact pad 19 can be part of the further wiring 8 and can thus especially be connected with terminals of integrated components and/or with further contact pads for external electrical connection.
(9) Bump contacts 17 on the metal wiring 7 serve as electrical connections to an optical device 10 mounted above the main surface 12. The optical device 10 may be a vertical cavity surface emitting laser, a photodiode or a wave guide component, for instance. Further bump contacts 18 on the further metal wiring 8 serve as electrical connections to a further optical device 20 mounted above the further main surface 13. The further optical device 20 may also be a vertical cavity surface emitting laser, a photodiode or a wave guide component, for instance. If the optical device 10 is a light emitting device like a VCSEL, for instance, the further optical device 20 may be a photodiode, for instance. The light is emitted in the direction of the light path 11 through the optical via 4 and may be focused into the light receiving area of the photodiode by a lens 23 arranged on the surface of the further dielectric layer 3. Such a lens 23 can be formed by imprinting techniques, especially by nano-imprinting techniques known per se, or it can be mounted as a separate device during assembly of the optical module.
(10) The embodiment according to
(11) The boundary between the dielectric sidewall layer 6 and the metal via layer 5 or the boundary between the metal via layer 5 and the dielectric cover layer 22 may be used for the propagation of light through the optical via 4 by means of surface plasmon-polaritons (SPPs). SPPs are collective charge oscillations generated at the interface of a dielectric and a metal by incident photons coupling with surface plasmons. SPPs sustain the propagation of electromagnetic waves along the interface between the dielectric and the metal. A metal via layer 5 of gold or copper may be suitable in this embodiment for the generation of SPPs.
(12) The optical via 4 and the electrical through-substrate via 14 have similar structures except for the optical via 4 being open at both ends, whereas the electrical through-substrate via 14 is closed by the contact pad 19. Because of the structural similarities, one or more optical vias 4 and one or more electrical through-substrate vias 14 can be produced together with essentially the same method steps.
(13) In the method of production, via holes are etched through the substrate 1 from the main surface 12. At least one via hole is provided for an optical via 4 and is formed at a distance from the contact pad 19. At least one further via hole is provided for an electrical through-substrate via 14 serving as electrical interconnection and is formed reaching the contact pad 19. Dielectric sidewall layers 6, 16 are optionally formed at the sidewalls of the via holes to insulate the semiconductor material from metallizations that are subsequently applied. The dielectric sidewall layers 6, 16 can be formed together in the same method step.
(14) The metal via layer 5 is deposited in the shape of a hollow cylinder in the via hole provided for the optical via 4, and the further metal via layer 15 is deposited in the via hole provided for the electrical through-substrate via 14 and may also form a hollow cylinder. The metal via layer 5 and the further metal via layer 15 can be applied together in the same method step. Hence the arrangement of the metal via layer 5 and the dielectric sidewall layer 6 in the optical via 4 can be similar to the arrangement of the further metal via layer 15 and the further dielectric sidewall layer 16 in the electrical through-substrate via 14. In particular, the metal via layer 5 at the sidewall of the optical via 4 and the portion of the further metal via layer 15 that is arranged at the sidewall of the electrical through-substrate via 14 can have the same thickness.
(15) The dielectric cover layer 22 may be applied in the same method step together with a portion of the dielectric layer 2 covering the further metal via layer 15 at the sidewall of the electrical through-substrate via 14. In this case the dielectric cover layer 22 and the portion of the dielectric layer 2 covering the further metal via layer 15 at the sidewall of the electrical through-substrate via 14 may have the same thickness.
(16) The further metal via layer 15 contacts the contact pad 19 at the bottom of the via hole. The metal via layer 5 is removed from the bottom of the via hole that is provided for the optical via 4, so that the metal via layer 5 is open at both ends and forms a metal tube allowing free passage of light. The removal of the bottom portion of the metal via layer 5 can be effected by anisotropically etching, especially by an anisotropic reactive ion etch step (RIE), with no or extremely low etch rate at the vertical sidewall and maximal etch rate on the horizontal bottom surface.
(17)
(18)
(19) In
(20)
(21) The arrangement of the substrate 1 with an optical device 10 and a board 21 shown in
(22)
(23)
(24) A further dielectric cover layer 28 may be arranged on the central portion of the metal via layer 5. The boundary between the central portion of the metal via layer 5 and the central portion of the dielectric sidewall layer 6 or the boundary between the central portion of the metal via layer 5 and the further dielectric cover layer 28 may additionally be used for light propagation by means of surface plasmon-polaritons as described above.
(25) The semiconductor pillar 27 is formed by etching the via hole for the optical via 4 in the shape of a hollow cylinder. The semiconductor pillar 27 may therefore rest on a portion of the further dielectric layer 3.
(26) The invention has the advantage that light signal transfer is enabled by through-substrate vias that are conventionally created for electrical connections between conductors on one side of a substrate and conductors on the opposite side. The necessary modifications of the through-substrate vias do not require a dedicated further etching step and do not go beyond conventional production techniques.