NON-LINEAR HIGH-FREQUENCY AMPLIFIER ARRANGEMENT

Abstract

A non-linear high-frequency amplifier arrangement suitable for generating power outputs 1 kW at frequencies of 1 MHz for plasma excitation is provided. The arrangement includes two LDMOS transistors each connected by their source connection to aground connection point, where the LDMOS transistors have the same design and are arranged in an assembly, a power transformer whose primary winding is connected to drain connections of the LDMOS transistors, a signal transformer whose secondary winding is connected by a first end to a gate connection of one LDMOS transistor and by a second end to a gate connection of the other LDMOS transistor, and a feedback path from the drain connection to the gate connection of each of the LDMOS transistors.

Claims

1. A high-frequency amplifier arrangement for generating an output power of 1 kW at frequencies of 1 MHz for plasma excitation, the high-frequency amplifier arrangement comprising: a. first and second Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors, wherein each is connected to a ground connection point by their respective source terminals, and wherein the LDMOS transistors are embodied alike and are arranged in a package; b. a power transformer, a primary winding of which is connected to drain terminals of the LDMOS transistors; c. a signal transformer, a secondary winding of which is connected at a first end to a gate terminal of the first LDMOS transistor and at a second end to a gate terminal of the second LDMOS transistor; and d. a first feedback path from the drain terminal of the first LDMOS transistor to the gate terminal of the first LDMOS transistor and a second feedback path from the drain terminal of the second LDMOS transistor to the gate terminal of the second LDMOS transistor.

2. The high-frequency amplifier arrangement of claim 1, wherein each of the first and second feedback paths comprises a respective series circuit including a respective resistor and a respective capacitor.

3. The high-frequency amplifier arrangement of claim 2, wherein each of the respective resistors has a resistance value in a range from 200 ohm to 600 ohm, and each of the respective capacitors has a capacitance in a range from 0.5 nF to 5.0 nF.

4. The high-frequency amplifier arrangement of claim 1, wherein the secondary winding of the signal transformer is connected at the first end to the gate terminal of the first LDMOS transistor by one or more first resistive elements and is connected at the second end to the gate terminal of the second LDMOS transistor by one or more second resistive elements, such that a lossy gate circuit is produced.

5. The high-frequency amplifier arrangement of claim 4, wherein each of the resistive elements is configured as a resistor having a resistance value in a range from 1 ohm to 100 ohm.

6. The high-frequency amplifier arrangement of claim 1, wherein the drain terminals of the LDMOS transistors are respectively connected to ground by at least one capacitor.

7. The high-frequency amplifier arrangement of claim 6, wherein the capacitors are connected to ground by one of a plurality of parallel vias and through-plating into a heat spreader of the LDMOS transistors.

8. The high-frequency amplifier arrangement of claim 1, further comprising a circuit board that lies flat on a metal cooling plate and is connected to the cooling plate.

9. The high-frequency amplifier arrangement of claim 8, wherein the circuit board is connected to the metal cooling plate by a plurality of ground connections, and the metal cooling plate is connected to ground.

10. The high-frequency amplifier arrangement of claim 8, wherein the package is arranged on the circuit board.

11. The high-frequency amplifier arrangement of claim 1, wherein a primary winding of the signal transformer is connected to a high-frequency input, and a secondary winding of the power transformer is connected to a high-frequency output.

12. A method of protecting a high-frequency amplifier arrangement, the method comprising: receiving a supply power by a primary winding of a signal transformer of the amplifier arrangement, wherein a secondary winding of the signal transformer is connected at a first end to a gate terminal of a first Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor of the amplifier arrangement and at a second end to a gate terminal of a second LDMOS transistor of the amplifier arrangement, wherein each of the first and second LDMOS transistors are connected to a ground connection point by a respective source terminal and to a primary winding of a power transformer of the amplifier arrangement by a respective drain terminal, and wherein the amplifier arrangement comprises a respective feedback path from the respective drain terminal to the respective gate terminal of each of the first and second LDMOS transistors; operating the high-frequency amplifier arrangement as a non-linear amplifier arrangement in a normal mode, wherein a set power is supposed to be output by the high-frequency amplifier arrangement in the normal mode; and in response to determining that less than 50% of the set power is to be output, operating the high-frequency amplifier arrangement in a linear mode.

13. The method of claim 12, further comprising outputting a high-frequency power by a secondary winding of the power transformer, wherein operating the high-frequency amplifier arrangement in the linear mode comprises operating the high-frequency amplifier arrangement in the linear mode over at least two cycles of the high-frequency power.

14. The method of claim 12, wherein operating the high-frequency amplifier arrangement in the linear mode comprises: operating the high-frequency amplifier arrangement in the linear mode for at least 100 ns.

15. The method of claim 12, wherein operating the high-frequency amplifier arrangement as the non-linear amplifier arrangement in the normal mode comprises: selecting voltage levels of driver signals for the gate terminals of the LDMOS transistors, such that the LDMOS transistors are operated at least temporarily in a saturation mode when switched on.

16. The method of claim 12, wherein operating the high-frequency amplifier arrangement in the linear mode comprises: selecting voltage levels of driver signals for the gate terminals of the LDMOS transistors such that the LDMOS transistors are operated in a non-saturation mode.

17. The method of claim 12, wherein each of the respective feedback paths comprises a respective series circuit including a respective resistor and a respective capacitor.

18. The method of claim 12, wherein the secondary winding of the signal transformer is connected at the first end to the gate terminal of the first LDMOS transistor by one or more first resistive elements and is connected at the second end to the gate terminal of the second LDMOS transistor by one or more second resistive elements, such that a lossy gate circuit is produced.

19. The method of claim 12, wherein the drain terminal of each of the LDMOS transistors is respectively connected to ground by at least one capacitor, and wherein the capacitors are connected to ground by one of a plurality of parallel vias and through-plating into a heat spreader of the LDMOS transistors.

20. The method of claim 12, wherein the LDMOS transistors are in a package on a circuit board that is on a metal cooling plate, and wherein the circuit board is connected to the metal cooling plate by a plurality of ground connections.

Description

DESCRIPTION OF DRAWINGS

[0021] Embodiments of the invention are shown in the schematic drawings and explained in greater detail in the following description.

[0022] In the drawings:

[0023] FIG. 1 shows a high-frequency amplifier arrangement according to the invention.

[0024] FIG. 2A shows voltage curves of gate voltages and drain voltages of LDMOS transistors when a set power is rapidly reduced.

[0025] FIG. 2B shows corresponding voltage curves when a set power is rapidly reduced, but the high-frequency amplifier arrangement is still being operated in linear mode.

[0026] FIG. 3A shows graphs obtained when no capacitors are used between drain and ground.

[0027] FIG. 3B shows graphs obtained when capacitors are used between drain and ground.

DETAILED DESCRIPTION

[0028] FIG. 1 shows a first embodiment of a high-frequency amplifier arrangement 1. The high-frequency amplifier arrangement 1 includes a circuit board 2 on which a package 3 is arranged. The package 3 includes two LDMOS transistors S1, S2, which are embodied alike and are each connected to a ground connection point 5 by their respective source terminals.

[0029] To stabilize the high-frequency amplifier arrangement 1, which can be operated in a non-linear manner, feedback paths 34, 35 are provided from the drain terminals of the LDMOS transistors S1, S2 to the gate terminals 15, 17. The feedback paths 34, 35 each include a series circuit having a resistor 36, 37 and a capacitor 38, 39.

[0030] The LDMOS transistors S1, S2 are each connected, by the drain terminals thereof, to an end of a primary winding 6 of a power transformer 7, which is part of an output network. The secondary winding 4 of the power transformer 7 is connected to ground 8 and also connected to a high-frequency output 9. A high-frequency power can be output through the high-frequency output 9, e.g., to a load.

[0031] The drain terminals of the LDMOS transistors S1, S2 are in each case connected to ground via a capacitor 32, 33. The connection is achieved by through-plating into a heat spreader of the LDMOS transistors S1, S2.

[0032] The high-frequency amplifier arrangement 1 further includes a signal transformer 10, which includes a primary winding 11 that is connected to a high-frequency input 12. A supply power can be provided to the high-frequency amplifier arrangement 1 through the high-frequency input 12. A set power is a power that is supposed to be output or generated by the high-frequency amplifier arrangement 1 in a normal mode. The secondary winding 13 of the signal transformer 10 is connected to the gate terminal 15 of the LDMOS transistor S1 by a resistive element 14, e.g., a resistor. The secondary winding 13 is also connected to the gate terminal 17 of the LDMOS transistor S2 by a resistive element 16, e.g., a resistor. The resistive elements 14, 16 and the secondary winding 13 are therefore connected in series. Just like the power transformer 7, the signal transformer 10 is also arranged on the circuit board 2.

[0033] The gate terminals 15, 17 are connected, by resistors 22, 23, to a capacitor 30, which is in turn connected to ground 27. A DC voltage source is connected to the terminal 31.

[0034] The circuit board 2 lies flat on a cooling plate 25, which can also be connected to ground 26. In particular, the circuit board 2 is connected to the cooling plate 25 by a plurality of ground connections 8, 27. The ground connection 5 is a ground connection point for transferring heat from LDMOS transistors S1, S2 to the cooling plate 25.

[0035] FIG. 2A shows a drain voltage curve 100 of the first LDMOS transistor S1 and the drain voltage curve 101 of the second LDMOS transistor S2. The gate voltage, by which the LDMOS transistors are driven, is indicated by reference numeral 102. Voltage peaks are indicated by a circle 103 and occur in the drain voltage when the set power is reduced abruptly, in particular when the high-frequency amplifier arrangement is switched off without changing to a linear amplifier mode after being switched off. Said voltage peaks should be avoided.

[0036] FIG. 2B shows the corresponding voltages 100, 101, 102 when, during sudden reduction of the set power, there is a transition from a non-linear amplifier mode into a linear amplifier mode. It can be seen in this case that the voltage peaks do not arise in the drain voltages 100, 101, as a result of which the LDMOS transistors are protected.

[0037] FIG. 3A shows, on the left-hand side, the differential mode impedance 110 and, on the right-hand side, the common mode impedance 111 of the matching network (as seen from the drains) when no capacitors are provided between drain and ground.

[0038] FIG. 3B shows, on the left-hand side, the differential mode impedance 112 and, on the right-hand side, the common mode impedance 113 of the matching network (as seen from the drains) when corresponding capacitors 32, 33 are used.

Other Embodiments

[0039] A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.