Layer structure for mounting semiconductor device and fabrication method thereof

Abstract

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Claims

1. A layer structure for mounting a semiconductor device, comprising: a single layer of first encapsulant having a first bottom surface and a first top surface opposite to the first bottom surface; a plurality of first conductive elements embedded in the single layer of first encapsulant and each having a first end portion exposed from the first bottom surface of the single layer of first encapsulant and a second end portion exposed from the first top surface of the single layer of first encapsulant; a circuit layer formed on the first end portions of the first conductive elements and having a first surface adjacent to the first conductive elements and a second surface opposite to the first surface; a plurality of second conductive elements formed on the second surface of the circuit layer so as to be electrically connected to the first conductive elements through the circuit layer; and a single layer of second encapsulant formed on the first bottom surface of the single layer of first encapsulant for encapsulating the circuit layer and the second conductive elements, wherein the single layer of second encapsulant has a second top surface adjacent to the single layer of first encapsulant and a second bottom surface opposite to the second top surface, and wherein the first top surface of the single layer of first encapsulant and the second bottom surface of the single layer of second encapsulant respectively form an outer surface and another outer surface of the layer structure.

2. The structure of claim 1, wherein each of the second conductive elements has a third end portion exposed from the second bottom surface of the single layer of second encapsulant.

3. The structure of claim 2, further comprising a chip mounted on the second bottom surface of the single layer of second encapsulant and electrically connected to the third end portions of the second conductive elements.

4. The structure of claim 2, further comprising a chip mounted on the first top surface of the single layer of first encapsulant and electrically connected to the second end portions of the first conductive elements.

5. The structure of claim 4, further comprising a circuit board mounted on the second bottom surface of the single layer of second encapsulant and electrically connected to the third end portions of the second conductive elements.

6. The structure of claim 1, wherein the circuit layer has a thickness less than 300 um.

7. The structure of claim 1, wherein the circuit layer is made of gold, copper, iron, steel or copper-nickel-palladium alloy.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1A to 1D are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the prior art;

(2) FIGS. 2A to 2G are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the present invention; and

(3) FIGS. 3 and 4 are schematic cross-sectional views showing other embodiments of the layer structure of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(4) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(5) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as first, second, top, bottom, on, a etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(6) FIGS. 2A to 2G are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the present invention.

(7) Referring to FIG. 2A, a conductive layer 20 having a first surface 20a and a second surface 20b opposite to the first surface 20a is provided. The conductive layer 20 can be a conductive film and have a thickness H less than 300 um. The conductive layer 20 can be made of, but not limited to, gold, copper, iron, steel, cold-pressed steel or copper-nickel-palladium alloy.

(8) Referring to FIG. 2B, a plurality of first conductive elements 21 are formed on the first surface 20a of the conductive layer 20. Each of the first conductive elements 21 has a first end portion 21a adjacent to the conductive layer 20 and a second end portion 21b opposite to the first end portion 21a.

(9) Referring to FIG. 2C, a first encapsulant 22 is formed on the first surface 20a of the conductive layer 20 for encapsulating the first conductive elements 21. The first encapsulant 22 has a first bottom surface 22a adjacent to the conductive layer 20 and a first top surface 22b opposite to the first bottom surface 22a.

(10) Referring to FIG. 2D, a plurality of second conductive elements 23 are formed on the second surface 20b of the conductive layer 20. Each of the second conductive elements 23 has a third end portion 23a and a fourth end portion 23b opposite to the third end portion 23a and adjacent to the conductive layer 20. As such, the conductive layer 20, the first conductive elements 21, the first encapsulant 22 and the second conductive elements 23 constitute a base material 2a.

(11) Referring to FIG. 2E, the conductive layer 20 is patterned or partially removed by etching to form a circuit layer 20 that electrically connects the first conductive elements 21 and the second conductive elements 23.

(12) Referring to FIG. 2F, a second encapsulant 24 is formed on the first bottom surface 22a of the first encapsulant 22 for encapsulating the circuit layer 20 and the second conductive elements 23. The second encapsulant 24 has a second top surface 24b adjacent to the first encapsulant 22 and a second bottom surface 24a opposite to the second top surface 24b.

(13) Referring to FIG. 2G. The first encapsulant 22 is thinned from the first top surface 22b by such as grinding so as to expose the second end portions 21b of the first conductive elements 21. Further, the second encapsulant 24 can be thinned from the second bottom surface 24a so as to expose the third end portions 23a of the second conductive elements 23. As such, a layer structure 2b for mounting a semiconductor device is formed.

(14) The present invention further provides a layer structure 2b for mounting a semiconductor device. Referring to FIG. 2G, the layer structure 2b has: a first encapsulant 22 having a first bottom surface 22a and a first top surface 22b opposite to the first bottom surface 22a; a plurality of first conductive elements 21 embedded in the first encapsulant 22 and each having a first end portion 21a exposed from the first bottom surface 22a of the first encapsulant 22; a circuit layer 20 formed on the first end portions 21a of the first conductive elements 21 and having a first surface 20a adjacent to the first conductive elements 21 and a second surface 20b opposite to the first surface 20a; a plurality of second conductive elements 23 formed on the second surface 20b of the circuit layer 20 so as to be electrically connected to the first conductive elements 21 through the circuit layer 20; and a second encapsulant 24 formed on the first bottom surface 22a of the first encapsulant 22 for encapsulating the circuit layer 20 and the second conductive elements 23, wherein the second encapsulant 24 has a second top surface 24b adjacent to the first encapsulant 22 and a second bottom surface 24a opposite to the second top surface 24b.

(15) Further, each of the first conductive elements 21 can have a second end portion 21b exposed from the first top surface 22b of the first encapsulant 22.

(16) The circuit layer 20 can further be formed on a portion of the first bottom surface 22a of the first encapsulant 22. The circuit layer 20 can have a thickness less than 300 um. The circuit layer 20 can be made of gold, copper, iron, steel, cold-pressed steel or copper-nickel-palladium alloy.

(17) Further, each of the second conductive elements 23 can have a third end portion 23a exposed from the second bottom surface 24a of the second encapsulant 24.

(18) FIGS. 3 and 4 are schematic cross-sectional views showing other embodiments of the layer structure of the present invention.

(19) Referring to FIG. 3, a singulation process is performed to the layer structure 2b of FIG. 2G and then a chip 25 is mounted on the second bottom surface 24a of the second encapsulant 24 and electrically connected to the third end portions 23a of the second conductive elements 23 through a plurality of first solder balls 26, thereby forming a layer structure 2c for mounting a semiconductor device.

(20) In other words, the layer structure 2c of FIG. 3 can have a chip 25 mounted on the second bottom surface 24a of the second encapsulant 24 and electrically connected to the third end portions 23a of the second conductive elements 23 through a plurality of first solder balls 26.

(21) In another embodiment, referring to FIG. 4, a singulation process is performed to the layer structure 2b of FIG. 2G. Then, a chip 25 can be mounted on the first top surface 22b of the first encapsulant 22 and electrically connected to the second end portions 21b of the first conductive elements 21 through a plurality of first solder balls 26, and/or a circuit board 27 can be mounted on the second bottom surface 24a of the second encapsulant 24 and electrically connected to the third end portions 23a of the second conductive elements 23 through a plurality of second solder balls 28. As such, a layer structure 2d for mounting a semiconductor device is formed.

(22) In other words, the layer structure 2d of FIG. 4 can have a chip 25 and/or a circuit board 27. The chip 25 can be mounted on the first top surface 22b of the first encapsulant 22 and electrically connected to the second end portions 21b of the first conductive elements 21. The circuit board 27 can be mounted on the second bottom surface 24a of the second encapsulant 24 and electrically connected to the third end portions 23a of the second conductive elements 23.

(23) The present invention mainly involves forming a plurality of first and second conductive elements on first and second surfaces of a conductive layer, respectively, and forming a first encapsulant to encapsulate the first conductive elements and forming a second encapsulant to encapsulate the second conductive elements and a circuit layer formed from the conductive layer.

(24) Therefore, the present invention overcomes the conventional problem that the first and second copper layers are easily damaged during etching of the carrier. According to the present invention, the first and second conductive elements can be easily formed on the conductive layer so as to reduce the fabrication difficulty and increase the product yield.

(25) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.