Integrated circuit with sensor and method of manufacturing such an integrated circuit

Abstract

Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Claims

1. An integrated circuit comprising: a substrate carrying a plurality of circuit elements; a metallization stack interconnecting the circuit elements, the metallization stack including a patterned upper metallization layer having a first metal portion; a passivation stack covering the metallization stack, the passivation stack including a moisture-impenetrable layer and being configured and arranged to mitigate moisture penetration to the metallization stack and ensure operation of the circuit elements; and a sensor including a sensing material deposited on top of the passivation stack, the sensing material being coupled to the first metal portion by a via extending through the passivation stack, wherein the sensor including the sensing material is deposited above the moisture-impenetrable layer, and wherein the passivation stack and the via provide a contiguous moisture barrier over the first metal portion, the contiguous moisture barrier preventing moisture from contacting the first metal portion upon exposure of the sensor to moisture.

2. The integrated circuit of claim 1, wherein the sensing material is deposited over the via.

3. The integrated circuit of claim 1, wherein the passivation stack includes a Ta.sub.2O.sub.5 layer, the sensing material being formed on the Ta.sub.2O.sub.5 layer.

4. The integrated circuit of claim 3, wherein the sensing material is formed on top of the Ta.sub.2O.sub.5 layer.

5. A method of manufacturing an integrated circuit, comprising: providing a substrate carrying a plurality of circuit elements; forming a metallization stack interconnecting the circuit elements, the metallization stack including a patterned upper metallization layer having a first metal portion; forming a passivation stack covering the metallization stack, the passivation stack including a moisture-impenetrable layer and being configured and arranged to mitigate moisture penetration to the metallization stack and ensure operation of the circuit elements; forming a trench in the passivation stack to expose the first metal portion; forming a via in the trench; and forming a sensor including a sensing material by depositing the sensing material on top of the passivation stack, the sensing material being coupled to the first metal portion, wherein the sensor including the sensing material is deposited above the moisture-impenetrable layer, and wherein the passivation stack and the via are formed such that they provide a contiguous moisture barrier over the first metal portion, the contiguous moisture barrier preventing moisture from contacting the first metal portion upon exposure of the sensor to moisture.

6. The method according to claim 5, wherein the sensing material is deposited over the via to couple the sensing material to the first metal portion.

7. The method according to claim 5, wherein the passivation stack includes a Ta.sub.2O.sub.5 layer, the sensing material being formed on the Ta.sub.2O.sub.5 layer.

8. The method according to claim 7, wherein the sensing material is formed on top of the Ta.sub.2O.sub.5 layer.

Description

BRIEF DESCRIPTION OF THE EMBODIMENTS

(1) Embodiments of the invention are described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

(2) FIG. 1 schematically depicts a prior art IC with multiple sensors;

(3) FIG. 2 schematically depicts a method to manufacture an IC with a sensor in accordance with an embodiment of the present invention;

(4) FIG. 3 schematically an IC with a sensor in accordance with another embodiment of the present invention;

(5) FIG. 4 schematically depicts a method to manufacture an IC with a sensor in accordance with yet another embodiment of the present invention;

(6) FIG. 5 schematically depicts a method to manufacture an IC with a sensor in accordance with yet another embodiment of the present invention;

(7) FIG. 6 schematically depicts an IC with a sensor in accordance with yet another embodiment of the present invention; and

(8) FIG. 7 schematically depicts an IC with a sensor in accordance with yet another embodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

(9) It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

(10) FIG. 2 schematically depicts the various steps of a method of manufacturing an IC with an environmental sensor, i.e. a sensor exposed to the environment of the IC in accordance with an embodiment of the present invention, in which an improved protection against moisture penetrating the internals of the IC is achieved. As shown in step (a), an IC may be provided comprising a substrate 10 onto which a metallization stack is formed. Such a metallization stack typically comprises a stack of patterned metal layers 12 electrically insulated from each other by electrically insulating, i.e. dielectric layers 14. Metal portions in different metallization layers 12 may be conductively coupled to each other by means of vias 16 extending through dielectric layers 14 separating such metal portions from each other. The substrate 10 may be any suitable substrate material, e.g. single crystal Si, SiGe, silicon on insulator and so on, and may carry a plurality of circuit elements such as transistors, diodes and so on.

(11) Equally, the metallization stack may be formed in any suitable manner, and may contain any suitable number of metal layers 12 and dielectric layers 14. It should be understood that three metal layers are shown by way of non-limiting example only.

(12) Each metal layer 12 and each dielectric layer 14 is depicted as a single layer in FIG. 2 for the sake of clarity only. It should be appreciated that such layers may consist of a number of stacked sub-layers, for instance in a submicron CMOS process, stacks of Ti, TiN, AlCu, TiN may be used to define a single metal layer in the metallization stack.

(13) Each of the dielectric layers 14 may also comprise more than a single layer. For instance, such a dielectric layer may be a stack comprising FSG (fluorosilicate glass), SiO.sub.2 and HDP oxide (High Density Plasma) any other suitable dielectric material combination. Other suitable materials may also be used.

(14) Similarly, it will be apparent that the vias 16 may be formed from more than a single material. For instance, in the aforementioned CMOS 14 technology, a via 16 may be formed by a TiN liner and a W plug. Other semiconductor processes may use different materials, e.g. Cu for the metal layers 12 and vias 16.

(15) In FIG. 2, the upper metal layer of the metallization stack comprises an electrode portion 20 and a bond pad portion 22. In step (b), the metallization stack is covered by a passivation stack, which may comprise the deposition of a high density plasma oxide 24 followed by an oxide planarization step, e.g. a chemical mechanical polishing (CMP) step, after which a SiO.sub.2 layer 26 and a Si.sub.3N.sub.4 layer 28 may be deposited to any suitable thickness. Other layer materials may also be contemplated for the passivation stack. It is known per se to the skilled person how to form such a passivation stack such that this will not be elaborated upon for reasons of brevity only.

(16) The method proceeds as shown in step (c), in which a resist 30 is deposited onto the passivation stack and subsequently patterned to leave exposed the parts of the passivation stack over the electrode portion 20. Any suitable resist material may be used for this purpose, e.g. a negative resist or a positive resist material. The resultant structure is subsequently subjected to an etch recipe, e.g. a reactive ion etch (RIE), to selectively remove the respective layers of the passivation stack from over the electrode portion 20 such that this portion becomes exposed by trenches 32, after which the patterned resist 30 is stripped from the patterned passivation stack. The resultant structure is shown in step (d).

(17) The trenches 32 are subsequently filled, e.g. by deposition of a TiN layer followed by a tungsten fill of the remainder of the trenches 32 to yield vias 34 extending through the passivation stack, as shown in step (e). The trenches 32 may be filled with tungsten using e.g. a chemical vapor deposition (CVD) process. Other via materials are equally feasible, e.g. Cu vias, which may be advantageous when Cu is used as the metal in the metallization stack.

(18) Next, a resist 36 is applied over the resultant structure as shown in step (f) to open the bond pad portion 22 whilst protecting the remainder of the IC. The resist 36 may be the same material as used for the resist 30 although it is equally feasible to use a different resist material. An etch step may be applied, such as a reactive ion etch stopping on the bond pad metal, e.g. Al, to remove the passivation stack in the areas exposed by the patterned resist 36, after which the resist 36 may be stripped off the passivation stack in any suitable manner. The resultant structure including the opening 38 over the bond pad portion 22 is shown in step (g).

(19) The sensor of the IC may now be completed by the deposition, e.g. spinning and subsequent development, of a sensing material 40 over the through-passivation vias 34, thereby functionalizing the electrodes 20 in the metallization stack. This is shown in step (h). For instance, in case of a relative humidity sensor, the sensing material 40 may be a material that can absorb moisture, which causes a change in the dielectric constant of the sensing material such that the moisture content can be determined capacitively. A non-limiting example of a suitable embodiment of the sensing material 40 is polyimide.

(20) In an alternative embodiment, the formation of the trenches 32 and subsequent formation of the vias 34 as shown in steps (d) and (e) of FIG. 2 may be extended to include the formation of a circular or any other suitably shaped via, i.e. a guard ring 34 through the passivation stack that terminates on the bond pad and surrounds the opening 38 such that the metallization stack is shielded from environmental contact through the side walls of opening 38. The method may subsequently proceed as shown in FIG. 2. The resultant IC is shown in FIG. 3.

(21) FIG. 4 shows an alternative embodiment of the method of the present invention, which shares the steps (a)-(e) of the embodiment shown in FIG. 2. These steps are therefore not shown in FIG. 4 for the sake of brevity. After the formation of the through-passivation vias 34 and subsequent planarization, e.g. by means of CMP, the passivation stack is extended by the deposition of a layer 42 of Ta.sub.2O.sub.5 over the resultant structure, as shown in step (a) of FIG. 4. This oxide is known to be moisture-impenetrable such that it provides additional protection against moisture penetration, e.g. through cracks in the through-passivation vias 34. As Ta.sub.2O.sub.5 is a so-called high-k dielectric material, its presence under the sensing material 40 reduces sensitivity of the environmental sensor only by a small amount when applying a typical thickness Ta.sub.2O.sub.5 layer 42, e.g. a sensitivity reduction of 5-10% for a 25 nm Ta.sub.2O.sub.5 layer in the shown configuration.

(22) After formation of the Ta.sub.2O.sub.5 layer, the IC may be finalized analogous to the method shown in FIG. 2, i.e. by providing the patterned resist 36 to define the bond pad opening (step (b) of FIG. 4), opening the bond pad 22, e.g. by RIE (step (c) of FIG. 4) and applying the sensing material 40 over the through-passivation vias 34 (step (d) of FIG. 4), with the alteration that the formation of opening 38 now includes removing the additional Ta.sub.2O.sub.5 layer from over the bond pad 22. It is noted that although not explicitly shown in FIG. 4, this embodiment of the present invention may further include a guard ring 34 around the bond pad 22.

(23) In order to increase the sensitivity of the sensor, another exemplary embodiment of the present invention includes the provision of one or more electrodes on the passivation stack such that the passivation stack is situated between these electrodes and the metallization stack. This is shown in FIG. 5, where a substrate carrying a metallization stack and a passivation stack is shown in step (a). The metallization stack comprises an electrode portion 20 and a bond pad portion 20 in the upper metallization layer of the metallization stack. The passivation stack comprises a high density plasma oxide layer 24, a SiO.sub.2 layer 26 and a Si.sub.3N.sub.4 layer as a scratch protection layer by way of non-limiting example only. The use of additional layers (e.g. a Ta.sub.2O.sub.5 layer 42 as shown in FIG. 4) and/or different layer materials will be apparent to the skilled person. In the next step shown as step (b), a resist 30 is deposited and patterned such that the passivation stack regions over the electrode portion 20 and a bond pad portion 20 in the upper metallization layer are exposed. The resist 30 may be any suitable material as previously explained.

(24) The resultant structure is subjected to a passivation stack etch recipe, e.g. a ME, to open the passivation stack as shown in step (c). The etch is terminated on the electrode portion 20 and a bond pad portion 20 in the upper metallization layer such that these portions are exposed by the trenches 32 formed in the etch step. The trenches 32 are subsequently filled with a conductive material, which may be preceded by the formation of a liner on the side walls and bottom of the trenches 32. For instance, the trenches 32 may be lined with a TiN liner and subsequently filled with a tungsten plug although it is reiterated that the vias 34 may be formed using any suitable conductive material.

(25) Preferably, the same conductive material is used for the through-passivation vias 34 as for the vias 16 in the metallization stack as this means that the same processing steps used for the formation of the vias 16 may be reused for the vias 34, thus limiting the overall cost of the manufacturing process. After the formation of the through-passivation vias 34 as shown in step (d), which typically includes a CMP planarization step following deposition of the via filler, the method proceeds as shown in step (e) by the deposition of a metal layer 50, e.g. an Al layer, a Cu layer or metal alloy layer such as an AlCu layer over the resultant structure from which external electrodes and bond pads are to be formed by patterning of the metal layer 50. The metal layer 50 may be deposited by any suitable process.

(26) To facilitate patterning of the metal layer 50, a resist 52 is deposited on the metal layer 50 and subsequently developed to expose the parts of the metal layer 50 to be removed, as shown in step (f). Any suitable resist may be used for this purpose. The exposed metal is subsequently removed, e.g. by using an etch recipe such as a RIE and the patterned resist 52 is subsequently stripped from the remaining metal portions to render an IC comprising one or more electrodes 54 and a bond pad 56 on the passivation stack as shown in step (g). The sensor may be completed by the deposition of the sensing material 40 over the one or more electrodes 54 as shown in step (h). The sensing material 40 may be deposited and patterned as previously explained.

(27) In a preferred embodiment, the sensor comprises two interdigitated electrodes 54, e.g. meandering or finger electrodes in which the electrodes are electrically insulated from each other by the moisture-adsorbent sensing material 40, such as polyimide or another suitable electrically insulating material. This effectively provides a capacitor having large surface area capacitor plates in the form of the interdigitated electrodes 54, with the sensing material 40 acting as the dielectric of the capacitor. It should be apparent that aspects of the embodiments of FIG. 2-5 may be combined without departing from the teachings of the present invention. One particular advantageous combination of such aspects is shown in FIG. 6, in which the bond pad portion 22 in the upper metallization layer is used as the actual bond pad instead of a bond pad portion provided on top of the passivation stack. This can be achieved by patterning the metal layer 50 such that only electrodes 54 are formed, after which a resist 36 may be applied to the resultant structure in analogy with step (f) in FIG. 2, followed by a passivation stack opening to form the opening 38 over the bond pad portion 22, and the removal of the resist 36 followed by the deposition of the sensing material 40 as explained in more detail in the detailed description of FIG. 2. The embodiment shown in FIG. 6 is particularly attractive from a cost perspective as it requires limited modification of existing manufacturing processes, in particular CMOS manufacturing processes.

(28) The electrodes 54 may be protected by a Ta.sub.2O.sub.5 layer 42 as shown in FIG. 7. This protects the electrodes 54 from corrosion and further improves the moisture hermeticity of the IC. The presence of the Ta.sub.2O.sub.5 layer 42 further facilitates the integration of a pH sensor on the same wafer as the environmental sensor of the present invention. The Ta.sub.2O.sub.5 layer 42 may be deposited after the patterning of the meandering electrodes 54 and prior to the opening of the bond pad 22 as explained in the description of FIG. 6.

(29) The Ta.sub.2O.sub.5 layer 42 may be deposited in any suitable manner, e.g. PVD or CVD. Chemical vapor deposition (CVD) is preferable as this yields a Ta.sub.2O.sub.5 layer having superior conformality.

(30) Although the described embodiments have been limited to providing the IC of the present invention with a single environmental sensor, it will be appreciated that other sensors may be included in the IC design without departing from the scope of the present invention.

(31) The IC of the present invention may be integrated in any suitable electronic device, e.g. a mobile communication device such as a mobile phone, personal digital assistant and so on, or may be used as a tag for an article for monitoring purposes, in which case the IC may be extended with RF functionality, e.g. an RF transceiver communicatively coupled to the sensor(s) of the IC.

(32) It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word comprising does not exclude the presence of elements or steps other than those listed in a claim. The word a or an preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.