Vertical semiconductor device with improved ruggedness

Abstract

A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Claims

1. A vertical semiconductor device comprising: a substrate having a first doping type; a buffer layer over the substrate and having the first doping type; a drift layer over the buffer layer and having the first doping type; and a spreading layer over the drift layer and having the first doping type; wherein: the substrate, the buffer layer, and the drift layer comprise silicon carbide; and a thickness of the buffer layer is greater than twenty-five percent and less than or equal to thirty-five percent of a thickness of the drift layer.

2. The vertical semiconductor device of claim 1 wherein a doping concentration of the buffer layer is at least ten times a doping concentration of the drift layer.

3. The vertical semiconductor device of claim 1 wherein a doping concentration of the buffer layer is between ten and thirty times a doping concentration of the drift layer.

4. The vertical semiconductor device of claim 1 wherein a doping concentration of the spreading layer is between 1×10.sup.16 cm.sup.−3 to 5×10.sup.16 cm.sup.−3.

5. The vertical semiconductor device of claim 1 wherein the thickness of the buffer layer is greater than twenty-five percent and less than or equal to thirty percent of the thickness of the drift layer.

6. The vertical semiconductor device of claim 1 wherein a doping concentration of the buffer layer is between 5×10.sup.16 cm.sup.−3 and 5×10.sup.18 cm.sup.−3.

7. The vertical semiconductor device of claim 6 wherein the spreading layer has a doping concentration between two and one thousand times that of the doping concentration of the drift layer.

8. The vertical semiconductor device of claim 6 wherein the buffer layer and the drift layer are uniformly doped.

9. The vertical semiconductor device of claim 6 wherein a thickness of the spreading layer is less than the thickness of the drift layer.

10. The vertical semiconductor device of claim 1 wherein a doping concentration of the buffer layer is between fifteen and twenty-five times a doping concentration of the drift layer.

11. The vertical semiconductor device of claim 1 wherein a doping concentration of the drift layer is between 1×10.sup.13 cm.sup.−3 and 1×10.sup.17 cm.sup.−3 and the thickness of the drift layer is between one and four micrometers.

12. The vertical semiconductor device of claim 11 wherein a doping concentration of the buffer layer is between 1×10.sup.17 cm.sup.−3 and 5×10.sup.18 cm.sup.3.

13. A vertical semiconductor device comprising: a substrate having a first doping type; a first drift layer and a second drift layer over the substrate and having the first doping type, wherein the second drift layer is between the first drift layer and the substrate; and a spreading layer over the first drift layer and having the first doping type, wherein the substrate, the first drift layer, and the second drift layer comprise silicon carbide.

14. The vertical semiconductor device of claim 13 wherein a doping concentration for the second drift layer is higher than a doping concentration for the first drift layer.

15. The vertical semiconductor device of claim 13 wherein a doping concentration for the second drift layer is between 1.1 and 3 times a doping concentration for the first drift layer.

16. The vertical semiconductor device of claim 13 wherein: a doping concentration for the second drift layer is higher than a doping concentration for the first drift layer; and a thickness of the second drift layer is less than a thickness of the first drift layer.

17. The vertical semiconductor device of claim 13 wherein doping concentrations of the first drift layer and the second drift layer are between 1×10.sup.13 cm.sup.−3 and 1×10.sup.17 cm.sup.3, a thickness of the first drift layer is between 2 and 50 micrometers, and a thickness of the second drift layer is between 1 and 30 micrometers.

18. The vertical semiconductor device of claim 13 wherein there is no buffer layer between the substrate and either of the first drift layer or the second drift layer.

19. The vertical semiconductor device of claim 13 wherein the spreading layer comprises silicon carbide and has a higher doping concentration than the first drift layer.

20. A vertical semiconductor device comprising: a substrate having a first doping type; a buffer layer over the substrate and having the first doping type; a first drift layer and a second drift layer over the buffer layer and having the first doping type, wherein the second drift layer is between the first drift layer and the substrate; and a spreading layer over the first drift layer and having the first doping type, wherein the substrate, the buffer layer, and the first and second drift layers comprise silicon carbide.

21. The vertical semiconductor device of claim 20 wherein a doping concentration for the second drift layer is higher than a doping concentration for the first drift layer.

22. The vertical semiconductor device of claim 20 wherein a doping concentration for the second drift layer is between 1.1 and 3 times a doping concentration for the first drift layer.

23. The vertical semiconductor device of claim 20 wherein: a doping concentration for the second drift layer is higher than a doping concentration for the first drift layer; and a thickness of the second drift layer is less than a thickness of the first drift layer.

24. The vertical semiconductor device of claim 23 wherein a doping concentration of the buffer layer is at least ten times an average doping concentration of the first drift layer and the second drift layer.

25. The vertical semiconductor device of claim 23 wherein a doping concentration of the buffer layer is between ten and thirty times an average doping concentration of the first drift layer and the second drift layer.

26. The vertical semiconductor device of claim 25 wherein a thickness of the buffer layer is between ten and thirty percent of a combined thickness of the first drift layer and the second drift layer.

27. The vertical semiconductor device of claim 20 wherein: a doping concentration of the buffer layer is between ten and thirty times a doping concentration of the first drift layer; and a thickness of the buffer layer is between ten and thirty percent of a thickness of the first and second drift layers.

28. The vertical semiconductor device of claim 27 wherein the spreading layer has a doping concentration between two and one thousand times that of the doping concentration of the first and second drift layers.

29. The vertical semiconductor device of claim 27 wherein the buffer layer and the first and second drift layers are uniformly doped.

30. The vertical semiconductor device of claim 27 wherein a thickness of the spreading layer is less than a combined thickness of the first drift layer and the second drift layer.

31. The vertical semiconductor device of claim 20 wherein doping concentrations of the first drift layer and the second drift layer are between 1×10.sup.13 cm.sup.−3 and 1×10.sup.17 cm.sup.3, a thickness of the first drift layer is between 2 and 50 micrometers, and a thickness of the second drift layer is between 1 and 30 micrometers.

32. The vertical semiconductor device of claim 31 wherein a doping concentration of the buffer layer is between 1×10.sup.17 cm.sup.−3 and 5×10.sup.18 cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 illustrates a conventional vertical semiconductor device.

(3) FIG. 2 is a graph illustrating the operating characteristics of a conventional vertical semiconductor device.

(4) FIG. 3 illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(5) FIGS. 4A through 4C are graphs illustrating various operating characteristics of a vertical semiconductor device according to one embodiment of the present disclosure.

(6) FIG. 5 illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(7) FIG. 6 illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(8) FIG. 7 illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(9) FIG. 8 is a graph illustrating the operating characteristics of vertical semiconductor devices according to various embodiments of the present disclosure.

(10) FIG. 9 illustrates a PiN diode according to one embodiment of the present disclosure.

(11) FIG. 10 illustrates a Schottky barrier diode according to one embodiment of the present disclosure.

(12) FIG. 11 illustrates a metal-oxide semiconductor field-effect transistor (MOSFET) according to one embodiment of the present disclosure.

(13) FIG. 12 is a flow chart illustrating a method for manufacturing a vertical semiconductor device according to one embodiment of the present disclosure.

(14) FIG. 13A illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(15) FIG. 13B is a graph illustrating the electric field in the vertical semiconductor device for the embodiment of FIG. 13A.

(16) FIG. 13C is graph illustrating the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in a blocking state for the embodiment of FIG. 13A.

(17) FIG. 14A illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(18) FIG. 14B is a graph illustrating the electric field in the vertical semiconductor device for the embodiment of FIG. 14A.

(19) FIG. 14C is graph illustrating the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in a blocking state for the embodiment of FIG. 14A.

(20) FIG. 15A illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(21) FIG. 15B is a graph illustrating the electric field in the vertical semiconductor device for the embodiment of FIG. 15A.

(22) FIG. 15C is graph illustrating the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in a blocking state for the embodiment of FIG. 15A.

(23) FIG. 16A illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(24) FIG. 16B is a graph illustrating the electric field in the vertical semiconductor device for the embodiment of FIG. 16A.

(25) FIG. 16C is graph illustrating the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in a blocking state for the embodiment of FIG. 16A.

(26) FIG. 17A illustrates a vertical semiconductor device according to one embodiment of the present disclosure.

(27) FIG. 17B is a graph illustrating the relative graded doping centration levels throughout the various layers of the vertical semiconductor device for the embodiment of FIG. 17A.

(28) FIG. 17C is graph illustrating the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in a blocking state for the embodiment of FIG. 17A.

(29) FIG. 18 illustrates a vertical power device according to one embodiment of the present disclosure.

(30) FIG. 19 is a graph illustrating the relative graded doping centration levels throughout the various layers of the vertical semiconductor device for the embodiment of FIG. 18.

DETAILED DESCRIPTION

(31) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(32) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(33) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(34) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(35) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(36) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(37) FIG. 2 is a graph illustrating an exemplary relationship between current through the conventional vertical semiconductor device 10 and voltage across the conventional vertical semiconductor device 10. As shown, the current through the device maintains relatively consistent leakage current at 1 pico-Amps for blocking voltages up to 1600 Volts (this graph is applicable to devices rated for blocking voltages up to 1200 Volts and forward currents up to 50 Amps, similar curves will show the same general characteristics for devices having other ratings). Above 1600 Volts, the conventional vertical semiconductor device 10 begins to experience avalanche breakdown, and the current through the device thus increases sharply. Above 1 Amps, the conventional vertical semiconductor device 10 experiences a second breakdown in which the current through the device continues to increase, and the voltage across the device decreases sharply. The extent to which the conventional vertical semiconductor device 10 experiences this second breakdown (i.e., the voltage at which second breakdown occurs) is proportional to the ability of the device to withstand radiation. This is because when operating at high voltages, radiation particles such as terrestrial neutrons or heavy ions may collide with charge particles in the device, knocking these charge particles loose and causing a cascade effect that results in the device “jumping” from the bottom portion of the curve shown in FIG. 2 to the top portion in which second breakdown occurs. If this occurs, the conventional vertical semiconductor device 10 will catastrophically fail.

(38) In light of the above, there is a need for vertical semiconductors with improved radiation tolerance and thus increased ruggedness. Accordingly, FIG. 3 shows the basic structure of a vertical semiconductor device 16 according to one embodiment of the present disclosure. The vertical semiconductor device 16 includes a substrate 18, a buffer layer 20 over the substrate 18, and a drift layer 22 over the buffer layer 20. A graph shows the relative doping concentrations of the substrate 18, the buffer layer 20, and the drift layer 22. As shown, the substrate 18 is more heavily doped than the buffer layer 20, which is in turn more heavily doped than the drift layer 22. In particular, the substrate 18, the buffer layer 20, and the drift layer 22 are all doped in a relatively consistent manner and thus form a step doping profile as shown. Providing the buffer layer 20 with a doping concentration that is higher than the drift layer 22 but lower than the substrate 18 creates a buffer for charge particles that may be accelerated by collisions with radiated particles, allowing these accelerated charge particles to recombine instead of passing through the vertical semiconductor device 16.

(39) Notably, the thickness and doping concentrations of the substrate 18, the buffer layer 20, and the drift layer 22 are merely exemplary. In particular, these thicknesses and doping concentrations are shown for a device rated for 1200 Volts. Those skilled in the art will readily appreciate that higher blocking voltages may dictate greater thicknesses for the drift layer 22, and in some embodiments, the buffer layer 20, and/or decreased doping concentrations for the same. However, the relationship between the thicknesses and doping concentrations of these layers will remain relatively unchanged. In one embodiment, a thickness of the buffer layer 20 may be between 5% and 35% the thickness of the drift layer 22. In specific embodiments, a thickness of the buffer layer 20 may be between 5% and 10% the thickness of the drift layer 22, between 10% and 15% the thickness of the drift layer 22, between 15% and 20% the thickness of the drift layer 22, between 20% and 25% the thickness of the drift layer, between 25% and 30% the thickness of the drift layer 22, between 30% and 35% the thickness of the drift layer 22, between 15% and 15% the thickness of the drift layer 22, and between 25% and 35% the thickness of the drift layer 22. Further, the doping concentration of the buffer layer 20 may vary between 20% and 90% the doping concentration of the substrate 18 while remaining greater than the doping concentration of the drift layer 22 by at least 20%. In specific embodiments, the doping concentration of the buffer layer 20 may be between 20% and 30% the doping concentration of the substrate 18, between 30% and 40% the doping concentration of the substrate 18, between 40% and 50% the doping concentration of the substrate 18, between 50% and 60% the doping concentration of the substrate 18, between 60% and 70% the doping concentration of the substrate 18, between 70% and 80% the doping concentration of the substrate 18, and between 80% and 90% the doping concentration of the substrate 18.

(40) In one embodiment, the substrate 18, the buffer layer 20, and the drift layer 22 are silicon carbide (SiC). Accordingly, the buffer layer 20 may be an epitaxial layer that is grown on the substrate 18 before the drift layer 22. The drift layer 22 may then be grown over the buffer layer 20. The buffer layer 20 may be grown in an environment with dopants to provide the desired doping concentrations, or grown and subsequently implanted (e.g., via ion implantation) to the desired doping concentration. In other embodiments, the buffer layer 20 may be an implanted region in the surface of the substrate 18. Since the substrate 18 is more highly doped than the desired doping level for the buffer layer 20, the substrate 18 may be doped with an opposite doping type (e.g., if the substrate 18 is an n-type substrate, it may be doped with a p-dopant) to decrease the net doping concentration thereof. Notably, the principles of the present disclosure apply equally to n-type or p-type substrates, buffer layers, and drift layers. That is, the principles of the present disclosure may be equally applied to n-type and p-type devices.

(41) FIG. 4A is a graph illustrating the effect of the buffer layer 20 on the second breakdown of the vertical semiconductor device 16. In particular, FIG. 4A shows a relationship between current through the vertical semiconductor device 16 and voltage across the vertical semiconductor device 16 for several different thicknesses of the buffer layer 20 at a doping concentration of 10.sup.17 cm.sup.−3. As shown, as the thickness of the buffer layer 20 increases, the voltage at which second breakdown occurs also increases. As defined herein, the second breakdown voltage is the lowest voltage at which the second breakdown occurs, and reflects the left-most point of the upper portion of the graph shown in FIG. 4A. Increasing the second breakdown voltage may significantly increase the radiation tolerance and thus ruggedness of the vertical semiconductor device 16. In one embodiment, the buffer layer 20 increases the second breakdown voltage such that it is greater than the avalanche voltage.

(42) FIG. 4B is a graph illustrating the effect of the buffer layer 20 on both the avalanche breakdown voltage and the second breakdown voltage. In particular, FIG. 4B shows a relationship between the avalanche breakdown voltage and the second breakdown voltage to a doping concentration of the buffer layer 20 when the buffer layer is 1 μm thick. As shown, as the doping concentration of the buffer layer 20 increases, the second breakdown voltage similarly increases, up to a certain point, where it begins to decline rapidly. Notably, the doping concentration of the buffer layer 20 has a minimal effect on the avalanche breakdown voltage, and thus using the buffer layer 20 does not decrease the performance of the vertical semiconductor device 16.

(43) FIG. 4C is a graph illustrating the effect of the buffer layer 20 on the failure rate of the vertical semiconductor device 16. In particular, FIG. 4C shows a relationship between failure rate (as a function of device hours) and voltage across the device. A first line shows the failure rate for devices not including the buffer layer 20, while a second line shows the failure rate for devices including the buffer layer 20. As illustrated, the failure rate of devices including the buffer layer 20 is significantly lower for a given device voltage.

(44) FIG. 5 shows the vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 shown in FIG. 5 is substantially similar to that shown in FIG. 3, except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 20 provides a linearly graded doping concentration that decreases in proportion to a distance from the drift layer 22 such that the overall doping profile of the device includes a step between the drift layer 22 and the buffer layer 20 and another step between the buffer layer 20 and the substrate 18. In this embodiment, the buffer layer 20 may be thicker to allow for the linear transition in the doping profile thereof. Such a doping profile may be created by first growing the buffer layer 20 and then performing ion implantation on it, or by growing the buffer layer 20 in an environment wherein the concentration of dopants are controlled throughout the growth process. Notably, this doping profile is merely exemplary, and any linearly graded doping concentration may be substituted for the one shown in FIG. 5 without departing from the principles of the present disclosure.

(45) FIG. 6 shows the vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 shown in FIG. 6 is substantially similar to that shown in FIG. 3 except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 20 provides a substantially smooth transition between the doping concentration of the drift layer 22 and the doping concentration of the substrate 18. In this embodiment, the buffer layer 20 may be substantially thicker to allow for the transition in the doping profile thereof. Such a doping profile may be created by first growing the buffer layer 20 and then performing ion implantation on it, or by growing the buffer layer 20 in an environment wherein the concentration of dopants are controlled throughout the growth process. Notably, this doping profile is merely exemplary, and any graded doping concentration, linear or otherwise, may be substituted for the one shown in FIG. 6 without departing from the principles of the present disclosure.

(46) FIG. 7 shows the vertical semiconductor device 16 according to an additional embodiment of the present disclosure. The vertical semiconductor device 16 shown in FIG. 7 is substantially similar to that shown in FIG. 3 except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 20 is provided as a doping “spike” and is not directly over the substrate 18. In this embodiment, the buffer layer 20 may be reduced in thickness. Such a doping profile may be formed either via separate growth on top of a small portion of the drift layer 22 or by growing a small portion of the drift layer 22, performing ion implantation to create the buffer layer 20, then growing the rest of the drift layer 22. Notably, this doping profile is merely exemplary, and any “spike” doping profile may be substituted for the one shown in FIG. 7 without departing from the principles of the present disclosure.

(47) FIG. 8 shows the effect of the buffer layer 20 for the embodiments shown in FIGS. 3, 5, 6 and 7 on the second breakdown of the vertical semiconductor device 16. As shown, the buffer layer 20 significantly increases the second breakdown voltage for each embodiment when compared to a conventional vertical semiconductor device not including the buffer layer 20. As discussed above, this results in a significantly increased radiation tolerance and thus improved ruggedness of the vertical semiconductor device 16.

(48) As discussed above, a number of implants, additional semiconductor layers, and/or metal layers may determine the device type and thus functionality of the vertical semiconductor device 16. In one embodiment, the vertical semiconductor device 16 is a PiN diode as shown in FIG. 9. Accordingly, the vertical semiconductor device 16 includes a p-layer 24 over the drift layer 22, an anode 26 over the p-layer 24, and a cathode 28 on the substrate 18 opposite the buffer layer 20. In another embodiment, the vertical semiconductor device 16 is a Schottky diode as shown in FIG. 10. Accordingly, the vertical semiconductor device 16 includes an anode 30 over the drift layer 22 and a cathode 32 on the substrate 18 opposite the buffer layer 20. One or more Schottky barrier regions 34 having an opposite doping type to the drift layer may be provided under the anode 30 to create a Schottky barrier diode (SBD). In yet another embodiment, the vertical semiconductor device 16 is a MOSFET as shown in FIG. 11. Accordingly, the vertical semiconductor device 16 includes a pair of junction implant regions 36, which are laterally separated from one another and include a source region 36A and a well region 36B, a gate oxide layer 38 running between the junction implant regions 36, a gate contact 40 over the gate oxide layer 38, a pair of source contacts 42 over a portion of the junction implant regions 36, and a drain contact 44 on the substrate 18 opposite the buffer layer 20. Those skilled in the art will appreciate that additional implanted regions, semiconductor layers, and/or metal layers may be provided to provide any number of different types of semiconductor devices, all of which are contemplated herein.

(49) FIG. 12 is a flow diagram illustrating a method for manufacturing a vertical semiconductor device according to one embodiment of the present disclosure. First, a substrate is provided (step 100). The substrate may be silicon carbide (SiC) as discussed above, and has a first doping type and a first doping concentration. A buffer layer is then provided over the substrate (step 102). The buffer layer has the first doping type and a second doping concentration that is less than the first doping concentration. The buffer layer may be epitaxially grown in an environment including dopants designed to create a desired doping profile, or may be grown and subsequently implanted (e.g., via ion implantation) to produce the desired doping profile. A drift layer is then provided over the buffer layer (step 104). The drift layer has the first doping type and a third doping concentration that is less than the second doping concentration. The drift layer may be epitaxially grown over the buffer layer. Finally, one or more additional implanted regions, semiconductor layers, and/or metal layers may be provided in order to provide a semiconductor device of a desired type (step 106). For example, a PiN diode, Schottky diode, MOSFET, or any other type of semiconductor device may be created by providing different implanted regions, semiconductor layers, and/or metal layers.

(50) The following disclosure provides further concepts that achieve radiation hardening for SiC power diodes and MOSFETs. These devices can potentially suffer catastrophic failure from high energy particles (i.e. neutrons, protons, or heavy ions) or energy bombardment (i.e. gamma rays, x-rays) while subjected to high blocking fields. The concepts also support better bipolar switching for most power devices that are switching quickly in a bipolar charge state. The concepts disclosed herein allow diode and MOSFET parts to be operated at higher voltages without the need for de-rating the voltage as is currently done. Devices fabricated from SiC or other semiconductor materials are benefit from these approaches and include, but are not limited to, vertical power diodes, MOSFETs, trench MOSFETs, IGBTs, and the like. Additional embodiments are provided below wherein each of the following embodiments may be implemented as any these device types.

(51) Typically, for better resistance to radiation-induced failure at high operating voltages (high field), it is known that the resistance of the drift layer can be increased by increasing the thickness or decreasing the doping of the drift layer. However, this means that the device will have a higher resistance and thus more power loss in normal use. Similarly, a device can be operated at lower voltages to avoid failure due to radiation, but this voltage limit may render the part unable to be used for the intended application.

(52) It is known that SiC and Si devices can fail due to terrestrial neutron or heavy ion bombardment at high semiconductor fields, but each behave differently. For Si devices, an altering of the drift layer design has been shown to improve radiation tolerance for devices under heavy ion bombardment. Silicon device ruggedness can be correlated to device breakdown, specifically an event termed “second breakdown” which occurs after a device at a high blocking field goes into a bipolar conduction mode. Higher second breakdown voltage onset equates directly to increased device ruggedness under radiation environments.

(53) Research has indicated that a Si device drift design change to keep device resistance constant can increase the second breakdown voltage, but this redesign lowers the avalanche voltage and makes devices more susceptible to other ‘typical’ modes of failure at high drift fields. Further, device ruggedness relates to the drift punch through voltage (V(PT)), and a drift design which increases the punch through voltage (V(PT)) value improves the high-voltage blocking ruggedness, and reduces switching transients that are harmful for circuits (i.e. diode reverse recovery transients are reduced), and thus increasing this value is also a key factor related to drift ruggedness in general.

(54) In addition, defects in the SiC substrate are known to be able to move basal-plane dislocations into the drift layer if the electric field is able to reach into the substrate while bipolar current is flowing. The following concepts reduce the occurrence of this by not allowing depletion to reach down to the substrate surface.

(55) Notably, Si and SiC semiconductors have key differences, which make design solutions much different. For example, for a given blocking voltage device, the doping levels and thickness of the drift layers 22 will differ by more than an order of magnitude between these materials, and thus unique solutions are needed for SiC-based devices. The bipolar effects involved in this type of breakdown event will be affected by different properties of hole lifetime and mobility in SiC compared to Si. For example, a 1200V vertical power device in SiC has a drift layer on the order of 10 um thick, doped to 1×10.sup.16 cm−3; whereas a Si device would be doped to ˜1×10.sup.14 cm−3 and be ˜100 um thick. Thus, the drift design limits for SiC devices is totally different than that of Si devices, and cannot be used it as a reference.

(56) As will become apparent, the following concepts achieve more than an order of magnitude decrease in the radiation failure rate at a given device voltage, while keeping the device resistance effectively unchanged and keeping the avalanche voltage level effectively unchanged. Further, improvements in switching performance are provided due to the disclosed non-punch-through design (NPT).

(57) Typically, SiC-based power devices are designed for the lowest possible resistance, which entails use of a punch-through drift design, wherein the drift layer 22 is fully depleted in blocking, and the electric field takes a trapezoidal form. Thus, the doping level in the drift layer 22 is relatively low, and the thickness is small, thereby providing a low resistance and good blocking voltage. However, the electric field punches through the drift layer 22 at a very low voltage and the bipolar breakdown (i.e. second breakdown) voltage is also low. As such, the power devices can be susceptible to high-field, high-current, and fast switching related failure mechanisms.

(58) As illustrated in FIG. 13A, a relatively thin but higher doped spreading layer 46 is provided in certain instances over the drift layer 22 to help the current spread before reaching the lower-doped drift layer 22. As such, a typical SiC or other wide bandgap vertical semiconductor device 16 may have a thin, higher doped top region as the spreading layer 46; a thicker, lower doped drift layer 22, and a relatively this substrate 18, which is shown thin in FIG. 13A to save space. FIG. 13B is a graph of the electric field within the vertical semiconductor versus distance from the top of the vertical semiconductor device 16. At avalanche, the electric field is highest at the top surface of the spreading layer 46 and drops in intensity through the spreading layer 46 and drift layer 22, although at different rates. Notably, the electric field remains at a significant level at the interface of the drift layer 22 and the substrate 18 (i.e. the top surface of the substrate 18). As such, the electric field effectively punches-through (PT) the entire drift layer 22, as illustrated in FIG. 13B. FIG. 13C illustrates that this type of punch through can occur well before avalanche breakdown, and the second breakdown can occur at a lower voltage than avalanche as well, for a structure such as this. In particular, FIG. 13C is a graph showing the electric field at the bottom of the drift layer 22, and the drain-source current (Ids), as the drain-source voltage (Vds) increased in a blocking mode for a FET or diode configuration of the vertical semiconductor device 16. The punch-through voltage V(PT) is observed, as well as the voltages for second breakdown and avalanche breakdown.

(59) To avoid or mitigate the punch through of the electric field in to the substrate, a buffer layer 20 may be employed with a spreading layer 46 as illustrated in FIG. 14A. The doping concentration of the buffer layer 20 may be between that of the drift layer 20 and substrate 18. Inclusion of the buffer layer 20 tends to keep the electric field away from the top surface of the substrate 18 and increases the second breakdown voltage. For the illustrated embodiment and as illustrated in FIG. 14B, the electric field at the avalanche voltage punches through the drift layer 22, but is stopped at the buffer layer 20, and as such does not punch through to the substrate 18. Inclusion of the buffer layer 20 increases the second breakdown voltage, which increases ruggedness in high-field bipolar conditions as well as keeps the electric field away from the substrate 18. Keeping the electric field away from the substrate minimizes the effects of basal plane dislocation motion from the substrate 18 into the drift layer 22. FIG. 14C illustrates the electric field at the bottom of the drift layer 22 and the drain-source current (Ids), as the drain-source voltage (Vds) increases in the blocking mode for a FET of diode configuration of the vertical semiconductor device 16. With the buffer layer 20, the avalanche (Vaval) and punch-through voltage V(PT) is unchanged; however, the voltage for second breakdown is significantly increased.

(60) For certain embodiments, the spreading layer 46 will generally range from 1E×10.sup.16 to 1×10.sup.17 cm.sup.−3 in doping level and 1 um-4 um in thickness depending on the desired current and voltage ratings. The doping for the drift layer 22 depends on the voltage rating of the device and can vary from 1×10.sup.13 to 1×10.sup.17 cm.sup.−3 doping range and from 2 um-300 um in thickness for devices rated from 300V to 300 kV. The buffer layer 20 is generally lower in doping than the substrate 18, which is often doped at 1×10.sup.18 or higher, and is high enough not to significantly deplete in blocking. As such, the buffer layer 20 may range from 1×10.sup.17 up to 5×10.sup.18 cm.sup.−3 and be 0.5 um to 5 um thick depending on the doping, in order to function as necessary. The thickness of the substrate 18 may range from 50 to 500 micrometers. The concept associated with the embodiment of FIG. 14A adds very little resistance to the structure, but aids in ruggedness performance.

(61) Alternative doping concentration ranges for the embodiment of FIG. 14A includes: from 1×10.sup.16 to 5×10.sup.16 cm.sup.−3 for the spreading layer 46; from 1×10.sup.13 to 1×10.sup.17 cm.sup.−3 for the drift layer 22; from 5×10.sup.16 to 5×10.sup.18 cm.sup.−3 for the buffer layer 46; and from 5×10.sup.17 to 1×10.sup.20 cm.sup.−3 for the substrate 18.

(62) In the embodiment of FIG. 15A, multiple drift layers are provided in the vertical semiconductor device 16 and referenced as an upper, first drift layer 22A and a lower, second drift layer 22B. No buffer layer 20 is included. The first drift layer 22A resides between the spreading layer 46 and the second drift layer 22B. The second drift layer 22B resides between the first drift layer 22A and the substrate 18.

(63) The lower, second drift layer 22B may have a doping level slightly higher than the upper, first drift layer 22A in an effort to thicken the drift from the prior embodiments. Further, first drift layer 22A can be thinner than the drift layer 22 of embodiment in FIG. 14A while having a slightly higher doping level to keep overall drift resistance low. Relative to the previous embodiment, these changes increase both the punch through voltage (V(PT)) and second breakdown voltage.

(64) In certain embodiments, the second drift layer 22B may have a doping level that is one to three times that of the first drift layer 22A while being any thickness near or less than that of the first drift layer 22A. This embodiment provides increased ruggedness by not allowing as high of an electric field to penetrate into the substrate 18. In select embodiments, the first and second drift layers 22A, 22B of the vertical semiconductor device 16 can be designed to prevent any electric field from punching through the second drift layer 22B into the substrate 18, as shown in FIG. 15B. FIG. 15B illustrates the electric fields in the vertical semiconductor device 16 at the avalanche voltage. Notably, the electric field is stopped in the second drift layer 22B just shy of the substrate 18.

(65) FIG. 15C illustrates the electric field at the bottom of the second drift layer 22B and the drain source current (Ids), as the drain-source voltage (Vds) increases in the blocking mode for a FET or diode configuration of the vertical semiconductor device 16. With the addition of the lower, second drift layer 22B, the avalanche voltage (Vaval) can be kept constant, while both the punch-through voltage V(PT) and the second breakdown voltage is increased beyond the avalanche voltage (Vaval).

(66) The use of multiple drift layers, such as the first and second drift layers 22A, 22B can aid in overall device ruggedness under high field, high current, and fast switching conditions. Snappiness in switching is reduced and electric fields are kept out of the substrate 18 so that the basal plane dislocations will not move into the first or second drift layers 22A, 22B. More than two drift layers may be used to achieve similar results.

(67) Exemplary doping concentration ranges for the embodiment of FIG. 15A includes: from 1×10.sup.16 to 5×10.sup.16 cm.sup.−3 for the spreading layer 46; from 1×10.sup.13 to 4×10.sup.16 cm.sup.−3 for the first drift layer 22A; from 2×10.sup.13 to 8×10.sup.16 cm.sup.−3 for the second drift layer 22B; and from 5×10.sup.17 to 1×10.sup.20 cm.sup.−3 for the substrate 18.

(68) An alternative set of ranges includes: from 1×10.sup.16 to 5×10.sup.16 cm.sup.−3 for the spreading layer 46; from 1×10.sup.15 to 2×10.sup.16 cm.sup.−3 for the first drift layer 22A; from 2×10.sup.15 to 3×10.sup.16 cm.sup.−3 for the second drift layer 22B; and from 1×10.sup.18 to 1×10.sup.20 cm.sup.−3 for the substrate 18.

(69) Exemplary thickness ranges include: 1-4 micrometers for the spreading layer 46; 2-50 micrometers for the first drift layer 22A; 1-30 micrometers for the second drift layer 22B; and 50-500 micrometers for the substrate 18.

(70) The embodiment illustrated in FIG. 16A builds on that of FIG. 15A by adding a buffer layer 20 between the second drift layer 22B and the substrate 18. As with the prior embodiment, the electric field at the avalanche voltage does not punch through second drift layer 22B, and as such is stopped shy of the buffer layer 20, as shown in FIG. 16B. The additional benefits of this embodiment become more readily apparent in FIG. 16C. FIG. 16C illustrates the electric field at the bottom of the drift layer 22B and the Ids current as the drain-source voltage (Vds) increases in the blocking mode when the vertical semiconductor device 16 is configured as a FET or diode. With the added buffer layer 20, the avalanche voltage (Vaval) and the punch-through voltage (V(PT)) are kept relatively constant, while the second breakdown voltage is further increased to provide additional field lowering in high field, high current discharge conditions.

(71) Exemplary doping concentration ranges for the embodiment of FIG. 16A includes: from 1×10.sup.16 to 5×10.sup.16 cm.sup.−3 for the spreading layer 46; from 1×10.sup.13 to 5×10.sup.16 cm.sup.−3 for the first drift layer 22A; from 2×10.sup.13 to 1×10.sup.17 cm.sup.−3 for the second drift layer 22B; from 5×10.sup.16 to 5×10.sup.18 cm.sup.−3 for the buffer layer 46; and from 1×10.sup.18 to 1×10.sup.20 cm.sup.−3 for the substrate 18.

(72) An alternative set of ranges includes: from 1×10.sup.16 to 5×10.sup.16 cm.sup.−3 for the spreading layer 46; from 1×10.sup.15 to 2×10.sup.16 cm.sup.−3 for the first drift layer 22A; from 2×10.sup.15 to 3×10.sup.16 cm.sup.−3 for the second drift layer 22B; from 1×10.sup.17 to 1×10.sup.18 cm.sup.−3 for the buffer layer 46; and from 1×10.sup.18 to 1×10.sup.20 cm.sup.−3 for the substrate 18.

(73) Exemplary thickness ranges include: 1-5 micrometers for the spreading layer 46; 2-50 micrometers for the first drift layer 22A; 1-30 micrometers for the second drift layer 22B; 1-20 micrometers for the buffer layer 46; and 50-500 micrometers for the substrate 18.

(74) The first and second drift layers 22A and 22B may have the same or different doping concentrations as well as the same or different doping profiles. For example, both the first and second drift layers 22A and 22B may have graded or fixed doping concentrations that are the same or different. Further, either one of the first and second drift layers 22A and 22B may have a graded doping profile while the other one is fixed. In certain embodiments, the spreading layer has a higher doping concentration than at least one, if not both, of the first and second drift layers.

(75) The embodiment of FIG. 17A provides a vertical semiconductor device 16 with a drift layer 22 with graded doping. In the illustrated embodiment, there is only one drift layer 22 and no buffer layer 20. The doping concentration increases in the drift layer 22 from the bottom (i.e. substrate interface) to the top (i.e. spreading layer 46 interface) of the drift layer 22. As such, the doping concentration is slightly higher at the bottom of the drift layer 22 and lower near the top of the drift layer 22. As illustrated in FIG. 17B, the doping concentration is relatively level throughout the spreading layer 46, drops to a first level at the top of the drift layer 22, increases continuously throughout the drift layer 22 to a level at or below the spreading layer 46, and jumps up to a much higher and relatively fixed level in the substrate 18. The doping concentrations in FIG. 17B are shown on a log scale.

(76) With the right doping concentration, profile, and thickness, an increase in both the punch through voltage (V(PT)) and the second breakdown voltage is provided, as illustrated in FIG. 17C. With the graded drift layer 22, the avalanche voltage (Vaval) can be kept constant, while the second breakdown voltage and the punch-through voltage V(PT) is increased beyond the avalanche voltage (Vaval) limit. This provides additional field lowering in high field, high current discharge conditions.

(77) Ruggedness under high field, high current, and fast switching conditions is increased by not allowing any or as high of a field to penetrate into the substrate 18. Bipolar device snappiness in switching is also reduced. As in the other embodiments, keeping the electric fields out of the substrate 18 prevents basal plane dislocations from moving into the drift layer 22.

(78) Exemplary doping concentration ranges for the embodiment of FIGS. 17A and 17B includes: from 1×10.sup.−16 to 5×10.sup.−16 cm.sup.−3 for the spreading layer 46; from between 1×10.sup.−13 and 5×10.sup.−18 cm.sup.−3 to between_1E15×10.sup.−X and_5E17_×10.sup.−X cm.sup.−3 for the drift layer 22; and from 1×10.sup.−18 to 1×10.sup.−20 cm.sup.−3 for the substrate 18.

(79) An alternative set of ranges includes: from 1×10.sup.−16 to 5×10.sup.−16 cm.sup.−3 for the spreading layer 46; from between 5×10.sup.−15 and 5×10.sup.−17 cm.sup.−3 to between 1×10.sup.−16 and 1×10.sup.−17 cm.sup.−3 for the drift layer 22; and from 1×10.sup.−18 to 5×10.sup.−19 cm.sup.−3 for the substrate 18.

(80) Exemplary thickness ranges include: 1-5 micrometers for the spreading layer 46; 3-200 micrometers for the drift layer 22; and 50-500 micrometers for the substrate 18.

(81) Turning now to FIG. 18, a buffer layer 20 and graded drift layer 22 are provided between the spreading layer 46 and the substrate 18. In this embodiment, the spreading layer 46 and the buffer layer 20 are uniformly doped and the drift layer 22 is graded as described above. In other embodiments, the doping for the spreading layer 46 and/or the buffer layer 20 is graded. The graph off FIG. 19 provides an exemplary doping profile on a log scale. As illustrated in FIG. 17B, the doping concentration decreases continuously from a first level at the top of the spreading layer 46 to a second level at the bottom of the spreading layer 46; increases continuously from the second level at the top of the drift layer 22 to a third level, which is lower than the first level, at the bottom of the drift layer 22; increases continuously from the second level throughout the buffer layer 20 to a fourth level. The doping throughout the substrate 18 is shown to be uniform at the fourth level. In the illustrated embodiment, the doping levels throughout the illustrated layers are continuous in that there are no abrupt changes in doping concentrations within a given layer or at the junction of layers.

(82) Exemplary doping concentration ranges for a fully graded embodiment includes: from between 5×10.sup.−16 and 1×10.sup.−14 cm.sup.−3 to between 3×10.sup.−16 and 5×10.sup.−15 cm.sup.−3 for the spreading layer 46; from between 1×10.sup.−13 and 1×10.sup.−17 cm.sup.−3 to between 5×10.sup.−15 and 5×10.sup.−16 cm.sup.−3 for the drift layer 22; from between 5×10.sup.−16 and 1×10.sup.−20 cm.sup.−3 to 1×10.sup.−17 and 1×10.sup.−20 cm.sup.−3 for the buffer layer 20; and from 1×10.sup.−18 to 1×10.sup.−20 cm.sup.−3 for the substrate 18.

(83) Exemplary thickness ranges include: 1-5 micrometers for the spreading layer 46; 3-200 micrometers for the drift layer 22; 1-20 micrometers for the buffer layer 20; and 50-500 micrometers for the substrate 18.

(84) The characteristics, thicknesses, doping concentrations, relationships of the thicknesses and/or doping concentrations and the like for the substrate 18, buffer layer 20, and drift layer 22 for the embodiments of FIGS. 3 through 12 may, but need not, be applied to any of the embodiments of FIGS. 13 through 19, and vice versa.

(85) Any of the above vertical semiconductor embodiments can be implemented as any of the previously identified vertical semiconductor components by adding the contacts (30, 32, 40, 42, 44) and appropriate doping regions/implants (34, 36A, 36B) as identified in FIGS. 10 and 11, wherein the doping regions will extend into one or more of the spreading layer 46, drift layer 22, first drift layer 22A, and/or second drift layer 22B. Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.