Semiconductor device having semiconductor chip with large and small irregularities on upper and lower side surface portions thereof

Abstract

A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside.

Claims

1. A semiconductor device, comprising: a semiconductor chip having a bottom surface; a die pad supporting the semiconductor chip; an adhesive adhering the semiconductor chip and the die pad; a plurality of signal leads extending toward a side of the die pad; bonding wires connecting the semiconductor chip and the plurality of signal leads; and an encapsulating body encapsulating the semiconductor chip, the bonding wires and a part of each signal lead with a mold resin, wherein a side surface of the semiconductor chip comprises a first irregular side surface and a second irregular side surface located above the first irregular side surface, wherein the first irregular side surface and the second irregular side surface are both generally perpendicular to the bottom surface of the semiconductor chip and lie generally in the same plane, wherein the second irregular side surface comprises second irregularities that are larger than first irregularities on the first irregular side surface, and wherein the encapsulating body is in direct contact with the semiconductor chip and directly contacts the first irregular side surface and the second irregular side surface.

2. A semiconductor device according to claim 1, wherein the second irregular side surface corresponds to two thirds or more of a thickness of the semiconductor chip.

3. A semiconductor device, comprising: a semiconductor chip having top and bottom surfaces bounded by a side surface; a die pad on which the bottom surface of the semiconductor chip is disposed; an adhesive interposed between the bottom surface of the semiconductor chip and the die pad to adhesively bond the semiconductor chip and the die pad; signal leads extending toward the die pad; bonding wires connecting respective signal leads to the semiconductor chip; and an encapsulating resin encapsulating the semiconductor chip, the bonding wires and a part of each signal lead, wherein the side surface of the semiconductor chip comprises a roughened lower surface portion extending from the bottom surface toward the top surface of the semiconductor chip and on which first roughened surface irregularities are formed, and a roughened upper surface portion extending from the lower surface portion to the top surface of the semiconductor chip and on which second roughened surface irregularities are formed, wherein the roughened lower and upper surface portions of the side surface lie generally in the same plane, wherein the second roughened surface irregularities are larger than the first roughened surface irregularities, and wherein the encapsulating resin is in direct contact with the semiconductor chip and directly contacts the first and second roughened surface irregularities.

4. A semiconductor device according to claim 3; wherein the roughened upper surface portion of the side surface extends for two thirds or more of the distance between the top and bottom surfaces of the semiconductor chip.

5. A semiconductor device according to claim 4; wherein the roughened lower and upper surface portions of the side surface are generally perpendicular to the bottom surface of the semiconductor chip.

6. A semiconductor device according to claim 3; wherein the second roughened surface irregularities are configured to improve the adhesive strength between the roughened upper surface portion and the encapsulating resin as compared to the adhesive strength between the roughened lower surface portion and the encapsulating resin.

7. A semiconductor device according to claim 3; wherein the first roughened surface irregularities are configured to allow the adhesive to creep upwardly along the roughened lower surface portion of the side surface during bonding of the semiconductor chip and the die pad to improve adhesive bonding therebetween.

8. A semiconductor device according to claim 7; wherein the second roughened surface irregularities are configured to improve the adhesive strength between the roughened upper surface portion and the encapsulating resin as compared to the adhesive strength between the roughened lower surface portion and the encapsulating resin.

9. A semiconductor device according to claim 3; wherein the plane is generally perpendicular to the bottom surface of the semiconductor chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A and 1B are cross-sectional views illustrating a semiconductor device according to a first embodiment of the present invention.

(2) FIG. 2 is a plan view of the semiconductor device according to the present invention.

(3) FIGS. 3A to 3C are step flow diagrams illustrating a method of manufacturing the semiconductor device according to the present invention.

(4) FIGS. 4A and 4B are cross-sectional views of a related-art semiconductor device.

(5) FIGS. 5A and 5B illustrate a method of manufacturing the semiconductor device according to the present invention.

(6) FIGS. 6A and 6B illustrate a method of manufacturing the semiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(7) A semiconductor device and a method of manufacturing the same of the present invention are described with reference to the drawings.

(8) FIGS. 1A and 1B are partial cross-sectional views of the semiconductor device according to the present invention. As illustrated in FIG. 1A, a semiconductor chip 2 having top and bottom surfaces bounded by a side surface is mounted on a die pad 3 having a roughened surface 15 on a top surface thereof via an adhesive 18 such as a silver paste. The top surface of the semiconductor chip 2 is covered by a protective film 17, which is formed of a polyimide film and the like. The die pad 3 and the semiconductor chip 2 are encapsulated by an encapsulating resin 8. FIG. 1B illustrates an enlarged view of the side surface of the semiconductor chip 2. As described below with reference to FIGS. 3 and 5-6, the side surface of the semiconductor chip 2 is roughened to form a first irregular side surface 24 formed of small irregularities (first roughened surface irregularities) on aside surface lower portion of the semiconductor chip 2 (the first irregularities are not shown) and a second irregular side surface 25 on which irregularities (second roughened surface irregularities), which are larger than the irregularities on the side surface lower portion. As illustrated in FIGS. 1A and 1B, the side surface lower and upper portions are generally perpendicular to the bottom surface of the semiconductor chip 2 and lie generally in the same plane (vertical plane in FIGS. 1A and 1B). With this configuration, the adhesive strength between the side surface upper portion of the semiconductor chip in which semiconductor elements are formed and the encapsulating resin 8 is improved, and hence the penetration of moisture is suppressed, and a semiconductor device having good moisture resistance can be obtained. It is noted that, the terms large and small used herein regarding the irregularities refer to the length from the bottom of the depressed portion to the top of the projecting portion of the formed irregularities being large or small.

(9) Further, by providing the first irregular side surface 24 at the side surface lower portion of the semiconductor chip 2, the adhesive 18 creeps up more satisfactorily during die bonding, so that the adhesive properties with the die pad 3 are improved even for a small semiconductor chip.

(10) FIG. 2 is a plan view illustrating a configuration of the semiconductor device according to the present invention. A resin-encapsulated semiconductor device 1 includes the semiconductor chip 2, the die pad 3 for fixing the semiconductor chip 2, and leads 4 extending on both sides of the die pad 3. The semiconductor chip 2 is constructed by, for example, a semiconductor substrate, a wiring layer provided on the semiconductor substrate, and the like. The semiconductor chip 2 is adhesively fixed to the die pad 3. The die pad 3 and the leads 4, which are conductive, are formed of, for example, a metal such as a FeNi alloy or a Cu alloy. A plurality of leads 4 are arranged around the die pad 3. A total of four leads 4 are arranged, i.e., two on one side of the die pad 3, and two on another side opposite thereto. One of the leads 4 is a suspension lead 5. Abase portion 5a of the suspension lead 5 is fixed to the die pad 3. The other three leads 4 are leads 6 separated from the die pad 3. An inner portion 6a of the leads 6 is electrically connected to the semiconductor chip 2 via conductive bonding wires 7. A gold wire or a copper wire is used for the bonding wires 7. The thus configured semiconductor chip 2, die pad 3, and inner portion 6a of the leads 6 are encapsulated by the encapsulating resin 8 formed of a resin, thereby protecting the semiconductor chip 2 from external shocks and the like, electrically insulating the semiconductor chip 2, and enabling the semiconductor chip 2 to be electrically connected to the outside via the plurality of leads 4. As the encapsulating resin 8, for example, a biphenyl-based insulating resin having added therein a phenolic curing agent, silicon rubber, filler, and the like may be used.

(11) Next, a method of manufacturing the semiconductor device of the present invention is described with reference to FIGS. 3A to 3C.

(12) First, steps S1 to S6 illustrated in FIGS. 3A to 3C are described. A dicing step S1 is a step of dividing a semiconductor wafer into semiconductor chips. A die bonding step S2 is a step of adhering a semiconductor chip to a die pad area of a lead frame using a silver paste and the like. Next, a die bonding curing step S3 is a step of curing a bonding portion by heating the adhered die pad and semiconductor chip. Next, a wire bonding step S4 is a step of connecting a bonding wire to an electrode portion of the semiconductor surface and a lead inner portion based on a bonding method that combines ultrasonic oscillation with thermocompression bonding. Further, in an assembly and testing step S5, testing is carried out on the bonding state of the semiconductor chip to the die pad and the bonding state of the bonding wire to the semiconductor chip. Then, the processing proceeds to a resin encapsulating step S6.

(13) In the resin encapsulating step S6, first, a mold including cavities, which are spaces surrounding the die pad and the semiconductor chip, a runner for causing the encapsulating resin to be injected to flow to the vicinity of each cavity, and a gate for connecting the runner and the cavities, is prepared correspondingly to each die pad. After the lead frame is sandwiched by the mold, and the encapsulating resin is injected and filled into each mold, the encapsulated lead frame is removed from the mold. At this point, thin resin burrs are formed between the leads and the like. Those burrs are formed by resin that has leaked out from slight gaps during the filling of the resin into the cavities of the mold. Depending on the mold, the resin burrs are formed at different positions and in different shapes for each mold.

(14) The dicing step S1 is now described in more detail using three methods as examples.

(15) First, FIG. 3A illustrates a manufacturing method that uses a laser dicing step. As illustrated in FIGS. 5A and 5B, a pulsed laser 9 is irradiated via a condensing lens 13 onto a scribe line 12 provided between a semiconductor chip 2 formed on a semiconductor substrate on which a dicing tape 14 has been attached and an adjacent semiconductor chip 2. The pulsed laser 9 is irradiated in multiple steps in a depth direction to form a modified layer 10 on the laser-irradiated area. The pulsed laser is irradiated in a concentrated manner at a high power on the upper of the thickness direction of the semiconductor chip 2 so that the modified layer 10 to be formed in the depth direction is continuously formed in a plane. This operation, which corresponds to the laser dicing step 1 of FIG. 3A, is a step of forming the second irregular side surface 25 of FIG. 1B. The laser dicing step 2 is a step of forming the first irregular side surface 24 in the lower of the thickness direction of the semiconductor chip. In this step, modified layers 11 to be formed in the depth direction by a low power laser are separately formed from each other. The size of the individual modified layers 11 is smaller than the size of the modified layer 10 formed in the laser dicing step 1. After carrying out the laser dicing steps 1 and 2, cleaving is carried out to obtain the semiconductor chip 2 having the first irregular side surface 24 and the second irregular side surface 25.

(16) If the thickness of the second irregular side surface 25 is sufficiently thick with respect to the thickness of the semiconductor chip 2, there is no need to carry out the laser dicing step 2, and hence the cleaving can be carried out after the laser dicing step 1. In this manufacturing method, irregularities having the same size as the above-mentioned example are formed on the second irregular side surface 25. However, the first irregular side surface 24 has very small irregularities because the first irregular side surface 24 is a cleaved surface.

(17) An example has been described above in which the pulsed laser is irradiated from the top surface, which is a surface on which the elements of the semiconductor chip are formed. However, the pulsed laser may be irradiated from a back surface of the semiconductor chip so as to avoid a TEG formed on the scribe line.

(18) The second irregular side surface 25 may also be realized using an ablation laser method instead of a pulsed laser method. In this case, an ablation laser is used in the laser dicing step 1, which enables larger irregularities to be formed than in the pulsed laser method. In the laser dicing step 2, a low power pulsed laser is used, and then cleaving is carried out to obtain the semiconductor chip.

(19) Next, FIG. 3B illustrates a manufacturing method using a blade dicing step. As illustrated in FIGS. 6A and 6B, in this manufacturing method, a dicing blade 16 is applied along scribe lines 12 provided between the semiconductor chip 2 formed on a semiconductor substrate on which the dicing tape 14 has been attached and an adjacent semiconductor chip 2 to cleave the semiconductor wafer into individual semiconductor chips. Here, using two types of dicing blade having different grain sizes, in a blade dicing step 1, the second irregular side surface 25 is formed by half-dicing from the semiconductor chip surface with a blade having a roughness of #1000 mesh or less. Next, in a blade dicing step 2, the first irregular side surface 24 is formed by cleaving using a blade having a #2000 mesh or more to obtain the semiconductor chip 2 having the first irregular side surface 24 and the second irregular side surface 25. In this manufacturing method, a semiconductor device having higher moisture resistance can be obtained by adding a modifying step S7 such as isotropic plasma silicon etching to remove a damaged layer on the cleaved surface.

(20) FIG. 3C illustrates a manufacturing method using a plasma dicing step. In a plasma dicing step 1, the second irregular side surface 25 is formed by silicon etching based on the Bosch process, in which isotropic etching and deposition of a protective film are repeated. In the Bosch process, continuous irregularities called scallops are formed on the semiconductor chip side surface. Then, the remaining silicon etching is carried out in a plasma dicing step 2 to cut the semiconductor wafer into individual semiconductor chips. Here, instead of the Bosch process, a method in which deep drilling is carried out by anisotropic etching is used. By carrying out such plasma dicing steps 1 and 2, the semiconductor chip 2 having the first irregular side surface 24 and the second irregular side surface 25 is obtained.