Dual-Thickness Active Area Architecture for SOI FETS

Abstract

Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the R.sub.ON*C.sub.OFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Two methods of forming shallow-trench isolation (STI) structures in both active layers are described. A first method forms STIs in the thin active layer first, then in the thick active layer. A second method forms STIs in the thin active layer first and partial STIs in the thick active layer, then completes the partial STIs in the thick active layer.

Claims

1. A substructure of a silicon-on insulator integrated circuit having dual-thickness active areas, including: (a) a substrate; (b) a buried oxide layer formed on the substrate; (c) a thin active layer formed on the buried oxide layer; and (d) a thick active layer formed on the buried oxide layer adjacent to the thin active layer.

2. The substructure of claim 1, wherein the thin active layer has a thickness at or below about 550 .

3. The substructure of claim 1, wherein the thick active layer has a thickness at or above about 1000 .

4. The substructure of claim 1, wherein the thick active layer is formed by epitaxial growth of one or more semiconductor materials on a selected region of the thin active layer.

5. The substructure of claim 4, wherein the thin active layer underlying the thick active layer is doped to lower a resistance of the thick active layer.

6. The substructure of claim 1, wherein the thin active layer is formed by removal of material from a selected region of the thick active layer.

7. The substructure of claim 1, further including a heat dissipation layer formed between the buried oxide layer and the thin and thick active layers.

8. The substructure of claim 1, further including a silicon carbide layer formed between the buried oxide layer and the thin and thick active layers.

9. The substructure of claim 1, wherein the substrate is one of P-type silicon, intrinsic silicon, high-resistivity silicon, porous silicon, or sapphire.

10. The substructure of claim 1, further including at least one field-effect transistor (FET), the at least one FET including: (a) a semiconductor well formed within the thin active layer; (b) a gate structure formed on the semiconductor well; (c) a source region formed within the semiconductor well adjacent a first side of the gate structure; and (d) a drain region formed within the semiconductor well adjacent a second side of the gate structure.

11. The substructure of claim 1, further including at least one field-effect transistor (FET), the at least one FET including: (a) a semiconductor well formed within the thick active layer; (b) a gate structure formed on the semiconductor well; (c) a source region formed within the semiconductor well adjacent a first side of the gate structure; and (d) a drain region formed within the semiconductor well adjacent a second side of the gate structure.

12. The substructure of claim 11, wherein the FET further includes a body contact region formed within the semiconductor well and extending to the buried oxide layer.

13. The substructure of claim 11, wherein the FET further includes a body region within the semiconductor well underneath the gate structure, and wherein a lower portion of the body region is doped to have a lower resistance R.sub.B.

14. (canceled)

15. The substructure of claim 11, wherein the FET further includes a body region within the semiconductor well underneath the gate structure, and wherein the FET is configured to fully deplete the body region in an OFF state.

16. (canceled)

17. The substructure of claim 11, wherein the FET further includes a body region within the semiconductor well underneath the gate structure, and wherein the FET is configured to partially deplete the body region in an OFF state.

18. The substructure of claim 11, wherein the semiconductor well includes at least two layers, at least one of the two layers comprising a silicon germanium alloy.

19. The substructure of claim 11, wherein the semiconductor well includes: (a) a first layer of silicon; (b) a second layer of a silicon germanium alloy; and (c) a third layer of tensile-strained silicon.

20. (canceled)

21. The substructure of claim 1, further including at least one field-effect transistor (FET), the at least one FET including: (a) a semiconductor well formed within the thick active layer and partially within the thin active layer; (b) a gate structure formed on the semiconductor well over the thick active layer; (c) a source region formed within the semiconductor well over the thick active layer adjacent a first side of the gate structure; (d) a drain region formed within the semiconductor well over the thick active layer adjacent a second side of the gate structure; and (e) a body contact region formed within the semiconductor well over the thin active layer.

22. The substructure of claim 21, wherein the semiconductor well includes at least two layers, at least one of the two layers comprising a silicon germanium alloy.

23. The substructure of claim 21, wherein the semiconductor well includes: (a) a first layer of silicon; (b) a second layer of a silicon germanium alloy; and (c) a third layer of tensile-strained silicon.

24.-35. (canceled)

Description

DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1A is a stylized cross-sectional diagram of a first example substructure of an SOI IC having dual-thickness active areas.

[0011] FIG. 1B is a stylized cross-sectional diagram of an example gate structure.

[0012] FIG. 2 is a stylized cross-sectional diagram of a second example substructure of an SOI IC having dual-thickness active areas.

[0013] FIG. 3A is a stylized cross-sectional diagram depicting a first stage in an additive method for fabricating dual-thickness active areas.

[0014] FIG. 3B is a stylized cross-sectional diagram depicting a second stage in an additive method for fabricating dual-thickness active areas.

[0015] FIG. 4A is a stylized cross-sectional diagram depicting a first stage in a subtractive method for fabricating dual-thickness active areas.

[0016] FIG. 4B is a stylized cross-sectional diagram depicting a second stage in a subtractive method for fabricating dual-thickness active areas.

[0017] FIG. 5 is stylized cross-sectional diagram depicting a multi-layer thick active layer AL.sub.THICK suitable for use in embodiments of the present invention.

[0018] FIG. 6A is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in a fully depleted OFF state.

[0019] FIG. 6B is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in an ON state.

[0020] FIG. 6C is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in a partially depleted OFF state.

[0021] FIGS. 7A-7H are stylized cross-sectional diagrams of a first set of manufacturing stages for an example substructure of an SOI IC that is to have dual-thickness active areas.

[0022] FIGS. 8A-8H are stylized cross-sectional diagrams of a second set of manufacturing stages for an example substructure of an SOI IC that is to have dual-thickness active areas.

[0023] FIG. 9 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0024] FIG. 10 is a process flow chart showing a first method for fabricating a substructure of an SOI IC having dual-thickness active areas.

[0025] FIG. 11 is a process flow chart showing a second method for fabricating a substructure of an SOI IC having dual-thickness active areas.

[0026] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.

DETAILED DESCRIPTION

[0027] The present invention encompasses structures and methods for better optimizing the performance of all the circuitryRF analog, non-RF analog, and digitalof an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer (e.g., about 550 ) while RF circuitry may be fabricated on a relatively thick active layer (e.g., about 2000 ). Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the R.sub.ON*C.sub.OFF figure of merit for the FET devices, and for optimizations not feasible (or in some cases, not possible) for RF circuitry fabricated on a relatively thin active layer. Embodiments of the present invention are particularly suitable for RF switches and amplifiers, including low-noise amplifiers (LNAs) and power amplifiers (Pas).

[0028] FIG. 1A is a stylized cross-sectional diagram of a first example substructure 100 of an SOI IC having dual-thickness active areas, fabricated using front-end-of-line processes. The illustrated substructure 100 includes a substrate 102, a trap-rich layer 104 formed on and/or in the substrate 102, and a BOX layer 106 formed on the trap-rich layer 104. The substrate 102 may be, for example, P-type Si, intrinsic Si, high-resistivity Si, porous Si, sapphire, or any other material compatible with SOI IC manufacture. In some embodiments, the trap-rich layer 104 may be omitted. In some embodiments, an optional heat dissipation layer 107 (e.g., silicon carbide, sic) may be formed over the BOX layer 106 (or over the trap-rich layer 104 if the BOX layer 106 is not present).

[0029] Dual-thickness active areas 108 of a semiconductor (e.g., Si or SiGe) are formed on the BOX layer 106 and comprise a relatively thin active layer AL.sub.THIN (e.g., at or below about 550 ) formed adjacent to a relatively thick active layer AL.sub.THICK (e.g., at or above about 1000 ). Two methods of fabricating the dual-thickness active areas 108 are set forth below.

[0030] In the example illustrated in FIG. 1A, a first N-type FET 110 is formed in and on the thin active layer AL.sub.THIN between surrounding isolation structures 112, such as shallow-trench isolation (STI) structures, and a second N-type FET 114 is formed in and on the thick active layer AL.sub.THICK between surrounding isolation structures 112. Each N-type FET 110, 114 includes a body contact BC to a P+ doped region, a source contact S to an N+ region, a drain contact D to an N+ region, and a gate contact G to a gate structure 116. In the illustrated example, the N+ source and drain regions are shown as extending only partway to the BOX layer 106, but in some embodiments, the N+ source and drain regions may extend all of the way to the BOX layer 106. While NFETs are shown, P-type FETs may be formed as well by reversing all P and N materials, in known fashion.

[0031] FIG. 1B is a stylized cross-sectional diagram of an example gate structure 116. In the illustrated example, a gate material 120, such as polysilicon (p-Si), is formed on an insulator 122, such as silicon dioxide (.sub.SiO2). One or more insulating spacers 122a, 122b (e.g., .sub.SiO2 or silicon nitride (SiN)) are formed on the sides of the gate material 120. It should be appreciated that other gate structures, including replacement metal gates (RMGs), may be used in embodiments of the present invention. The fabrication of gate structures 116 is well-known in the art.

[0032] Not shown in FIG. 1A is a superstructure that would be formed on the active areas 108 in a back-end-of-line (BEOL) process. The superstructure generally comprises inter-layer dielectric (ILD) with formed layers of conductive material (e.g., metallization layers), and vertical conductors (vias) of various sizes. Portions of the metallization layers may be connected to bonding pads by corresponding vias. The completed IC may then be packaged using any of a number of known technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0033] FIG. 2 is a stylized cross-sectional diagram of a second example substructure 200 of an SOI IC having dual-thickness active areas. Part of a single FET 202 is formed in and on a thick active layer AL.sub.THICK while the remainder of the FET 202 is formed in the adjacent thin active layer AL.sub.THIN. More specifically, in the illustrated example, a source contact S to an N+ region, a drain contact D to an N+ region, and a gate contact G to a gate structure 116 of the FET 202 are formed in and on the thick active layer AL.sub.THICK. In the illustrated example, the N+ source and drain regions are shown as extending only partway to the BOX layer 106, but in some embodiments, the N+ source and drain regions may extend all of the way to the BOX layer 106.

[0034] Of note, a body contact BC to a P+ doped region is formed in the adjacent thin active layer AL.sub.THIN. Accordingly, the layout of FETs on a substrate 102 supporting dual-thickness active areas 108 may cross the boundary between the thin active layer AL.sub.THIN and the thick active layer AL.sub.THICK.

[0035] FIG. 3A is a stylized cross-sectional diagram depicting a first stage in an additive method for fabricating dual-thickness active areas. A starting point is a partial IC substructure comprising a substrate 102 (e.g., P-type Si), a trap-rich layer 104 formed on and/or in the substrate 102, and a BOX layer 106 formed on the trap-rich layer 104. In some embodiments, the trap-rich layer 104 may be omitted. A thin active layer AL.sub.THIN is then formed on the BOX layer 106 by a suitable technology (e.g., epitaxial growth of Si) to a desired thickness (e.g., about 550 ). Note that the depicted partial IC substructure and thin active layer AL.sub.THIN are not to scale; for example, the substrate 102 alone may be about 775 m thick.

[0036] FIG. 3B is a stylized cross-sectional diagram depicting a second stage in an additive method for fabricating dual-thickness active areas. After masking part of the thin active layer AL.sub.THIN that is to remain unchanged, a thick active layer AL.sub.THICK is formed by depositing semiconductor material on the unmasked thin active layer AL.sub.THIN. Deposition may be by a suitable technology (e.g., epitaxial growth of Si) to a desired thickness (e.g., about 2000 including the thickness of the thin active layer AL.sub.THIN). A thickness of about 1000 or more for the thick active layer AL.sub.THICK increases electron mobility and application for RF switch circuits and LNA and PA devices and circuits. A thick active layer AL.sub.THICK may also have enhanced channel strain compared to a thin active layer AL.sub.THIN.

[0037] With any residual masking material removed, the partial IC substructure and dual-thickness active areas are ready for FET fabrication, such as is shown in FIGS. 1A and 2. Note that while only a single thin active layer AL.sub.THIN and a single thick active layer AL.sub.THICK are shown, a single IC die of a wafer may include more than one thin active layer AL.sub.THIN and/or more than one thick active layer AL.sub.THICK.

[0038] FIG. 4A is a stylized cross-sectional diagram depicting a first stage in a subtractive method for fabricating dual-thickness active areas. A starting point is a partial IC substructure comprising a substrate 102 (e.g., P-type Si), a trap-rich layer 104 formed on and/or in the substrate 102, and a BOX layer 106 formed on the trap-rich layer 104. In some embodiments, the trap-rich layer 104 may be omitted. A thick active layer AL.sub.THICK is then formed on the BOX layer 106 by a suitable technology (e.g., epitaxial deposition of Si) to a desired thickness (e.g., about 2000 ). Again, the depicted partial IC substructure and thick active layer AL.sub.THICK are not to scale.

[0039] FIG. 4B is a stylized cross-sectional diagram depicting a second stage in a subtractive method for fabricating dual-thickness active areas. After masking part of the thick active layer AL.sub.THICK that is to remain unchanged, a thin active layer AL.sub.THIN is formed by thinning the unmasked thick active layer AL.sub.THICK to a desired thickness (e.g., about 550 ), such as by ion beam dry etching or chemical wet etching processes. With any residual masking material removed, the partial IC substructure and dual-thickness active areas are ready for FET fabrication, such as is shown in FIGS. 1A and 2. Note again that while only a single thin active layer AL.sub.THIN and a single thick active layer AL.sub.THICK are shown, a single IC die may include more than one thin active layer AL.sub.THIN and/or more than one thick active layer AL.sub.THICK.

[0040] Note that the doping levels of the thin active layer AL.sub.THIN and the thick active layer AL.sub.THICK may have different concentrations. Further, the top surface region of the thick active layer AL.sub.THICK may be graded or retrograded to have little or no doping, so as behave very much like intrinsic Si or to essentially be intrinsic Si and thus exhibit higher carrier mobility. The added thickness of the thick active layer AL.sub.THICK allows for greater opportunities to engineer the material in the P-well body region beneath the gate structure 116.

[0041] In general, circuitry that would not particularly benefit from being fabricated in and on the thick active layer AL.sub.THICKsuch as digital and non-RF analog circuitrymay be fabricated in and on the thin active layer AL.sub.THIN. Accordingly, little or no change would be needed to existing fabrication steps to form active and/or passive devices in and on the thin active layer AL.sub.THIN. Development time and cost should be reduced by using existing fabrication processes for circuitry that is suitable for the thin active layer AL.sub.THIN.

[0042] RF analog circuitry, such as RF switches (e.g., antenna switches, signal switches), LNAs, and Pas, may be fabricated in the thick active layer AL.sub.THICK. Advantages of the thick active layer AL.sub.THICK with respect to fabrication of such circuitry are several. For example, the thick active layer AL.sub.THICK may be formed in several layers of different materials that result in improved performance. A thin active layer AL.sub.THIN generally is too thin to allow a multi-layer active layer. A multi-layer thick active layer AL.sub.THICK may be fabricated using either the additive process or the subtractive process described above.

[0043] FIG. 5 is stylized cross-sectional diagram depicting a multi-layer thick active layer AL.sub.THICK suitable for use in embodiments of the present invention. A first layer comprises Si, which may be doped (e.g., P+ or P) or undoped (i.e., intrinsic Si). A second layer formed on the first layer is SiGe, an alloy of Si and about 15%-45% Ge. The second layer may be formed, for example, by diffusion of Ge into Si or by epitaxial growth. The SiGe layer provides a lattice constant larger than the lattice constant of the lower Si layer. A third layer of Si is formed on the second layer, such as by epitaxial growth. The lattice spacing of the Si third layer is forced to match the lattice constant of the SiGe layer, resulting in a tensile-strained Si layer that provides improved FET performance. For example, about 13% Ge in the SiGe second layer results in about a 25% increase in electron mobility and drain current in the channel of a FET formed in and on the Si third layer.

[0044] In some embodiments, the SiGe second layer may comprise sublayers, such as a graded SiGe sublayer formed by implantation of Ge into the Si first layer, a relaxed SiGe sublayer formed by chemical vapor deposition (CVD) or epitaxial growth on the graded SiGe sublayer and partially relaxed through the introduction of dislocations, and a strained SiGe sublayer formed by CVD or epitaxial growth on the relaxed SiGe sublayer.

[0045] Another advantage of fabricating FETs in the thick active layer AL.sub.THICK is that there is sufficient vertical room to provide a body bias voltage per FET rather than using a single substrate bias voltage for all FETs. Not only does this allow independent biasing of each FET, but R.sub.ON (and thus R.sub.ON*C.sub.OFF) can improve up to about 5% to about 10% with a body bias voltage of 0V or just slightly positive voltage, compared to a conventional substrate bias voltage of about 3.0 or 3.5V for switch operation. For example, FIGS. 1A and 2 both show FETs with top-access body contacts BC coupled to corresponding body contact P+ doped regions that extend through the thick active layer AL.sub.THICK to the BOX layer 106, and shallower N+ source S and drain D regions. With a thick active layer AL.sub.THICK, an elongated body contact P+ region, and shallow S and D regions, the resistance R.sub.B of the body region underneath the gate structure 116 to the body contact P+ doped region is less than in a thin active layer AL.sub.THIN, resulting in faster and more complete depletion of the FET channel when transitioning to the OFF state.

[0046] Moreover, when using the additive process described above, since all of the thin active layer AL.sub.THIN is exposed before formation of an overlying thick active layer AL.sub.THICK, some or all of the thin active layer AL.sub.THIN that will underlie the thick active layer AL.sub.THICK may be doped (e.g., with a P-type material such as Indium for an NFET) to further lower the resistance R.sub.B of the P-well body regionsee region 130 in FIGS. 1A and 2. Since the doped thin active layer AL.sub.THIN will be spaced from the top surface of the added semiconductor material comprising the rest of the thick active layer AL.sub.THICK, such doping in the underlying thin active layer AL.sub.THIN should have little effect on carrier mobility in the channel of a FET fabricated in and on the overlying portion of the thick active layer AL.sub.THICK. Of note, the lower resistance R.sub.B of the P-well body region in the thick active layer AL.sub.THICK should help to improve the breakdown voltage BV.sub.DSS, reliability, and linearity of FETs formed in the thick active layer AL.sub.THICK, particularly for SOI N-type Extended Drain MOS (EDMOS) FETs.

[0047] FIG. 6A is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in a fully-depleted OFF state. For the voltages shown in FIG. 6A, the P-well of the FET in the thick active layer AL.sub.THICK will be fully depleted if the top of the P-well is essentially intrinsic Si, such as by retrograding the Si deposited to complete the thick active layer AL.sub.THICK. The gate voltage V.sub.G is shown in FIG. 6A as 0V, but can be a negative voltage (e.g.,3.5V or 5V) to turn the FET OFF faster and prevent current leakage between the source S and drain D. The body contact voltage V.sub.BC may also be a negative voltage. Full depletion reduces harmonics in applied RF signals. Note that the thickness selection for the thick active layer AL.sub.THICK in RF switch applications is tied to having full depletion in an OFF-state operationhigh thickness values for the thick active layer AL.sub.THICK may result in only partial depletion.

[0048] FIG. 6B is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in an ON state. For the voltages shown in FIG. 6B, a conduction channel is formed in the P-well of the FET while a portion of the P-well is partially depleted. Turn-on of the FET is dominated by the essentially intrinsic Si at the top of the P-well and is generally quite fast.

[0049] FIG. 6C is a stylized cross-sectional diagram of an example substructure of an SOI IC having a thick active layer AL.sub.THICK FET in a partially depleted OFF state. In some applications, particularly for RF switches, speed of switching states between ON and OFF is often a critical design goal. A FET having a thick active layer AL.sub.THICK enables a partially-depleted OFF state that depletes the channel underneath the gate structure 116 but leaves some body charge (indicated in FIG. 6C by + symbols) between the depletion region and the BOX layer 106. The result is that the thick active layer AL.sub.THICK FET can be more rapidly turned ON and OFF, since the depletion region is limited to the upper regions of the body beneath the gate structure 116.

[0050] Depending on the relative thicknesses of the AL.sub.THIN and AL.sub.THICK layers, it may be challenging to concurrently form STIs in both the thin active layer AL.sub.THIN and the thick active layer AL.sub.THICK, for example, because of focus issues for photolithographic process steps. One approach to overcoming this challenge is to fabricate thin and thick STIs in separate steps. For example, FIGS. 7A-7H are stylized cross-sectional diagrams of a first set of manufacturing stages for an example substructure of an SOI IC that is to have dual-thickness active areas.

[0051] In FIG. 7A, a starting point is a partial IC substructure comprising a substrate 102 (e.g., P-type Si), a trap-rich layer 104 formed on and/or in the substrate 102, and a BOX layer 106 formed on the trap-rich layer 104. In some embodiments, the trap-rich layer 104 may be omitted. A thin active layer AL.sub.THIN is then formed on the BOX layer 106 by a suitable technology (e.g., epitaxial growth of Si) to a desired thickness (e.g., about 550 ). A pad oxide 702 is formed on the thin active layer AL.sub.THIN, and a first SiN layer 704 is formed on the pad oxide 702. The combination of materials may comprise a first masking layer, but other conventional masking processes may be used for the first masking layer.

[0052] In FIG. 7B, the pad oxide 702 and the first SiN layer 704 are lithographically patterned and etched to create openings 706 for the fabrication of STIs within the portion of the IC substructure that is to retain a thin active layer AL.sub.THIN. STIs 708 are then formed by etching an opening or void through the exposed thin active layer AL.sub.THIN and filling the etched opening or void with a suitable material (e.g., SiO.sub.2, CVD oxide, or high-density plasma oxide). The pad oxide 702 and the first SiN layer 704 may be removed, such as by chemical-mechanical polishing (CMP).

[0053] In FIG. 7C, a second SiN layer 710 and a first oxide layer 712 are laid down over the thin active layer AL.sub.THIN. The combination of materials may comprise a second masking layer, but other conventional masking processes may be used for the second masking layer.

[0054] In FIG. 7D, the second SiN layer 710 and the first oxide layer 712 are lithographically patterned and etched to create an opening 714 for the fabrication of the thick active layer AL.sub.THICK.

[0055] In FIG. 7E, the remaining material for the thick active layer AL.sub.THICK is deposited within the (former) opening 714, such as by epitaxial growth of Si.

[0056] In FIG. 7F, a third SiN layer 716 and a second oxide layer 718 are laid down over the thick active layer AL.sub.THICK and the second SiN layer 710 and the first oxide layer 712 The combination of materials may comprise a third masking layer, but other conventional masking processes may be used for the third masking layer. In some embodiments, only the thick active layer AL.sub.THICK is covered by the third masking layer.

[0057] In FIG. 7G, the third SiN layer 716 and the second oxide layer 718 are lithographically patterned and etched to create openings 720 for the fabrication of STIs within the portion of the IC substructure that is to have a thick active layer AL.sub.THICK. STIs 722 are then formed by etching a void through the exposed thick active layer AL.sub.THICK and filling the etched void with a suitable material. Note that the STI material and fabrication process for the STIs 722 of this stage need not be the same material used for the thin STI's 708.

[0058] In FIG. 7H, the remaining oxides and nitride layers have been removed, such as by CMP, leaving a substructure of an SOI IC having dual-thickness active areas with corresponding STIs 708, 722.

[0059] As another example, FIGS. 8A-8H are stylized cross-sectional diagrams of a second set of manufacturing stages for an example substructure of an SOI IC that is to have dual-thickness active areas.

[0060] In FIG. 8A, a starting point is a partial IC substructure comprising a substrate 102 (e.g., P-type Si), a trap-rich layer 104 formed on and/or in the substrate 102, and a BOX layer 106 formed on the trap-rich layer 104. In some embodiments, the trap-rich layer 104 may be omitted. A thin active layer AL.sub.THIN is then formed on the BOX layer 106 by a suitable technology (e.g., epitaxial growth of Si) to a desired thickness (e.g., about 550 ). A pad oxide 802 is formed on the thin active layer AL.sub.THIN, and a first SiN layer 804 is formed on the pad oxide 802.

[0061] In FIG. 8B, the pad oxide 802 and the first SiN layer 804 are lithographically patterned and etched to create openings 806 for the fabrication of STIs. STIs 808 are then formed by etching a void through the exposed thin active layer AL.sub.THIN and filling the etched void with a suitable material. The pad oxide 802 and the first SiN layer 804 may be removed, such as by chemical-mechanical polishing (CMP).

[0062] In FIG. 8C, a second SiN layer 810 and a first oxide layer 812 are laid down over the thin active layer AL.sub.THIN.

[0063] In FIG. 8D, the second SiN layer 810 and the first oxide layer 812 are lithographically patterned and etched to create an opening 814 for the fabrication of the thick active layer AL.sub.THICK.

[0064] In FIG. 8E, the remaining material for the thick active layer AL.sub.THICK is deposited within the (former) opening 814, such as by epitaxial growth of Si.

[0065] In FIG. 8F, a third SiN layer 816 and a second oxide layer 818 are laid down over the thick active layer AL.sub.THICK and the second SiN layer 810 and the first oxide layer 812.

[0066] In FIG. 8G, the third SiN layer 816 and the second oxide layer 818 are lithographically patterned and etched to create openings 820 for the fabrication of STIs within the portion of the IC substructure that is to have a thick active layer AL.sub.THICK. A second set of STIs 822 are then formed by etching a void through the exposed thick active layer AL.sub.THICK to at least the tops of the first set of STIs 808 formed within lower portion of the thick active layer AL.sub.THICK and filling the etched void with a suitable material. Note that the STI material and fabrication process for the STIs 822 of this stage need not be the same material used for the thin STI's 808. For example, the thin or lower STI's 808 may be made using SiO.sub.2 while the upper STI's 822 may be made using high-density plasma oxide.

[0067] In FIG. 8H, the remaining oxides and nitride layers have been removed, such as by CMP, leaving a substructure of an SOI IC having dual-thickness active areas with corresponding STIs 808, 822.

[0068] It may be noted that the bottoms of the second set of STIs 822 need not exactly match the tops of the corresponding first set of STIs 808 within the thick active layer AL.sub.THICK, but may be smaller or larger. The second set of STIs 822 may even penetrate somewhat into the first set of STIs 808 within the thick active layer AL.sub.THICK if the etchant used to make openings 820 is somewhat aggressive or used too long.

[0069] It should be appreciated that a number of other embodiments of the disclosed substructure having dual-thickness active areas may include additional or variant structures, features, and materials compatible with CMOS IC fabrication processes, both during FEOL and BEOL processing stages.

[0070] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0071] As one example of further integration of embodiments of the present invention with other components, FIG. 9 is a top plan view of a substrate 900 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 900 includes multiple ICs 902a-902d having terminal pads 904 which would be interconnected by conductive vias and/or traces on and/or within the substrate 900 or on the opposite (back) surface of the substrate 900 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 902a-902d may embody, for example, signal switches, active and/or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 902b may incorporate one or more instances of an SOI IC having dual-thickness active areas.

[0072] The substrate 900 may also include one or more passive devices 906 embedded in, formed on, and/or affixed to the substrate 900. While shown as generic rectangles, the passive devices 906 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 900 to other passive devices 906 and/or the individual ICs 902a-902d. The front or back surface of the substrate 900 may be used as a location for the formation of other structures.

[0073] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) RF switches, RF power amplifiers, RF low-noise amplifiers (LNAs), RF phase shifters, RF attenuators, antenna beam-steering systems, charge pump devices, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0074] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (OFDM), quadrature amplitude modulation (QAM), Code-Division Multiple Access (CDMA), Time-Division Multiple Access (TDMA), Wide Band Code Division Multiple Access (W-CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0075] Another aspect of the invention includes methods for fabricating a substructure of a silicon-on insulator integrated circuit having dual-thickness active areas. For example, FIG. 10 is a process flow chart 1000 showing a first method for fabricating a substructure of an SOI IC having dual-thickness active areas. The method includes: providing a substrate (Block 1002); forming a buried oxide layer on the substrate (Block 1004); forming a thin active layer on the buried oxide layer (Block 1006); and adding semiconductor material on selected regions of the thin active layer to form a thick active layer (Block 1008).

[0076] As another example, FIG. 11 is a process flow chart 1100 showing a second method for fabricating a substructure of an SOI IC having dual-thickness active areas. The method includes: providing a substrate (Block 1102); forming a buried oxide layer on the substrate (Block 1104); forming a thick active layer on the buried oxide layer (Block 1106); and removing selected portions of the thick active layer to form a thin active layer (Block 1108).

[0077] Additional aspects of the above methods may include one or more of the following: wherein the thin active layer has a thickness at or below about 550 ; wherein the thick active layer has a thickness at or above about 1000 ; wherein the thick active layer is formed by epitaxial growth of one or more semiconductor materials on selected regions of the thin active layer; wherein the thin active layer underlying the thick active layer is doped to lower a resistance of the thick active layer; further including forming a heat dissipation layer between the buried oxide layer and the thin and thick active layers; further including forming a silicon carbide layer between the buried oxide layer and the thin and thick active layers; and/or wherein the substrate is one of P-type silicon, intrinsic silicon, high-resistivity silicon, porous silicon, or sapphire.

[0078] The term MOSFET, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms metal or metal-like include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), insulator includes at least one insulating material (such as silicon oxide or other dielectric material), and semiconductor includes at least one semiconductor material.

[0079] As used in this disclosure, the term radio frequency (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0080] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., top, bottom, above, below, lateral, vertical, horizontal, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0081] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as bipolar junction transistors (BJTs), BiCMOS, BCD including LDMOS, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHZ). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0082] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially stacking components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0083] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

[0084] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).