SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

Claims

1. A semiconductor device comprising: a power rail; an insulating layer disposed on the power rail; a first channel disposed on the insulating layer; a second channel disposed on the first channel; a gate structure disposed on the first channel and the second channel; a source/drain disposed adjacent the gate structure; and a first via disposed between the power rail and the source/drain, and electrically connecting the source/drain and the power rail, wherein a portion of the gate structure is disposed between the first channel and the second channel.

2. The semiconductor device of claim 1, wherein a top surface of the first via and a bottom surface of the insulating layer are disposed at the same vertical level.

3. The semiconductor device of claim 1, wherein the insulating layer extends between the first channel and the power rail.

4. The semiconductor device of claim 1, wherein the source/drain extends through the insulating layer.

5. The semiconductor device of claim 1, wherein the first via directly contacts the power rail.

6. The semiconductor device of claim 1, wherein the insulating layer includes silicon oxide or silicon oxynitride.

7. The semiconductor device of claim 1, further comprising: an interconnection line disposed on the gate structure; and a second via disposed between the interconnection line and the source/drain, and electrically connecting the interconnection line and the source/drain.

8. The semiconductor device of claim 1, wherein the semiconductor device has a gate-all-around structure.

9. A semiconductor device comprising: a power rail; a first channel over the power rail; a second channel over the first channel; an insulating layer extending between the first channel and the power rail; a gate structure over the first channel, the second channel and the insulating layer; a source/drain adjacent the gate structure, and extending through the insulating layer; and a first via directly contacting the power rail, and electrically connecting the power rail and the source/drain, wherein a portion of the gate structure is disposed between the first channel and the second channel.

10. The semiconductor device of claim 9, further comprising a first contact electrically connected to the source/drain and the first via.

11. The semiconductor device of claim 9, wherein a top surface of the first via and a bottom surface of the insulating layer are disposed at the same vertical level.

12. The semiconductor device of claim 9, wherein the first via directly contacts the power rail.

13. The semiconductor device of claim 9, further comprising: an interconnection line disposed on the gate structure; and a second via disposed between the interconnection line and the source/drain, and electrically connecting the interconnection line and the source/drain.

14. The semiconductor device of claim 9, wherein the semiconductor device has a gate-all-around structure.

15. A semiconductor device comprising: a substrate; a fin-shaped active pattern disposed on the substrate and including a first channel and a second channel disposed on the first channel; a first gate structure crossing the fin-shaped active pattern; a second gate structure crossing the fin-shaped active pattern; a source/drain disposed between the first gate structure and the second gate structure; an insulating layer disposed on the first gate structure and the second gate structure; a power rail disposed on the insulating layer; and a first via disposed between the power rail and the source/drain, and electrically connecting the source/drain and the power rail, wherein a portion of the first gate is disposed between the first channel and the second channel.

16. The semiconductor device of claim 15, further comprising: an interconnection line disposed on the substrate; and a second via disposed between the interconnection line and the source/drain, and electrically connecting the interconnection line and the source/drain.

17. The semiconductor device of claim 16, further comprising: an upper contact coupled to the source/drain and the first via; and a lower contact coupled to the source/drain and the second via.

18. The semiconductor device of claim 17, wherein the lower contact is trapezoid-shaped.

19. The semiconductor device of claim 15, wherein the semiconductor device has a gate-all-around structure.

20. The semiconductor device of claim 15, wherein the insulating layer electrically isolates the power rail from the first channel and/or the second channel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, exemplary embodiments as described herein.

[0009] FIG. 1 is a top plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concepts.

[0010] FIGS. 2A to 2C are cross-sectional views taken along lines A-A, B-B, and C-C, respectively, of FIG. 1 according to exemplary embodiments of the present inventive concepts.

[0011] FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1 illustrating a semiconductor device according to an exemplary embodiment of the present inventive concepts.

[0012] FIGS. 4A and 4B are cross-sectional views taken along line A-A of FIG. 1 illustrating a semiconductor device according to exemplary embodiments of the present inventive concepts.

[0013] FIG. 5 is a cross-sectional view taken along a line A-A of FIG. 1 illustrating a semiconductor device according to an exemplary embodiment of the present inventive concepts.

[0014] FIGS. 6, 8, 10, 12, 14, and 16 are top plan views illustrating a method of fabricating a semiconductor device according to exemplary embodiments of the present inventive concepts.

[0015] FIGS. 7A, 9A, 11A, 13A, 15A, and 17A are cross-sectional views taken along lines A-A of FIGS. 6, 8, 10, 12, 14, and 16, respectively, according to exemplary embodiments of the present inventive concepts.

[0016] FIGS. 7B, 9B, 11B, 13B, 15B, and 17B are cross-sectional views taken along lines B-B of FIGS. 6, 8, 10, 12, 14, and 16, respectively, according to exemplary embodiments of the present inventive concepts.

[0017] It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain exemplary embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the exact structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by exemplary embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0018] Exemplary embodiments of the present inventive concepts will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0019] FIG. 1 is a top plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concepts. FIGS. 2A to 2C are cross-sectional views taken along lines A-A, B-B, and C-C, respectively, of FIG. 1 according to exemplary embodiments of the present inventive concepts.

[0020] Referring to FIGS. 1 and 2A to 2C, a lower substrate 102 may include a p-channel metal-oxide field-effect transistor (PMOSFET) region PR and an n-channel metal-oxide field-effect transistor (NMOSFET) region NR. The lower substrate 102 may be a semiconductor substrate, which is formed of or includes silicon, germanium, or silicon-germanium, or a compound semiconductor substrate. For example, the lower substrate 102 may be a silicon wafer. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0021] In an exemplary embodiment, the PMOSFET and NMOSFET regions PR and NR may be logic cell regions, on which logic transistors constituting a logic circuit of a semiconductor device are formed. For example, logic transistors constituting a processor core or I/O terminals may be disposed on the logic cell region of the lower substrate 102. The PMOSFET region PR and the NMOSFET region NR may include some of the logic transistors. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2 that is perpendicular to the first direction D1.

[0022] A plurality of active patterns AP1 and AP2 extending in the second direction D2 may be provided on the PMOSFET region PR and the NMOSFET region NR. For example, as shown in the exemplary embodiment of FIG. 1, the active patterns AP1 and AP2 may include first active patterns AP1 on the PMOSFET region PR and second active patterns AP2 on the NMOSFET region NR. The first and second active patterns AP1 and AP2 may be provided on a top surface of the lower substrate 102 (e.g., in the third direction D3) and may have a fin-shape structure protruding in the third direction D3 that is perpendicular to the top surface of the lower substrate 102. Each of the first and second active patterns AP1 and AP2 may include a bottom surface APb, which faces the top surface of the lower substrate 102, and a top surface APa, which is opposite to the bottom surface APb (e.g., in the third direction D3).

[0023] In the present specification, spatially relative terms, such as beneath, below, lower, bottom, top, above, upper and the like, may be used herein for ease of description to describe the relationship of one element or feature to other element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, as shown in FIGS. 6 to 11B, if the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. Therefore, the exemplary term below can encompass both an orientation of above and below. Similarly, a semiconductor that extends in the first direction D1 may be rotated to change the direction of the semiconductor to the second direction D2, the third direction D3, etc. The semiconductor device according to exemplary embodiments of the present inventive concepts may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0024] Gate electrodes GE may cross the first and second active patterns AP1 and AP2 and extend in the first direction D1. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrodes GE may overlap with channel regions CH1, when viewed in a plan view. Each of the gate electrodes GE may be disposed to face a bottom surface of each of the channel regions CH and two side surfaces of each of the channel regions, which are opposite to each other and which extend in the third direction D3 and are spaced apart in the first direction D1 (see FIG. 2C). The gate electrodes GE may be formed of or include at least one of, for example, conductive metal nitrides (e.g., titanium nitride or tantalum nitride) or metallic materials (e.g., titanium, tantalum, tungsten, copper, or aluminum). However, exemplary embodiments of the present inventive concepts are not limited thereto. A portion of the gate electrodes GE may be positioned between (e.g., spaced apart in the third direction D3 between) the bottom surfaces APb of the first and second active patterns AP1 and AP2 and the top surface of the lower substrate 102, as shown in FIG. 2A. In addition, the uppermost surface of the gate electrodes GE may be positioned at a level that is not higher than the level of the top surfaces APa of the first and second active patterns AP1 and AP2. For example, the distance between the top surface of the lower substrate to the uppermost surface of the gate electrodes (e.g., in the third direction D3) may be less than or equal to the distance (e.g., in the third direction D3) between the top surface of the lower substrate and the top surfaces APa of the first and second active patterns AP1 and AP2.

[0025] A pair of gate spacers GS may be respectively disposed on two opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend along the gate electrodes GE in the first direction D1. Bottom surfaces of the gate spacers GS may be located at a level that is lower than bottom surfaces of the gate electrodes GE. For example, the distance (e.g., in the third direction D3) between the top surface of the lower substrate to the bottom surfaces of the gate spacers GS may be less than the distance (e.g., in the third direction D3) between the top surface of the lower substrate to the bottom surfaces of the gate electrodes GE. The bottom surfaces of the gate spacers GS may be coplanar with a bottom surface of a first lower insulating layer 112 to be described below. The gate spacers GS may be formed of or include at least one of SiCN, SiCON, or SiN. In an exemplary embodiment, the gate spacers GS may have a multi-layered structure including at least two layers, each of which is made of SiCN, SiCON, or SiN. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0026] Gate dielectric patterns GI may be interposed between the gate electrodes GE and the first and second active patterns AP1 and AP2. Each of the gate dielectric patterns GI may extend along a top surface (e.g., in the third direction D3) of a corresponding one of the gate electrodes GE. Each of the gate dielectric patterns GI may cover a bottom surface (e.g., in the third direction D3) and both side surfaces of each of the channel regions CH1 which extend in the third direction D3 and are spaced apart in the first direction D1. The gate dielectric patterns GI may be formed of or include at least one of high-k dielectric materials. Examples of the high-k dielectric materials may include at least one selected from: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0027] A gate capping pattern GP may be disposed on the bottom surface (e.g., in the third direction D3) of each of the gate electrodes GE. The gate capping patterns GP may extend along the gate electrodes GE in the first direction D1. The gate capping patterns GP may include a material that has an etch selectivity with respect to first and second lower insulating layers 112 and 114 to be described below. For example, the gate capping patterns GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0028] First source/drain patterns SD1 may be provided on side surfaces of the first active patterns AP1. The first source/drain patterns SD1 may include impurities of a first conductivity type (e.g., p-type). A first channel region CH1 may be interposed between a pair of the first source/drain patterns SD1. Second source/drain patterns SD2 may be disposed on side surfaces of the second active patterns AP2. The second source/drain patterns SD2 may include impurities of a second conductivity type (e.g., n-type). A second channel region CH2 may be interposed between a pair of the second source/drain patterns SD2.

[0029] The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns that are formed by a selective epitaxial growth process. Bottom surfaces of the first and second source/drain patterns SD1 and SD2 may be positioned at a level that is lower than the bottom surfaces of the first and second channel regions CH1 and CH2. For example, the distance (e.g., in the third direction D3) between the top surface of the lower substrate 102 to the bottom surfaces of the first and second source/drain patterns SD1 and SD2 may be less than the distance (e.g., in the third direction) between the top surface of the lower substrate to the bottom surfaces of the first and second channel regions. The first and second source/drain patterns SD1 and SD2 may have top surfaces that are positioned at a higher level than the top surfaces of the first and second channel regions CH1 and CH2. For example, the distance (e.g., in the third direction D3) between the top surface of the lower substrate 102 to the top surfaces of the first and second source/drain patterns SD1 and SD2 may be greater than the distance (e.g., in the third direction) between the top surface of the lower substrate to the top surfaces of the first and second channel regions CH1 and CH2. The first source/drain patterns SD1 may include a semiconductor material (e.g., SiGe), whose lattice constant is greater than the lattice constant of the lower substrate 102. In this exemplary embodiment, the first source/drain patterns SD1 may exert a compressive stress to the first channel regions CH1. In an exemplary embodiment, the second source/drain patterns SD2 may include the same semiconductor material (e.g., Si) as the material of the lower substrate 102.

[0030] The first source/drain patterns SD1 may penetrate a first upper insulating layer 120 to be described below and may be extended to cover a portion of a top surface of the first upper insulating layer 120. Each of the first source/drain patterns SD1 may include a first portion SDB and a second portion SDE extended from the first portion SDB (e.g., in the third direction D3). The first portion SDB of the first source/drain patterns SD1 may be positioned between opposite sidewalls of the first active patterns AP1 (e.g., in the second direction D2). The second portion SDE of the first source/drain patterns SD1 may be located at a vertical level higher than the top surface APa of the first active pattern AP1. For example, the distance (e.g., in the third direction D3) between the top surface of the lower substrate 102 to the second portion SDE of the first source/drain patterns SD1 may be greater than the distance (e.g., in the third direction D3) between the top surface of the lower substrate to the top surface APa of the first active pattern AP1. As shown in FIG. 2A, the largest width W2 (e.g., length in the second direction D2) of the second portion SDE of the first source/drain patterns SD1 may be larger than the largest width W1 (e.g., length in the second direction D2) of the first portion SDB of the first source/drain patterns SD1. For example, the first source/drain patterns SD1 may have the largest width at a level that is higher (e.g., in the third direction D3) than the top surface APa of the first active patterns AP1.

[0031] A first upper insulating layer 120, a second upper insulating layer 122, and a third upper insulating layer 124 may be sequentially stacked on the top surface APa of the first active pattern AP1. For example, as shown in FIG. 2A, the second upper insulating layer 122 may be disposed directly on a top surface of the first upper insulating layer 120 (e.g., in the third direction D3). The third upper insulating layer 124 may be disposed directly on a top surface of the second upper insulating layer 122 (e.g., in the third direction D3).

[0032] Each of the first to third upper insulating layers 120, 122, and 124 may include a silicon oxide layer or a silicon oxynitride layer. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0033] Upper contacts UAC may penetrate the second upper insulating layer 122 and may be electrically connected to the first and second source/drain patterns SD1 and SD2. The upper contacts UAC may have bar-shape patterns extending in the first direction D1. For example, as shown in the exemplary embodiment of FIG. 2A, the upper contacts UAC may be disposed directly on a top surface of the second portion SDE of the first source/drain patterns SD1 and second source/drain patterns SD2 (e.g., in the third direction D3).

[0034] A first upper interconnection line POR1, a second upper interconnection line POR2, and upper vias UV may be provided in the third upper insulating layer 124. For example, as shown in FIG. 2A, a bottom surface of the upper vias UV (e.g., in the third direction D3) may directly contact a top surface (e.g., in the third direction D3) of the upper contacts UAC. A bottom surface of the first upper interconnection line POR1 may contact a top surface of the upper vias UV. The upper vias UV may connect the first upper interconnection line POR1 and second upper interconnection line POR2 to the upper contacts UAC. The first upper interconnection line POR1 and the second upper interconnection line POR2 may be a power rail, such as a buried power rail. For example, the first upper interconnection line POR1 and the second upper interconnection line POR2 may be applied with a power voltage or a ground voltage. The first upper interconnection line POR1 may be connected to at least one of the first source/drain patterns SD1 through the upper via UV. The second upper interconnection line POR2 may be connected to at least one of the second source/drain patterns SD2 through the upper via UV. The first upper interconnection line POR1 may be used to apply the power voltage to the first source/drain patterns SD1, and the second upper interconnection line POR2 may be used to apply the ground voltage to the second source/drain patterns SD2.

[0035] The first upper interconnection line POR1 and the second upper interconnection line POR2 may extend in the second direction D2. A width (e.g., length in the first direction D1) of the first upper interconnection line POR1 may be larger than a width (e.g., length in the first direction D1) of the first active pattern AP1. The first upper interconnection line POR1 may at least partially overlap (e.g., in the third direction D3) each of the first source/drain patterns SD1, which are disposed below the same, when viewed in a plan view. Similarly, a width (e.g., length in the first direction D1) of the second upper interconnection line POR2 may be larger than a width (e.g., length in the first direction D1) of the second active pattern AP2. The second upper interconnection line POR2 may at least partially overlap (e.g., in the third direction D3) each of the second source/drain patterns SD2, which are disposed below the same, when viewed in a plan view.

[0036] A first lower insulating layer 112, a second lower insulating layer 114, and a third lower insulating layer 116 may be disposed between the first and second active patterns AP1 and AP2 and the lower substrate 102.

[0037] The first lower insulating layer 112 may be disposed on the bottom surfaces APb of the first and second active patterns AP1 and AP2. For example, a top surface (e.g., in the third direction D3) of the first lower insulating layer 112 may be disposed directly on the bottom surface APb of the first and second active patterns AP1, AP2. The first lower insulating layer 112 may cover the gate spacers GS and the first and second source/drain patterns SD1 and SD2. A bottom surface (e.g., in the third direction D3) of the first lower insulating layer 112 may be substantially coplanar with bottom surfaces of the gate capping patterns GP and the bottom surfaces of the gate spacers GS. The second lower insulating layer 114 may be formed on the bottom surface of the first lower insulating layer 112 and may cover the gate capping patterns GP. For example, the top surface (e.g., in the third direction D3) of the second lower insulating layer 114 may be disposed directly on the bottom surface of the first lower insulating layer 112. The first and second lower insulating layers 112 and 114 may include, for example, a silicon oxide layer. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0038] Lower contacts LAC may be disposed to penetrate the first and second lower insulating layers 112 and 114 and may be electrically connected to the first and second source/drain patterns SD1 and SD2. For example, contact holes may be formed in the first and second lower insulating layers 112 and 114 to penetrate the first and second lower insulating layers 112 and 114 and to expose the first or second source/drain pattern SD1 and SD2. The lower contact LAC may be provided in the contact hole. The lower contacts LAC may be disposed between a pair of the gate electrodes GE. The lower contacts LAC may extend from the first portion SDB of the first source/drain patterns SD1 to a bottom surface (e.g., in the third direction D3) of the second lower insulating layer.

[0039] Lower interconnection lines LML and lower vias LV may be provided in the third lower insulating layer 116. For example, as shown in the exemplary embodiment of FIG. 2A, the bottom surface (e.g., in the third direction D3) of the lower contacts LAC may be disposed on a top surface of the third lower insulating layer 116 and may directly contact a top surface of the lower substrate 102. However, exemplary embodiments of the present inventive concepts are not limited thereto. The lower vias LV may connect the lower contacts LAC to the lower interconnection lines LML. For example, as shown in FIG. 2A a top surface (e.g., in the third direction D3) of the lower vias LV may contact a bottom surface (e.g., in the third direction D3) of the lower contacts LAC. A top surface (e.g., in the third direction D3) of the lower interconnection lines LML may contact a bottom surface (e.g., in the third direction D3) of the lower vias LV.

[0040] As shown in FIG. 2C, gate contacts GC may be provided to penetrate the second lower insulating layer 114 and the gate capping patterns GP and may be electrically connected to the gate electrodes GE. In an exemplary embodiment, the gate contact GC may be disposed between the PMOSFET and NMOSFET regions PR and NR, when viewed in a plan view. For example, the gate contact GC may be spaced apart from the PMOSFET and NMOSET regions PR and NR in the first direction D1. The gate contact GC may penetrate the gate capping pattern GP and may be in contact with a bottom surface of the gate electrode GE. A bottom surface (e.g., in the third direction D3) of the gate contact GC may be coplanar with a bottom surface (e.g., in the third direction D3) of the second lower insulating layer 114. The gate contact GC extends in a downward direction to the lower interconnection lines LML in an opposite direction as the upper contacts UAC which extend upwardly to the first and second upper interconnection lines POR1 and POR2.

[0041] FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1 according to an exemplary embodiment of the present inventive concepts.

[0042] Referring to FIG. 3, unlike the exemplary embodiment shown in FIG. 2A, the exemplary embodiment in FIG. 3 includes a top surface of the first active pattern AP1 that is positioned at a level higher than an interface between the first and second portions SDB and SDE of the first source/drain pattern SD1. For example, the distance between the top surface (e.g., in the third direction D3) of the lower substrate 102 to the top surface (e.g., in the third direction D3) of the first active pattern AP1 is greater than the distance between the top surface of the lower substrate to the interface between the first and second portions SDB and SDE of the first source/drain pattern SD1.

[0043] FIGS. 4A and 4B are cross-sectional views taken along line A-A of FIG. 1 illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0044] Referring to FIG. 4A, the second portion SDE of the first source/drain pattern SD1 may include first and second members SDE-1, SDE-2, which are spaced apart from each other in the first direction D1. Each of the first and second members SDE-1, SDE-2 may penetrate the first upper insulating layer 120 and may be connected to the first portion SDB of the first source/drain pattern SD1. The portions of the first and second members SDE-1, SDE-2 of the second portion SDE that penetrate the first upper insulating layer 120 may have a width (e.g., a length in the first direction D1) that is narrower than the portion of the first and second members that are disposed above the first upper insulating layer.

[0045] Referring to the exemplary embodiment shown in FIG. 4B, the second portion SDE of the first source/drain pattern SD1 may be connected to the first portion SDB of the first source/drain pattern SD1 through one opening formed in the first upper insulating layer 120. Therefore, the first and second portions SDB and SDE of the first source/drain pattern SD1 may be seamlessly connected to each other, without the first upper insulating layer 120 or the first lower insulating layer 112 interposed therebetween.

[0046] FIG. 5 is a cross-sectional view taken along line A-A of FIG. 1 illustrating a semiconductor device according to an exemplary embodiment of the present inventive concepts.

[0047] Referring to FIG. 5, a semiconductor device according to an exemplary embodiment of the present inventive concepts may have a gate-all-around structure. For example, the first active pattern AP1 may include a plurality of channel regions CHP, which are interposed between adjacent source drain patterns SD1. The channel regions CHP may be stacked and vertically spaced apart from each other. Insulation patterns ILL may be interposed between the first source drain patterns SD1 and the gate electrodes GE. The insulation patterns ILL may be interposed between the channel regions CHP. The insulating patterns ILL may electrically isolate the gate electrode GE from the first source drain patterns SD1.

[0048] FIGS. 6, 8, 10, 12, 14, and 16 are top plan views illustrating a method of fabricating a semiconductor device according to exemplary embodiments of the present inventive concepts. FIGS. 7A, 9A, 11A, 13A, 15A, and 17A are cross-sectional views taken along lines A-A of FIGS. 6, 8, 10, 12, 14, and 16, respectively. FIGS. 7B, 9B, 11B, 13B, 15B, and 17B are cross-sectional views taken along lines B-B of FIGS. 6, 8, 10, 12, 14, and 16, respectively.

[0049] For convenience of explanation with respect to a method of fabricating a semiconductor device according to exemplary embodiments of the present inventive concepts, a capsized shape of a semiconductor device is illustrated in FIGS. 6 to 11B. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0050] Referring to FIGS. 6, 7A, and 7B, a substrate 100 including the first and second active patterns AP1 and AP2 may be formed. The substrate 100 may include an etch stop layer ESL.

[0051] In an exemplary embodiment, an ion implantation process and/or an epitaxial growth process may be performed on a semiconductor layer to form the etch stop layer ESL. Thereafter, the substrate 100 including the etch stop layer ESL may be formed by growing a semiconductor layer on the etch stop layer ESL. In an exemplary embodiment, the substrate 100 may be formed of or include silicon and silicon germanium. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0052] The substrate 100 including the etch stop layer ESL may be patterned to form the first and second active patterns AP1 and AP2. The etch stop layer ESL may be positioned below the first and second active patterns AP1 and AP2.

[0053] A device isolation layer ST may be formed on the substrate 100 to fill gap regions between the first and second active patterns AP1 and AP2. The device isolation layer ST may be formed of or include an insulating material, such as silicon oxide. However, exemplary embodiments of the present inventive concepts are not limited thereto.

[0054] Referring to FIGS. 8, 9A, and 9B, the first and second source/drain patterns SD1 and SD2 and a gate structure GST may be formed on the first active patterns AP1.

[0055] For example, the first portions SDB of the first source/drain patterns SD1 may be formed on the first active patterns AP1. As shown in the exemplary embodiment of FIG. 9A, the first portions SDB of the first source/drain patterns SD1 may be formed directly on the first active patterns AP1. The first portions SDB of the second source/drain patterns SD2 may be formed on the second active patterns AP2. For example, the first portions SDB of the second source/drain patterns SD2 may be formed directly on the second active patterns AP2. The first portions SDB of the first source/drain patterns SD1 may be doped with p-type impurities, and the first portions SDB of the second source/drain patterns SD2 may be doped with n-type impurities. However, exemplary embodiments of the present inventive concepts are not limited thereto. For example, in other exemplary embodiments, the first portions SDB of the first source/drain patterns SD1 may be doped with n-type impurities, and the first portions SDB of the second source/drain patterns SD2 may be doped with p-type impurities.

[0056] The first portions SDB of the first and second source/drain patterns SD1 and SD2 may be epitaxial patterns, which are formed by a selective epitaxial growth process. For example, the first and second active patterns AP1 and AP2 may be partially recessed. An epitaxial growth process may be subsequently performed on the recessed portions of the first and second active patterns AP1 and AP2. The first lower insulating layer 112 may be formed to cover the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0057] Thereafter, the gate electrodes GE may be formed to cross the first and second active patterns AP1 and AP2 and to extend in the first direction D1. The gate dielectric layers GI may be formed between the gate electrodes GE and the first and second active patterns AP1, AP2, respectively. The gate spacers GS may be formed on both side surfaces of each of the gate electrodes GE. Gate capping layers GP may be formed on the gate electrodes GE, respectively.

[0058] Referring to FIGS. 10, 11A, and 11B, the lower interconnection lines LML may be formed to be electrically connected to the first portions SDB of the first and second source/drain patterns SD1 and SD2. For example, the second lower insulating layer 114 may be formed on the first lower insulating layer 112. The lower contact LAC may be formed to penetrate the first lower insulating layer 112 and the second lower insulating layer 114 and may be coupled to the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0059] The third lower insulating layer 116 may be formed on the second lower insulating layer 114. For example, a bottom surface of the third lower insulating layer 116 may be formed directly on a top surface of the second lower insulating layer 114. The lower interconnection lines LML and the lower vias LV, which connect the lower interconnection lines LML to the lower contact LAC, may be formed in the third lower insulating layer 116.

[0060] Referring to FIGS. 12, 13A, and 13B, the lower substrate 102 may be formed. A wafer bonding process may be performed such that a bottom surface (e.g., in the third direction D3) of the third lower insulating layer 116 faces the top surface of the lower substrate 102. The lower substrate 102 may be a carrier substrate or an interconnection substrate. In an exemplary embodiment in which the lower substrate 102 is an interconnection substrate, interconnection lines in the lower substrate 102 may be electrically connected to the lower interconnection lines LML.

[0061] Referring to FIGS. 14, 15A, and 15B, a portion of the substrate 100 may be removed to expose the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0062] For example, the partial removal of the substrate 100 may include performing an etching process to expose the etch stop layer ESL and performing a CMP process to expose the top surfaces of the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0063] In an exemplary embodiment, as a result of the partial removal of the substrate 100, the first active patterns AP1 may be divided into a plurality of patterns arranged in the second direction D2. For example, as shown in FIG. 15A, one first active pattern AP1 including one channel region CH1 may be disposed between opposite sidewalls of the first and second source/drain patterns SD1 and SD2.

[0064] Referring to FIGS. 16, 17A, and 17B, the second portions SDE of the first and second source/drain patterns SD1 and SD2 may be formed on the first portions SDB of the first and second source/drain patterns SD1 and SD2. For example, a bottom surface (e.g., in the third direction D3) of the second portions SDE of the first and second source/drain patterns SD1 and SD2 may be formed directly on a top surface (e.g., in the third direction D3) of the first portions SDB of the first and second source/drain patterns. The second portions SDE of the first and second source/drain patterns SD1 and SD2 may be epitaxial patterns, which are grown from the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0065] For example, the first upper insulating layer 120 may be formed on the first and second active patterns AP1 and AP2 and the first and second source/drain patterns SD1 and SD2. Thereafter, a patterning process may be performed on the first upper insulating layer 120 to form openings exposing top surfaces of the first portions SDB of the first and second source/drain patterns SD1 and SD2. Next, an epitaxial growth process may be performed to form the second portions SDE of the first and second source/drain patterns SD1 and SD2. The epitaxial growth process may be performed such that the width W2 of the second portions SDE of the first and second source/drain patterns SD1 and SD2 is larger than the width W1 of the first portions SDB of the first and second source/drain patterns SD1 and SD2.

[0066] Referring back to FIGS. 1, 2A, and 2B, the second upper insulating layer 122 may be formed on the first upper insulating layer 120. For example, a bottom surface of the second upper insulating layer 122 (e.g., in the third direction D3) may be disposed directly on a top surface of the first upper insulating layer 120. The upper contacts UAC may be formed to penetrate the second upper insulating layer 122. The upper contacts UAC may be respectively coupled to the second portions SDE of the first and second source/drain patterns SD1 and SD2.

[0067] The third upper insulating layer 124 may be formed on the second upper insulating layer 122 to cover the upper contacts UAC. The first and second upper interconnection lines POR1 and POR2 and the upper via UV may be formed in the third upper insulating layer 124. The upper via UV may be formed to electrically connect the first and second upper interconnection lines POR1 and POR2 to at least one upper contact UAC.

[0068] In a semiconductor device according to an exemplary embodiment of the inventive concept, a power transfer network is stably formed on a second surface of a semiconductor substrate. As a result, it may be possible to increase the reliability and integration density of the semiconductor device.

[0069] While exemplary embodiments of the present inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.