MEMORY DEVICE INCLUDING A SUPERLATTICE GETTERING LAYER

Abstract

A semiconductor device may include a semiconductor substrate and a memory device on the semiconductor substrate including a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel. The semiconductor device may further include a superlattice gettering layer between the substrate and the MIC channel. The superlattice gettering layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice gettering layer may further include gettered metal particles from the MIC channel.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a memory device on the semiconductor substrate comprising a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel; and a superlattice gettering layer between the substrate and the MIC channel, the superlattice gettering layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; the superlattice gettering layer further comprising gettered metal particles from the MIC channel.

2. The semiconductor device of claim 1 wherein the memory device comprises a NAND memory device.

3. The semiconductor device of claim 1 wherein the MIC channel comprises a vertical MIC channel extending vertically upward from the substrate.

4. The semiconductor device of claim 3 wherein the gate comprises a stack of alternating gate insulator layers and gate electrode layers.

5. The semiconductor device of claim 4 wherein each gate electrode layer comprises a tungsten gate electrode.

6. The semiconductor device of claim 1 further comprising a doped diffusion layer in the semiconductor substrate, and wherein the superlattice gettering layer is within the doped diffusion layer.

7. The semiconductor device of claim 1 further comprising an oxide-nitride-oxide liner between the gate and the MIC channel.

8. The semiconductor device of claim 1 wherein the gettered metal particles comprise nickel particles.

9. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.

10. The semiconductor device of claim 1 wherein the non-semiconductor monolayers comprise oxygen.

11. A semiconductor device comprising: a semiconductor substrate; a NAND memory device on the semiconductor substrate comprising a vertical metal induced crystallization (MIC) channel extending vertically upward from the semiconductor substrate, and a gate surrounding the vertical MIC channel; and a superlattice gettering layer between the substrate and the MIC channel, the superlattice gettering layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; the superlattice gettering layer further comprising gettered metal particles from the MIC channel, and the gettered metal particles comprising nickel.

12. The semiconductor device of claim 11 wherein the gate comprises a stack of alternating gate insulator layers and gate electrode layers.

13. The semiconductor device of claim 12 wherein each gate electrode layer comprises a tungsten gate electrode.

14. The semiconductor device of claim 11 further comprising a doped diffusion layer in the semiconductor substrate, and wherein the superlattice gettering layer is within the doped diffusion layer.

15. The semiconductor device of claim 11 further comprising an oxide-nitride-oxide liner between the gate and the MIC channel.

16. A semiconductor device comprising: a semiconductor substrate; a memory device on the semiconductor substrate comprising a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel; and a superlattice gettering layer between the substrate and the MIC channel, the superlattice gettering layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; the superlattice gettering layer further comprising gettered metal particles from the MIC channel.

17. The semiconductor device of claim 16 wherein the memory device comprises a NAND memory device.

18. The semiconductor device of claim 16 wherein the MIC channel comprises a vertical MIC channel extending vertically upward from the substrate.

19. The semiconductor device of claim 18 wherein the gate comprises a stack of alternating gate insulator layers and gate electrode layers.

20. The semiconductor device of claim 19 wherein each gate electrode layer comprises a tungsten gate electrode.

21. The semiconductor device of claim 16 further comprising a doped diffusion layer in the semiconductor substrate, and wherein the superlattice gettering layer is within the doped diffusion layer.

22. The semiconductor device of claim 16 further comprising an oxide-nitride-oxide liner between the gate and the MIC channel.

23. The semiconductor device of claim 16 wherein the gettered metal particles comprise nickel particles.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.

[0017] FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.

[0018] FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.

[0019] FIG. 4 is cross-sectional diagram of a memory device including a superlattice gettering layer in accordance with an example embodiment.

[0020] FIGS. 5A-5J are a series of cross-sectional diagrams illustrating an example method for making the memory device of FIG. 4.

[0021] FIG. 6 is graph including SIMS profiles of Ni in the memory device of FIG. 4 with MST gettering layer, as well as in a similar device without the MST gettering layer.

DETAILED DESCRIPTION

[0022] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

[0023] Generally speaking, the present disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide performance enhancement characteristics. The enhanced semiconductor superlattice may also be referred to as an MST layer or MST technology in this disclosure.

[0024] More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice 25 described further below. In prior work, Applicant theorized that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. See, e.g., U.S. Pat. No. 6,897,472, which is hereby incorporate herein in its entirety by reference.

[0025] Further development by Applicant has established that the presence of MST layers may advantageously improve the mobility of free carriers in semiconductor materials, e.g., at interfaces between silicon and insulators like SiO.sub.2 or HfO.sub.2. Applicant theorizes, without wishing to be bound thereto, that this may occur due to various mechanisms. One mechanism is by reducing the concentration of charged impurities proximate to the interface, by reducing the diffusion of these impurities, and/or by trapping the impurities so they do not reach the interface proximity. Charged impurities cause Coulomb scattering, which reduces mobility. Another mechanism is by improving the quality of the interface. For example, oxygen emitted from an MST film may provide oxygen to a SiSiO.sub.2 interface, reducing the presence of sub-stoichiometric SiO.sub.x. Alternately, the trapping of interstitials by MST layers may reduce the concentration of interstitial silicon proximate to the SiSiO.sub.2 interface, reducing the tendency to form sub-stoichiometric SiO.sub.x. Sub-stoichiometric SiO.sub.x at the SiSiO.sub.2 interface is known to exhibit inferior insulating properties relative to stoichiometric SiO.sub.2. Reducing the amount of sub-stoichiometric SiO.sub.x, at the interface may more effectively confine free carriers (electrons or holes) in the silicon, and thus improve the mobility of these carriers due to electric fields applied parallel to the interface, as is standard practice in field-effect-transistor (FET) structures. Scattering due to the direct influence of the interface is called surface-roughness scattering, which may advantageously be reduced by the proximity of MST layers followed by anneals or during thermal oxidation.

[0026] In addition to the enhanced mobility characteristics of MST structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

[0027] Referring now to FIGS. 1 and 2, the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 1.

[0028] Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and a non-semiconductor monolayer(s) 50 thereon. The non-semiconductor monolayers 50 are indicated by stippling in FIG. 1 for clarity of illustration.

[0029] The non-semiconductor monolayer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By constrained within a crystal lattice of adjacent base semiconductor portions it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, as seen in FIG. 2. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a-46n through atomic layer deposition techniques so that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers 46 of semiconductor material are deposited on or over a non-semiconductor monolayer 50, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0030] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

[0031] Applicant theorizes without wishing to be bound thereto that non-semiconductor monolayers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

[0032] Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

[0033] It is also theorized that semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present embodiments, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

[0034] The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.

[0035] Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

[0036] Each non-semiconductor monolayer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

[0037] It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the non-semiconductor monolayer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of FIG. 2, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

[0038] In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

[0039] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the embodiments may be readily adopted and implemented, as will be appreciated by those skilled in the art.

[0040] Referring now additionally to FIG. 3, another embodiment of a superlattice 25 in accordance with the embodiments having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a has three monolayers, and the second lowest base semiconductor portion 46b has five monolayers. This pattern repeats throughout the superlattice 25. The non-semiconductor monolayers 50 may each include a single monolayer. For such a superlattice 25 including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of FIG. 3 not specifically mentioned are similar to those discussed above with reference to FIG. 1 and need no further discussion herein.

[0041] In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

[0042] Turning now to FIG. 4, a semiconductor device 30 which incorporates the above-described MST structures as a gettering layer for metal induced crystallization (MIC) processing is now described. By way of background, various approaches have been used for 3D NAND memory devices and fabrication. For example, in Y. Aiba, et al., Demonstration of recovery annealing on 7-bits per cell 3D flash memory at cryogenic operation for bit cost scalability and sustainability, T3-3, VLSI Symposium 2023, a significant improvement in 3D NAND device performance was reported for an epitaxial (epi) Si channel over conventional poly-Si channel, where amorphous silicon (a-Si) is converted to crystalline Si using the MIC technique. In another example (Z. Jin, et al., Nickel induced crystallization of amorphous silicon thin films, p.194, J. Appl. Phys. 1998), it was reported that 5-10 nm of a Ni layer deposited on 1 m a-Si can convert the a-Si layer into crystalline Si in a subsequent anneal at 500 C. for 1 hr., while Ni diffuses through the a-Si layer.

[0043] While such techniques provide enhanced channel performance, because an MIC-based 3D-NAND epi Si channel relies on rapid diffusion of Ni atoms, diffused Ni needs to be contained or removed so that it does not diffuse into other transistor regions on the Si substrate. Otherwise, this could lead to undesirable crystalline defects, resulting in significant yield reduction.

[0044] The semiconductor device 30 illustratively includes a semiconductor substrate 31 and a memory device 32 on the semiconductor substrate including an MIC channel 32 adjacent the semiconductor substrate, and a gate 34 associated with the MIC channel. In the present example, the memory device 32 is a 3D vertical NAND memory device, although in other embodiments different types of memory devices may be used (e.g., 3D horizontal channel NAND, 3D NOR memory devices, etc.). The semiconductor device 30 further illustratively includes a superlattice gettering layer 25, such as the MST layers described above, between the semiconductor substrate 31 and the MIC channel 33. The superlattice gettering layer 25 advantageously getters metal particles (Ni in the example illustrated in FIG. 4) from the MIC channel resulting from the rapid diffusion of metal (e.g., Ni) during MIC processing.

[0045] Referring additionally to FIGS. 5A-5J, an example method for making the semiconductor device 30 of FIG. 4 is now described. The method begins with forming an MST layer 25 on the silicon substrate 31 (FIG. 5A), as discussed further above. By way of example, the MST layer 25 may have a thickness in a range of 5-500 nm, for example. An implant layer 35 is then formed through the implantation of a dopant. In the present example, this is an N+ layer implant 35 (P 10 keV 310.sup.15, for example) accompanied by a rapid thermal anneal (RTA) (e.g., 1000 C. for 5s).

[0046] Following the implant layer 35 formation, a stack of alternating oxide and nitride films 36, 37 is formed (FIG. 5C). In the illustrated example, the are four oxide layers 36 and three nitride layers 37 in the stack, although different numbers of layers may be used in different embodiments. Next, a trench 38 is etched in the film stack (FIG. 5D), followed by a partial recess of the nitride layers (FIG. 5E).

[0047] A metal gate electrode 60 deposition (e.g., tungsten (W)) may then be performed adjacent the nitride and etched back, as seen in FIG. 5F. A dielectric film 61 may then be formed in the trench 38 and etched back (FIG. 5G). By way of example, the dielectric film 61 may be an oxide-nitride-oxide (ONO) film, although other suitable dielectrics may be used in different embodiments. Next, a silicon channel 62, which is amorphous, may then be formed in the trench 38 on the liner 61, as seen in FIG. 5H.

[0048] The MIC processing begins with the formation of a metal (here, Ni) layer 63 on the stack (FIG. 5I). By way of example, the metal layer 63 may have a thickness in a range of 5-10 nm, although different thicknesses may be used in different embodiments. Then an MIC anneal may be performed, which causes Ni diffusion through the a-Si of the channel 62 so that it crystalizes (FIG. 5J). As seen in FIG. 4, Ni from the MIC anneal which would otherwise diffuse into the substrate 31 (or other regions) is instead gettered or trapped by the MST layer 25, which resides inside of the diffusion layer 35. The surface Ni/NiSi layer 63 may then be removed, and further device processing performed as appropriate (e.g., contact formation, etc.), as will be appreciated by those skilled in the art.

[0049] The effectiveness of the above-described configuration was confirmed by the SIMS profiles shown in the graph 65 of FIG. 6. After depositing 0.9 um of a-Si by LPCVD at 550 C., 10 nm of Ni film was deposited by evaporation. After a subsequent 500 C. 1 hr anneal emulating an MIC anneal, the Ni depth profile was measured. From the graph 65 it is evident that the Si substrate with the MST film contains the Ni diffused from the top surface at the a-Si/crystalline Si interface, as compared to the version with no MST gettering layer.

[0050] Another technical advantage of the above-described approach is that by implementing the MST layer 25 on starting wafers (e.g., as a blanked deposition across the wafer surface), periphery circuits in other regions will gain MST benefits. These benefits may include Vt variability improvement, mobility improvement, gate leakage reduction, and gate oxide reliability improvement, for example. Further details regarding the gettering capabilities of MST films is provided in U.S. Pat. No. 10,410,880 to Takeuchi, which is also assigned to the present Applicant and is hereby incorporated herein in its entirety by reference.

[0051] Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the present disclosure is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included.