STRUCTURE FOR A FRONT-FACING IMAGE SENSOR

Abstract

A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

Claims

1. A structure for a front-side image sensor, comprising: a semiconductor substrate comprising a trapping layer, the trapping layer including cavities therein; an electrically insulating layer overlying the semiconductor substrate; an active layer overlying the electrically insulating layer; and a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer, the plurality of electrically isolating trenches defining a plurality of pixels.

2. The structure of claim 1, wherein the trapping layer is buried within the semiconductor substrate.

3. The structure of claim 1, wherein the trapping layer is in direct contact with the electrically insulating layer.

4. The structure of claim 1, wherein a density of the cavities within the trapping layer is higher than or equal to 10.sup.15 cavities/cm.sup.3.

5. The structure of claim 1, wherein the semiconductor substrate comprises monocrystalline silicon.

6. The structure of claim 1, wherein the active layer comprises a doped-semiconductor material.

7. The structure of claim 1, wherein the active layer comprises: a first semiconductive layer; and a second semiconductive layer overlying the first semiconductive layer, the second semiconductive layer exhibiting substantially similar lattice parameters and coefficients of thermal expansion to the first semiconductive layer.

8. The structure of claim 1, wherein a thickness of the electrically insulating layer is between 5 nm and 400 nm.

9. The structure of claim 1, wherein a thickness of the electrically insulating layer is between 30 nm and 150 nm.

10. The structure of claim 1, wherein the electrically insulating layer comprises silicon oxide.

11. A structure, comprising: a carrier substrate; an electrically insulating layer overlying the carrier substrate and a trapping layer, the trapping layer comprising cavities therein; a semiconductive layer overlying the electrically insulating layer; and a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

12. The structure of claim 11, wherein the electrically insulating layer consists of silicon oxide.

13. The structure of claim 11, wherein the electrically insulating layer comprises a stack of dielectric and/or metal materials.

14. The structure of claim 11, wherein the electrically insulating layer comprises an upper silicon oxide layer, a lower silicon oxide layer, and a silicon nitride layer positioned between the upper silicon oxide layer and the lower silicon oxide layer.

15. The structure of claim 14, wherein: a thickness of the upper silicon oxide layer is between 5 nm and 50 nm, a thickness of the silicon nitride layer is between 10 nm and 100 nm, and a thickness of the lower silicon oxide layer is between 50 nm and 500 nm.

16. The structure of claim 11, wherein the electrically insulating layer comprises a first dielectric layer, a second dielectric layer, and a metal layer positioned between the first dielectric layer and the second dielectric layer.

17. The structure of claim 11, wherein: the semiconductive layer defines an active layer of an image sensor, and the plurality of electrically isolating trenches defines a plurality of pixels.

18. The substrate of claim 1, wherein the semiconductive layer comprises a doped-semiconductor material.

19. The substrate of claim 1, wherein the semiconductive layer comprises a silicon layer.

20. The substrate of claim 1, wherein the carrier substrate comprises a semiconductor material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features and advantages of the present disclosure will emerge from the detailed description that follows, with reference to the accompanying drawings in which:

[0038] FIG. 1A is a sectional view of an SOI substrate for an image sensor according to one embodiment of the present disclosure;

[0039] FIG. 1B is a sectional view of a substrate according to one variant of FIG. 1A;

[0040] FIG. 2 schematically illustrates the implantation of atomic species into a donor substrate in order to form a weakened zone there delimiting a semiconductor layer to be transferred;

[0041] FIG. 3 schematically illustrates the bonding of the weakened donor substrate of FIG. 2 to a carrier substrate;

[0042] FIG. 4 schematically illustrates the transfer of the semiconductor layer to the carrier substrate in order to form an SOI structure;

[0043] FIG. 5 schematically illustrates the implantation of helium into the SOI structure of FIG. 4;

[0044] FIG. 6 illustrates the substrate obtained after forming electrically isolating trenches in the substrate of FIG. 1 in order to singulate each pixel of the image sensor, the substrate having undergone a re-epitaxy step beforehand;

[0045] FIG. 7 shows images of a section of the substrate of FIG. 5 produced by transmission electron microscopy (the right-hand image being an enlargement of the left-hand image);

[0046] FIG. 8 is an image produced by transmission electron microscopy of a section of the substrate of FIG. 5 after an additional heat treatment has been applied to the substrate with respect to the images of FIG. 7;

[0047] FIG. 9 shows a measurement, taken by secondary-ion mass spectrometry (SIMS), of copper concentration illustrating the diffusion thereof within the substrate of FIG. 5, superposed over an image of a section of the substrate produced by transmission electron microscopy;

[0048] FIG. 10 shows a SIMS measurement of copper concentration illustrating the diffusion thereof within a substrate like that of FIG. 5 but without a trapping layer;

[0049] FIG. 11 shows a SIMS measurement of copper concentration illustrating the diffusion thereof within the substrate of FIG. 5.

[0050] To make the drawings clearer, the various layers have not been drawn to scale. Reference signs that are identical from one figure to the next have been used to reference elements that are identical or that perform the same function.

DETAILED DESCRIPTION

[0051] FIG. 1A illustrates an SOI substrate for an image sensor according to one embodiment of the present disclosure.

[0052] The substrate successively comprises, from its back face to its front face, a carrier substrate 1, an electrically insulating layer 2 and a semiconductor layer 3, referred to as the active layer, which is intended for the formation of the pixels of the image sensor.

[0053] A trapping layer 4 for trapping metal atoms is arranged at a certain depth in the carrier substrate 1, not necessarily in contact with the electrically insulating layer 2. As will be described in detail below, the trapping layer 4 comprises cavities that develop from gaseous ions implanted into the carrier substrate under the effect of a heat treatment. The density of cavities in the trapping layer 4 is advantageously higher than or equal to 10.sup.15 cavities/cm.sup.3. The cavities make it possible to capture metal atoms that are present in the SOI substrate in the vicinity of the electrically insulating layer 2, which may negatively affect the correct operation of the sensor. These atoms may be initially present in the carrier substrate 1 and/or in the active layer 3 and diffuse through the SOI substrate under the effect of heat treatments until reaching the trapping layer 4, where they are captured.

[0054] The carrier substrate is advantageously a silicon, in particular, monocrystalline silicon, substrate.

[0055] The electrically insulating layer 2 may be a layer of silicon oxide, which is a conventional insulator in the field of silicon-on-insulator substrates.

[0056] Alternatively, the electrically insulating layer may consist of a stack of various dielectric and/or metal materials, such as what is known as an ONO, i.e., oxide-nitride-oxide, stack. The constituent materials of the stack are advantageously chosen so as to increase the reflectivity of the electrically insulating layer in the infrared in comparison with a layer of silicon oxide of the same total thickness. Preferably, a metal layer is encapsulated between two dielectric layers, which thus prevents any metal contamination of the active layer. This makes it possible to avoid the generation of electrical defects at the interface between the active layer and the electrically insulating layer and recombinations between the semiconductor material of the active layer and the metal components of the image sensor, which could dope the active layer.

[0057] According to one particular embodiment illustrated in FIG. 1B, the electrically insulating layer 2 comprises a layer 22 of silicon nitride between two layers 21, 23 of silicon oxide. The thickness of the layer 21, which is arranged on the carrier substrate 1 side, is between 50 nm and 500 nm, the thickness of the layer 23, which is arranged on the active layer 3 side, is between 5 nm and 50 nm and the thickness of the layer 22 is between 10 nm and 100 nm. Such an electrically insulating layer has the advantage of reflecting the photons transmitted through the active layer 3 better than a layer of silicon oxide of the same thickness of the substrate of FIG. 1A.

[0058] Particularly advantageously, whether it consists of one or of several materials, the electrically insulating layer 2 is thin, i.e., it is between 5 nm and 400 nm, and, preferably, between 30 nm and 150 nm, thick. Such a layer forms no barrier to the diffusion of metal, in particular, copper, atoms. It is therefore not necessary, as in document US 2010/0090303, to damage the electrically insulating layer locally in order to allow atoms to pass through.

[0059] The active layer is advantageously monocrystalline. As schematically shown in FIG. 1, the active layer 3 is formed by stacking a first semiconductor layer 3a and an additional semiconductor layer 3b, the layer 3b being fabricated by epitaxy on top of the layer 3a, which then serves as a seed layer. The materials of the layers 3a and 3b advantageously exhibit similar lattice parameters and coefficients of thermal expansion that make it possible to minimize the formation of crystal defects within the layer 3b as it is epitaxially grown. According to one preferred embodiment, the layers 3a and 3b consist of the same material, typically silicon or silicon-germanium. The layers 3a and/or 3b may potentially be doped.

[0060] The thickness of the active layer 3 is typically greater than or equal to 1 m.

[0061] A process for fabricating the substrate of FIG. 1A based on the SMART CUT method will now be described with reference to FIGS. 2 to 5.

[0062] With reference to FIG. 2, a donor substrate 30 covered with the electrically insulating layer 2 is provided. The electrically insulating layer may be formed by thermally oxidizing the material of the donor substrate and/or by depositing one or more dielectric and/or metal layers. A weakened zone, which delimits the semiconductor layer 3a to be transferred, is formed by implanting atomic species (represented by arrows) into the donor substrate 30. The atomic species implanted for this purpose advantageously comprise hydrogen and/or helium.

[0063] With reference to FIG. 3, the donor substrate 30 is bonded to the carrier substrate 1, the electrically insulating layer 2 being at the bonding interface.

[0064] With reference to FIG. 4, the donor substrate 30 is detached along the weakened zone 31 in order to transfer the semiconductor layer 3a to the carrier substrate 1.

[0065] With reference to FIG. 5, gaseous (for example, helium) ions are implanted into the carrier substrate 1 through the semiconductor layer 3a and the electrically insulating layer 2. A person skilled in the art is capable of defining the implantation parameters, in particular, the dose and implantation energy, so as to localize the gaseous ions 40 in a layer in the thickness of the carrier substrate 1. By way of indication, a dose of between 1E16 atoms/cm2 and 5E17 atoms/cm2 is suitable for obtaining a density of cavities of at least 10E15 cavities/cm.sup.3. The implantation energy is typically between a few keV and 120 keV. A person skilled in the art will choose a suitable energy according to the thicknesses of the layers through which the ions have to pass for the ions to be localized in the carrier substrate below the electrically insulating layer.

[0066] A heat treatment is next carried out to develop cavities from the implanted gaseous ions in order to form a layer for trapping metal atoms. Generally speaking, this treatment involves heating the substrate to a temperature of between 850 C. and 1200 C. for a duration of between 30 minutes and 180 minutes. This heat treatment may be carried out as a specific step in the process. However, it may be advantageous to use the thermal budget of another step in the process, for example, a step of finishing the SOI substrate (such as an anneal for smoothing or for healing defects) or the epitaxy step carried out in order to grow the additional semiconductor layer 3b on top of the transferred semiconductor layer 3a.

[0067] As an alternative to the SMART CUT process described above, the semiconductor layer may be transferred, after bonding the donor substrate to the carrier substrate, by thinning the donor substrate from its face opposite the bonding interface, for example, by etching, until the desired thickness for the transferred semiconductor layer is obtained. The formation of the weakened zone is not necessary in this case.

[0068] Forming the trapping layer after bonding the donor substrate to the carrier substrate, rather than before as described in document US 2010/0090303, makes it possible to ensure that the surfaces to be bonded are of optimum quality and consequently that the adhesion between the two substrates is good, even if the electrically insulating layer is thin. Additionally, implanting the gaseous ions before the epitaxy of the additional semiconductor layer makes it possible to minimize the implantation energy and to avoid damaging the active layer.

[0069] With reference to FIG. 6, the additional semiconductor layer 3b is grown by epitaxy on top of the transferred semiconductor layer 3a until the desired thickness for the active layer 3 is obtained. As mentioned above, the thermal budget of this epitaxy may be used to develop the cavities that form the trapping layer 4. Next, trenches are formed through the active layer 3 down into the electrically insulating layer 2, and the trenches 5 are filled with a dielectric material in order to electrically isolate the pixels of the image sensor.

Experimental Results

[0070] SOI substrates such as illustrated in FIG. 5 have been produced and the trapping layer has been formed by developing cavities from the implanted gaseous ions by heating some of the SOI substrates to a temperature of 950 C. for 40 minutes (see FIG. 7).

[0071] The substrates then underwent heat treatments that SOI substrates, including the layer for trapping metal atoms, may undergo in order to check that the trapping layer is stable and remains operational even after having undergone a heat treatment with a high thermal budget (see FIG. 8). It is assumed that the thermal budget of a treatment at 1100 C. for two hours is the maximum thermal budget that allows the trapping properties of the cavity layer to be conserved. This thermal budget is compatible with finishing steps and potentially epitaxy.

[0072] FIG. 7 shows images of a section of the substrate of FIG. 5 produced by transmission electron microscopy (the right-hand image being an enlargement of the left-hand image) after a heat treatment for developing the cavities has been carried out. Within the carrier substrate 1 it is possible to see the cavities arranged in a trapping layer 4 forming a layer for trapping metal atoms. In the example illustrated, the thickness of the trapping layer 4 is 179 nm and it is buried at a depth of 205 nm below the interface between the carrier substrate 1 and the electrically insulating layer 2.

[0073] FIG. 8 is an image produced by transmission electron microscopy of a section of the substrate of FIG. 5 after an additional heat treatment has been applied to the substrate with respect to the images of FIG. 7, the heat treatment being carried out at a temperature of up to 1100 C. for a duration of less than or equal to two hours. In the thickness of the carrier substrate 1, at the implantation depth of the gaseous ions, it is possible to see cavities arranged in the trapping layer 4, which forms a layer for trapping metal atoms.

[0074] FIG. 9 shows a measurement, taken by secondary-ion mass spectrometry (SIMS), of copper concentration in the substrate of FIG. 5, superposed over an image of a section of the substrate produced by transmission electron microscopy. To carry out this measurement, a layer of copper was deposited on top of the semiconductor layer 3a and a heat treatment (800 C. for two hours) was carried out to diffuse the copper atoms into the substrate. This heat treatment was chosen for demonstration purposes to ensure, taking into account the physical diffusion properties of copper in silicon and silicon oxide, complete dispersion of this element into the material. This measurement thus reflects the ability of copper atoms to pass through the electrically insulating layer 2 and be trapped by the trapping layer 4. Thus, while the concentration of copper atoms in the semiconductor layer 3a is about 1.1E11 atoms/cm.sup.3 and about 1.8E9 atoms/cm.sup.3 in the electrically insulating layer, the curve shows a peak at the trapping layer 4 with a concentration of copper atoms of about 2.3E13 atoms/cm.sup.3. The concentration of copper atoms below the trapping layer 4 is very low.

[0075] FIGS. 10 and 11 show a SIMS measurement of copper concentration within a substrate like that of FIG. 5 without and with the trapping layer 4, respectively. To carry out this measurement, a layer of copper was deposited on the back face of the carrier substrate 1 and a heat treatment (800 C. for two hours) was carried out to diffuse the copper atoms into the substrate. In the case of FIG. 10 (no trapping layer), a high concentration of copper atoms is observed in the carrier substrate 1 below the electrically insulating layer (peak P1) and a high concentration of copper atoms is observed in the transferred layer in the vicinity of the free surface of the layer (peak P2). In the case of FIG. 11 (a trapping layer according to the present disclosure being present), it is observed that the copper-atom concentration peak P3 is localized in the trapping layer.

REFERENCES

[0076] U.S. Pat. No. 6,083,324 [0077] US 2010/0090303