NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE

Abstract

The present invention is a nitride semiconductor substrate for high frequency, which includes an SOI substrate in which a single crystal silicon thin film is formed on a single crystal silicon substrate via a silicon oxide layer, and a nitride semiconductor layer including a GaN layer formed on the SOI substrate; in which the single crystal silicon thin film contains nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and has a resistivity of 100 cm or more, the single crystal silicon substrate has a resistivity of 50 mcm or less, and the silicon oxide layer has a thickness of 10 to 400 nm. This can provide the nitride semiconductor substrate in which the nitride semiconductor layer is grown on the SOI substrate for manufacturing devices for high frequency, and the nitride semiconductor substrate with suppressed plastic deformation.

Claims

1. A nitride semiconductor substrate for high frequency comprising: an SOI substrate in which a single crystal silicon thin film is formed on a single crystal silicon substrate via a silicon oxide layer; and a nitride semiconductor layer including a GaN layer formed on the SOI substrate, wherein the single crystal silicon thin film contains nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and has a resistivity of 100 cm or more, the single crystal silicon substrate has a resistivity of 50 mcm or less, and the silicon oxide layer has a thickness of 10 to 400 nm.

2. The nitride semiconductor substrate according to claim 1, wherein the silicon oxide layer has a thickness of 10 to 200 nm.

3. A method for manufacturing a nitride semiconductor substrate for high frequency, the method comprising the steps of: providing two single crystal silicon substrates serving as a bond wafer and a base wafer; bonding the two single crystal silicon substrates to each other via a silicon oxide layer; thinning the bond wafer into a single crystal silicon thin film to obtain an SOI substrate, in which the single crystal silicon thin film is formed via the silicon oxide layer on the base wafer; and growing a nitride semiconductor layer including a GaN layer on the single crystal silicon thin film of the SOI substrate to obtain a nitride semiconductor substrate having the nitride semiconductor layer formed on the SOI layer, wherein a substrate containing nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and having a resistivity of 100 cm or more is used as the single crystal silicon substrate serving as the bond wafer, a substrate having a resistivity of 50 mcm or less is used as the single crystal silicon substrate serving as the base wafer, and a layer having a thickness of 10 to 400 nm is used as the silicon oxide layer.

4. The method for manufacturing a nitride semiconductor substrate according to claim 3, wherein a layer having a thickness of 10 to 200 nm is used as the silicon oxide layer.

5. The method for manufacturing a nitride semiconductor substrate according to claim 3, wherein the single crystal silicon substrate serving as the bond wafer is manufactured by an FZ method or an MCZ method and provided.

6. The method for manufacturing a nitride semiconductor substrate according to claim 4, wherein the single crystal silicon substrate serving as the bond wafer is manufactured by an FZ method or an MCZ method and provided.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a schematic cross-sectional view illustrating an example of a nitride semiconductor substrate according to the present invention.

[0042] FIG. 2 is a schematic view of a configuration of an example of a nitride semiconductor substrate according to the present invention.

[0043] FIG. 3 is a graph illustrating the change of warp state during epitaxial growth in Examples and Comparative Examples.

[0044] FIG. 4 is a graph illustrating relations between thicknesses and warps of the silicon oxide layers in Examples and Comparative Examples.

DESCRIPTION OF EMBODIMENTS

[0045] As described above, when a nitride semiconductor is epitaxially grown on an SOI substrate having a single crystal silicon thin film with a high resistivity to manufacture a device for high frequency, plastic deformation may have occurred during epitaxial growth.

[0046] The present inventors have earnestly studied the nitride semiconductor substrate with suppressed plastic deformation and a manufacturing method thereof and found out that the nitride semiconductor substrate with suppressed plastic deformation can be manufactured by having the single crystal silicon thin film of the SOI substrate containing nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more, the single crystal silicon thin film having a resistivity of 100 cm or more, the single crystal silicon substrate having a resistivity of 50 mcm or less, and the silicon oxide layer of the SOI substrate having a thickness of 10 to 400 nm. This finding led to the completion of the present invention.

[0047] In other words, the present invention is a nitride semiconductor substrate for high frequency comprising: [0048] an SOI substrate in which a single crystal silicon thin film is formed on a single crystal silicon substrate via a silicon oxide layer; and [0049] a nitride semiconductor layer including a GaN layer formed on the SOI substrate, [0050] wherein the single crystal silicon thin film contains nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and has a resistivity of 100 cm or more, [0051] the single crystal silicon substrate has a resistivity of 50 mcm or less, and [0052] the silicon oxide layer has a thickness of 10 to 400 nm.

[0053] In addition, the present invention is a method for manufacturing a nitride semiconductor substrate for high frequency, the method comprising the steps of: [0054] providing two single crystal silicon substrates serving as a bond wafer and a base wafer; [0055] bonding the two single crystal silicon substrates to each other via a silicon oxide layer; [0056] thinning the bond wafer into a single crystal silicon thin film to obtain an SOI substrate, in which the single crystal silicon thin film is formed via the silicon oxide layer on the base wafer; and [0057] growing a nitride semiconductor layer including a GaN layer on the single crystal silicon thin film of the SOI substrate to obtain a nitride semiconductor substrate having the nitride semiconductor layer formed on the SOI layer, [0058] wherein a substrate containing nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and having a resistivity of 100 cm or more is used as the single crystal silicon substrate serving as the bond wafer, [0059] a substrate having a resistivity of 50 mcm or less is used as the single crystal silicon substrate serving as the base wafer, and [0060] a layer having a thickness of 10 to 400 nm is used as the silicon oxide layer.

[0061] Hereinafter, the present invention will be described in detail with reference to the drawings. However, the present invention is not limited thereto.

[Nitride Semiconductor Substrate]

[0062] FIG. 1 shows a schematic cross-sectional view of an example of a nitride semiconductor substrate according to the present invention. FIG. 2 shows a schematic view of a configuration of an example of the nitride semiconductor substrate according to the present invention.

[0063] A nitride semiconductor substrate 1 shown in FIG. 1 includes an SOI substrate 2 and a nitride semiconductor layer (nitride semiconductor thin film) 3.

[0064] In the SOI substrate 2, a single crystal silicon thin film 23 is formed on a single crystal silicon substrate 21 via a silicon oxide layer 22.

[0065] The nitride semiconductor layer 3 includes a GaN layer 34 shown in FIG. 2. The nitride semiconductor layer 3 shown in FIG. 2 includes an AlN layer 31, an AlGaN layer 32, and superlattice layers (SLs) 33 in addition to the GaN layer 34; however, the nitride semiconductor layer 3 is not limited to a configuration like the one shown in FIG. 2 as long as the GaN layer 34 is included.

[0066] The single crystal silicon thin film 23 of the SOI substrate 2 of the nitride semiconductor substrate 1 contains nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and has a resistivity of 100 cm or more. Moreover, the single crystal silicon substrate 21 has a resistivity of 50 mcm or less. Furthermore, the silicon oxide layer 22 has a thickness of 10 to 400 nm.

[0067] Such an SOI substrate 2 can exhibit high strength even when the SOI substrate 2 has the SOI layer 23 with a high resistivity. The inventive nitride semiconductor substrate 1 can be the substrate with suppressed plastic deformation by virtue of including such an SOI substrate 2.

[0068] On the other hand, when the nitrogen concentration in the single crystal silicon thin film 23 is less than 2.010.sup.14 atoms/cm.sup.3, plastic deformation cannot be sufficiently suppressed. The upper limit of the nitrogen concentration in the single crystal silicon thin film 23 is not particularly limited but can be 1.010.sup.20 atoms/cm.sup.3, for example.

[0069] Moreover, when the thickness of the silicon oxide layer 22 exceeds 400 nm, plastic deformation cannot be sufficiently suppressed. On the contrary, when the thickness of the silicon oxide layer 22 is less than 10 nm, bonding is not performed well, and a void is generated. When the thickness of the silicon oxide layer 22 is 10 to 400 nm, the nitride semiconductor substrate 1 can be made with even more suppressed plastic deformation.

[0070] Also, when the resistivity of the single crystal silicon substrate 21 exceeds 50 mcm, plastic deformation cannot be sufficiently suppressed. The lower limit of the resistivity of the single crystal silicon substrate 21 is not particularly limited but can be 2 mcm, for example.

[0071] Moreover, by virtue of the resistivity of the single crystal silicon thin film 23 being 100 cm or more, the device for high frequency having excellent high frequency characteristics can be manufactured. The upper limit of the resistivity of the single crystal silicon thin film 23 is not particularly limited but can be 30000 cm, for example.

[Method for Manufacturing Nitride Semiconductor Substrate]

[0072] An inventive method for manufacturing a nitride semiconductor substrate includes the steps of: [0073] providing two single crystal silicon substrates serving as a bond wafer and a base wafer; [0074] bonding the two single crystal silicon substrates to each other via a silicon oxide layer; [0075] thinning the bond wafer into a single crystal silicon thin film to obtain an SOI substrate, in which the single crystal silicon thin film is formed via the silicon oxide layer on the base wafer; and [0076] growing a nitride semiconductor layer including a GaN layer on the single crystal silicon thin film of the SOI substrate to obtain a nitride semiconductor substrate having the nitride semiconductor layer formed on the SOI layer.

[0077] In the step of providing two single crystal silicon substrates, as the single crystal silicon substrate serving as the bond wafer, the substrate containing nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and having a resistivity of 100 cm or more is provided. The upper limit of the nitrogen concentration of the single crystal silicon substrate serving as the bond wafer is not particularly limited but can be 1.010.sup.20 atoms/cm.sup.3, for example. Moreover, the upper limit of the resistivity of the single crystal silicon substrate serving as the bond wafer is not particularly limited but can be 30000 cm, for example.

[0078] The single crystal silicon substrate serving as the bond wafer is preferably the single crystal silicon substrate manufactured by an FZ method or an MCZ method and having a plane orientation of (111). The nitrogen concentration of 2.010.sup.14 atoms/cm.sup.3 or more can be achieved by, for example, doping nitrogen in the production process of the single crystal silicon according to the FZ method or the MCZ method.

[0079] Moreover, as the single crystal silicon substrate serving as the base wafer, the substrate having a resistivity of 50 mcm or less is provided. The lower limit of the resistivity of the single crystal silicon substrate serving as the base wafer is not particularly limited but can be 2 mcm, for example.

[0080] The single crystal silicon substrate serving as the base wafer is preferably the single crystal silicon substrate manufactured by the CZ method and having a plane orientation of (100).

[0081] Furthermore, the single crystal silicon substrate serving as the bond wafer is, for example, thermally oxidized to form the silicon oxide layer having a thickness of 10 to 400 nm on the surface. It is preferred that the silicon oxide layer having a thickness of 10 to 200 nm is formed.

[0082] Then, the single crystal silicon substrate serving as the bond wafer is laminated to and brought together with the single crystal silicon substrate serving as the base wafer via the silicon oxide layer having a thickness of 10 to 400 nm, and then performed bonding heat treatment at, for example, 1150 C. for about 2 hours to bond them each other.

[0083] Then, the bond wafer is processed to make a thickness of, for example, about 100 to 200 nm to obtain the single crystal silicon thin film. This processing method is not particularly limited, but the method of delamination by hydrogen ion implantation followed by polishing is easier and thus preferred.

[0084] By this process, as shown in, for example, FIG. 1, an SOI substrate 2 in which a single crystal silicon thin film 23 is formed on a base wafer (single crystal silicon substrate) 21 via the silicon oxide layer 22 can be obtained.

[0085] By using the SOI substrate 2 thus provided as a starting substrate, the nitride semiconductor layer including the GaN layer is grown on the SOI substrate 2. For example, as shown in FIG. 2, first, an AlN layer 31 is formed with a thickness of, for example, 150 nm, and then an AlGaN layer 32 is formed with a thickness of, for example, 160 nm. Next, superlattice layers (SLs) 33 are formed by laminating alternately with 40 to 60 pairs of the GaN layers and the AlN layers. Then, a GaN layer 34 having a thickness of, for example, 800 to 1200 nm is formed. Then, a barrier layer made of the AlGaN layer 32 having a thickness of, for example, 3 nm is formed, and a cap layer made of the GaN layer 34 having a thickness of, for example, 3 nm is formed further on top of the barrier layer, thereby manufacturing a nitride semiconductor substrate 1 (GaN-HEMT epitaxial growth substrate) 1 in which a nitride semiconductor layer 3 is formed on the SOI substrate 2, as shown in FIG. 2.

[0086] According to such an inventive method for manufacturing the nitride semiconductor substrate, the inventive nitride semiconductor substrate can be manufactured. However, the method for manufacturing the inventive nitride semiconductor substrate is not limited to the manufacturing method described above.

[0087] Thus, in the inventive method for manufacturing the nitride semiconductor substrate, a nitride semiconductor thin film including the AlN layer 31, the GaN layer 34, and the AlGaN layer 32 is formed on the SOI substrate 2 in which the single crystal silicon thin film is formed on the single crystal silicon substrate serving as the base wafer via the silicon oxide layer. As the single crystal silicon substrate serving as the bond wafer, the substrate that contains nitrogen at a concentration of 2.010.sup.14 atoms/cm.sup.3 or more and has a resistivity of 100 cm or more is used, and as the single crystal silicon substrate serving as the base wafer, the substrate that has a resistivity of 50 mcm or less is used, and as the silicon oxide layer, the layer that has a thickness of 10 to 400 nm, preferably 10 to 200 nm is used. Consequently, the nitride semiconductor substrate can be manufactured with relatively improved strength even with high resistivity, and the nitride semiconductor substrate is particularly applicable to devices for the high frequency with excellent high frequency characteristics and has suppressed plastic deformation.

EXAMPLES

[0088] Hereinafter, the present invention will be specifically described with reference to Examples and Comparative Examples. However, the present invention is not limited thereto.

Example 1

[0089] As shown in FIG. 2, a nitride semiconductor layer 3 having a thickness of 1.8 m was epitaxially grown on an SOI substrate 2 to obtain a nitride semiconductor substrate (GaN-HEMT substrate) 1 of Example 1.

[0090] In this case, an SOI substrate having a diameter of 150 mm and meeting the following condition was used as the SOI substrate 2.

[0091] As a single crystal silicon substrate (Bond Substrate) serving as a bond wafer, the single crystal silicon substrate manufactured by an MCZ method with nitrogen-doping, having a plane orientation of (111), containing nitrogen at a concentration of 510.sup.14 atoms/cm.sup.3, and having a resistivity of 1200 cm was provided.

[0092] As a single crystal silicon substrate (Base Substrate) serving as a base wafer, the single crystal silicon substrate manufactured by a CZ method, having a plane orientation of (100), a resistivity of 8 mcm, and a thickness of 675 m was provided.

[0093] The provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 200 nm on a surface of the bond wafer.

[0094] Then, the bond wafer was implanted with hydrogen ions through an oxide film to form a bubble layer, then was laminated and brought together with the single crystal silicon substrate serving as the base wafer via the silicon oxide layer. Subsequently, heat-treatment was performed to delaminate the bond wafer at the bubble layer, then bonding heat treatment was performed at 1150 C. for 2 hours to bond the substrate to each other.

[0095] Consequently, a single crystal silicon thin film (SOI layer) that contained nitrogen at a concentration of 510.sup.14 atoms/cm.sup.3, and had a resistivity of 1200 cm and a thickness of 100 nm was obtained.

[0096] With this processing, as shown in FIG. 1, the SOI substrate 2, in which a single crystal silicon thin film 23 was formed on the base wafer (single crystal silicon substrate) 21 via the silicon oxide layer (BOX Layer) 22, was obtained.

[0097] In Example 1, the nitride semiconductor layer 3 was formed by epitaxial growth, following a procedure described earlier with referring to FIG. 2, on the SOI substrate 2 obtained as described above.

Comparative Example 1

[0098] A nitride semiconductor substrate of Comparative Example 1 was obtained with the same procedure as in Example 1 except that a substrate was used as a single crystal silicon substrate serving as a bond wafer, the substrate having been manufactured by an FZ method without doping nitrogen and having a plane orientation of (111) and a resistivity of 5535 cm.

Comparative Example 2

[0099] A nitride semiconductor substrate of Comparative Example 2 was obtained with the same procedure as in Comparative Example 1, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 400 nm on a surface of a bond wafer.

Example 2

[0100] A nitride semiconductor substrate of Example 2 was obtained with the same procedure as in Example 1, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 400 nm on a surface of a bond wafer.

Comparative Example 3

[0101] A nitride semiconductor substrate of Comparative Example 3 was obtained with the same procedure as in Comparative Example 1, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 650 nm on a surface of a bond wafer.

Comparative Example 4

[0102] A nitride semiconductor substrate of Comparative Example 4 was obtained with the same procedure as in Example 1, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 650 nm formed on a surface of a bond wafer.

Comparative Example 5

[0103] A nitride semiconductor substrate of Comparative Example 5 was obtained with the same procedure as in Comparative Example 4, except that, as a single crystal silicon substrate serving as a base wafer, the single crystal silicon substrate was used, in which the substrate was manufactured by a CZ method, and had a plane orientation of (100), a resistivity of 8 mcm, a thickness of 675 m, and a back-surface CVD oxide film having a thickness of 600 nm formed on the opposite surface to the surface where a bond wafer was bonded.

Comparative Example 6

[0104] A nitride semiconductor substrate of Comparative Example 6 was obtained with the same procedure as in Comparative Example 4, except that a single crystal silicon thin film had a thickness of 200 nm.

[0105] Table 1 below shows details of SOI substrates, and warps after epitaxial growth of nitride semiconductor layers, for Examples 1 and 2 and Comparative Examples 1 to 6.

TABLE-US-00001 TABLE 1 Single Crystal Silicon Thin Film Silicon Oxide (SOI Layer) Layer Single Crystal Nitrogen (BOX Layer) Silicon Substrate Production Thickness Resistivity Concentration Thickness Resistivity Thickness Warp Method (nm) (cm) (atoms/cm.sup.3) (nm) (mcm) (m) (m) Comparative FZ 100 5535 200 8 675 55 Example 1 Example 1 MCZ 100 1200 5 10.sup.14 200 8 675 16 Comparative FZ 100 5535 400 8 675 60 Example 2 Example 2 MCZ 100 1200 5 10.sup.14 400 8 675 25 Comparative FZ 100 5535 650 8 675 284 Example 3 Comparative MCZ 100 1200 5 10.sup.14 650 8 675 180 Example 4 Comparative MCZ 100 1200 5 10.sup.14 650 8 675 287 Example 5 Comparative MCZ 200 1200 5 10.sup.14 650 8 675 199 Example 6

[0106] As clear from the results shown in Table 1, it is indicated that warps after epitaxial growth of the nitride semiconductor substrates of Examples 1 and 2 are #50 m or less, which is a general standard of a device for production, and the plastic deformation is sufficiently suppressed.

[0107] On the other hand, it is indicated that the nitride semiconductor substrates of Comparative Examples 1 and 2, which did not use the substrates containing nitrogen at a concentration of 510.sup.14 atoms/cm.sup.3 as the single crystal silicon substrate serving as the bond wafer, had the warps after epitaxial growth exceeding 50 m, and thus the plastic deformation was not sufficiently suppressed.

[0108] Furthermore, it is indicated that the nitride semiconductor substrates of Comparative Examples 3 to 6, which used the layers having thicknesses of larger than 400 nm as the silicon oxide layers, had the warps after epitaxial growth exceeding 50 m, and thus the plastic deformation was not sufficiently suppressed.

Example 3

[0109] A nitride semiconductor substrate of Example 3 was obtained with the same procedure as in Example 1, except that the single crystal silicon substrate being manufactured by a CZ method, and having a plane orientation of (100), a resistivity of 8 mcm, and a thickness of 1000 m was used as a single crystal silicon substrate serving as a base wafer.

Example 4

[0110] A nitride semiconductor substrate of Example 4 was obtained with the same procedure as in Example 1, except that the single crystal silicon substrate being manufactured by an FZ method with nitrogen-doping, having a plane orientation of (111), containing nitrogen at a concentration of 510.sup.14 atoms/cm.sup.3, and having a resistivity of 3552 cm was used as a single crystal silicon substrate serving as a bond wafer. That is, in Example 4, as in Example 1, a silicon oxide layer having a thickness of 200 nm was used.

Example 5

[0111] A nitride semiconductor substrate of Example 5 was obtained with the same procedure as in Example 4, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 400 nm on a surface of a bond wafer.

Comparative Example 7

[0112] A nitride semiconductor substrate of Comparative Example 7 was obtained with the same procedure as in Example 4, except that a provided bond wafer was thermally oxidized to form a silicon oxide layer having a thickness of 650 nm on a surface of a bond wafer.

[0113] Table 2 below shows the details of the SOI substrates, and the warps after epitaxial growth of the nitride semiconductor layers for Examples 3 to 5 and Comparative Example 7.

TABLE-US-00002 TABLE 2 Single Crystal Silicon Thin Film Silicon Oxide (SOI Layer) Layer Single Crystal Nitrogen (BOX Layer) Silicon Substrate Production Thickness Resistivity Concentration Thickness Resistivity Thickness Warp Method (nm) (cm) (atoms/cm.sup.3) (nm) (mcm) (m) (m) Example 3 MCZ 100 1200 5 10.sup.14 200 8 1000 8 Example 4 FZ 100 3552 5 10.sup.14 200 8 675 18 Example 5 FZ 100 3552 5 10.sup.14 400 8 675 40 Comparative FZ 100 3552 5 10.sup.14 650 8 675 270 Example 7

[0114] FIG. 3 shows a part of log data obtained from warp states during epitaxial growth as curvature in Examples 1 and 3, as well as in Comparative Examples 3 and 6.

[0115] As shown in FIG. 3, Comparative Example 3 and Comparative Example 6 in which the silicon oxide layers have a thickness of 650 nm, show large plastic deformation at about 2 hours and 40 minutes.

[0116] On the other hand, it is indicated in FIG. 3 that the warps of the substrates during epitaxial growth in Examples 1 and 3 were suppressed compared to those in Comparative Examples 3 and 6.

[0117] In addition, FIG. 4 shows a relation between the thicknesses and the warps of the silicon oxide layers in Examples and Comparative Examples.

[0118] Specifically, square plots and dotted approximate curves show the change in the warps when the silicon oxide layer (BOX) thicknesses were varied to 200 nm (Example 1), 400 nm (Example 2), and 650 nm (Comparative Example 4), using the bond wafers manufactured by the MCZ method and provided.

[0119] In addition, circular plots and dotted approximate curves show the change in the warps when the silicon oxide layer (BOX) thicknesses were varied to 200 nm (Example 4), 400 nm (Example 5), and 650 nm (Comparative Example 7), using the bond wafers manufactured by the FZ method and provided.

[0120] As can be understood from FIG. 4, regardless of whether the bond wafers were manufactured by the MCZ method or the FZ method, the warps were 50 m or less in Examples where the silicon oxide layer (BOX layers) thicknesses were 400 nm or less, in which the warps were significantly suppressed compared with Comparative Examples with the silicon oxide layers having a thickness of 650 nm.

[0121] It should be noted that the present invention is not limited to the above-described embodiments. The embodiments are just examples, and any examples that have substantially the same features and demonstrate the same functions and effects as those in the technical concept disclosed in claims of the present invention are included in the technical scope of the present invention.