High-electron-mobility transistor device and method of manufacturing the same

Abstract

A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.

Claims

1. A method of manufacturing a high-electron-mobility transistor device, the method comprising: sequentially forming a transition layer and a semiconductor layer on a substrate; etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region; forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer; forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer; and forming a gate electrode on the upward exposed barrier layer.

2. The method of claim 1, wherein the forming of the source electrode and the drain electrode on the 2-DEG layer comprises directly and electrically connecting the 2-DEG layer to the source electrode and the drain electrode.

3. The method of claim 1, wherein the forming of the source electrode and the drain electrode on the 2-DEG layer comprises respectively forming the source electrode and the drain electrode on both end portions of the 2-DEG layer upward exposed at the surface of the semiconductor layer.

4. The method of claim 1, wherein the forming of the source electrode and the drain electrode on the 2-DEG layer comprises: respectively forming a first metal pattern and a second metal pattern on both end portions of the 2-DEG layer upward exposed at the surface of the semiconductor layer; diffusing the formed first and second metal patterns into the semiconductor layer and the barrier layer through a rapid thermal process; and forming the first and second metal patterns, diffused into the semiconductor layer and the barrier layer, as the source electrode and the drain electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:

(2) FIG. 1 is a cross-sectional view for describing a semiconductor device according to an embodiment of the present invention; and

(3) FIGS. 2A to 2L are cross-sectional views for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE DISCLOSURE

(4) Hereinafter, an HEMT device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. Widths and thicknesses of layers or regions illustrated in the accompanying drawings are exaggeratedly illustrated for clarity. In a detailed description, like reference numerals refer to like elements.

(5) Herein, a process of forming a first feature portion on or over a second feature portion may include embodiments where the first and second feature portions are formed to directly contact each other, and moreover, may include embodiments where additional feature portions are formed between the first and second feature portions so that the first and second feature portions do not directly contact each other.

(6) FIG. 1 is a cross-sectional view for describing a semiconductor device according to an embodiment of the present invention.

(7) Referring to FIG. 1, the semiconductor device (hereinafter referred to as an HEMT device) may include a substrate 100, a transition layer 101, a semiconductor layer 102, a barrier layer 103, a drain electrode 202, a source electrode 203, a passivation layer 204, and a gate electrode 205.

(8) The substrate 100 may be, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or a diamond substrate, but is not limited thereto.

(9) The transition layer 101 may be stacked (disposed) on the substrate 100. The transition layer 101 may function as a buffer layer for reducing a lattice constant and a thermal expansion coefficient difference between the substrate 100 and the semiconductor layer 102. In the drawing, the transition layer 101 having a single-layer structure is illustrated, but is not limited thereto and may have a multi-layer structure.

(10) The semiconductor layer 102 may be stacked (disposed) on the transition layer 101. A groove or a region (10 of FIG. 2B) having a certain depth may be formed in a surface of the semiconductor layer 102. The barrier layer 103 may be stacked (disposed) in the groove or the region. The semiconductor layer 102 may have a thickness of tens M or less, and for example, may include one or more of Group III-V compound semiconductors including AlN, InN, GaN, AlGaN, InGaN, AlInN, AlGaInN, and GaAs. A material of the 2-DEG layer capable of being formed in the semiconductor layer 102 is not limited and may be used as a material of the semiconductor layer 102.

(11) When the barrier layer 103 is stacked (disposed) in the groove or the region formed in the surface of the semiconductor layer 102, a 2-DEG layer 102A formed along an interface between the semiconductor layer 102 and the barrier layer 103 may be defined in the semiconductor layer 102. In this case, both end portions of the 2-DEG layer 102A may be formed to have a bent shape so as to be exposed at the surface of the semiconductor layer 102.

(12) The drain electrode 202 and the source electrode 203 may be stacked (disposed) on a junction boundary between the semiconductor layer 102 and the barrier layer 103 so as to be electrically connected to the both end portions of the 2-DEG layer 102A.

(13) The passivation layer 204 may be stacked on the semiconductor layer 102 and the barrier layer 103, which are exposed upward. Also, opening portions which upward expose the drain electrode 202, the source electrode 203, and a portion of the barrier layer 103 between the drain electrode 202 and the source electrode 203 may be formed in the passivation layer 204. A bias voltage may be applied to the drain electrode 202 and the source electrode 203 upward exposed by the opening portions.

(14) The gate electrode 205 may be stacked (disposed) on the barrier layer 103 upward exposed by the opening portion (2k of FIG. 20) formed in the passivation layer 204.

(15) Hereinafter, a method of manufacturing the semiconductor device (or the HEMT device) illustrated in FIG. 1 will be described in detail.

(16) FIGS. 2A to 2L are cross-sectional views for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

(17) First, referring to FIG. 2A, the substrate 100 may be prepared. The transition layer 101 may be formed on the substrate 100 by a known deposition process including an epitaxial growth process. The semiconductor layer 102 may be formed on the transition layer 101 by the known deposition process.

(18) Subsequently, referring to FIG. 2B, a barrier layer region 10 having a certain depth may be formed through an etching process of removing a portion of a surface of the semiconductor layer 102. Herein, the barrier layer region 10 may be referred to as a groove or an etch groove. The etching process may include, for example, a dry etching process, a wet etching process, or a combination thereof. A structure of the barrier layer region 10 may have various shapes.

(19) Subsequently, referring to FIG. 2B, the barrier layer 103 may be formed in the barrier layer region (10 of FIG. 2B) formed in the surface of the semiconductor layer 102. A known deposition process may be used for forming the barrier layer 103.

(20) FIGS. 2D to 2F illustrates another example which forms the barrier layer 103 in the surface of the semiconductor layer 102. First, referring to FIG. 2D, the barrier layer 103 may be formed (stacked) on the whole surface of the semiconductor layer 102 (a first semiconductor layer).

(21) Subsequently, referring to FIG. 2E, an etching process of removing a portion of the barrier layer 103 formed on the surface of the semiconductor layer 102 may be performed. The etching process may include, for example, a dry etching process, a wet etching process, or a combination thereof.

(22) Subsequently, referring to FIG. 2F, a second semiconductor layer 104 may be formed on the surface of the semiconductor layer 102 upward exposed by the etching process of FIG. 2E. In a case where two semiconductor layers 102 and 104 are stacked in this manner, a 2-DEG layer 102A may be formed in a horizontal direction in the first semiconductor layer 102 and may be formed in a vertical direction in the second semiconductor layer 104. Accordingly, both ends A and B of the 2-DEG layer 102A may be exposed in an upward direction at a surface of the second semiconductor layer 104.

(23) The second semiconductor layer 104 may have a thickness of tens M or less, and for example, may include one or more of Group III-V compound semiconductors including AlN, InN, GaN, AlGaN, InGaN, AlInN, AlGaInN, and GaAs, but the present invention is not limited thereto. In another embodiment, a material of the 2-DEG layer capable of being formed in the second semiconductor layer 104 contacting the barrier layer 103 is not limited and may be used as a material of the second semiconductor layer 104. A material of the semiconductor layer 102 (or the first semiconductor layer) may be the same as or different from a material of the second semiconductor layer 104.

(24) Referring to FIGS. 2C, 2F, and 2G, a heterojunction may be formed in an interface between the semiconductor layer 102 and the barrier layer 103, and the 2-DEG layer 102A may be defined in the semiconductor layer 102 by the heterojunction. In an operation, the 2-DEG layer 102A may function as a conductive channel.

(25) The 2-DEG layer 102A may be formed along the interface between the semiconductor layer 102 and the barrier layer 103, and in this case, the both end portions A and B of the 2-DEG layer 102A may have a bent shape. Accordingly, the 2-DEG layer 102A may extend to the surface of the semiconductor layer 102, and the both end portions A and B of the 2-DEG layer 102A may be exposed at the surface of the semiconductor layer 102.

(26) The semiconductor layer 102 may be an undoped layer, but depending on the case, may be a layer doped with a small amount of impurities. The barrier layer 103 may include, for example, at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B) among nitrides and may have a single-layer or multi-layer structure for increasing a concentration of electrons of the 2-DEG layer. For example, the barrier layer 103 may be formed in a single-layer or multi-layer structure which includes one or more of various nitrides consisting of InGaN, AlGaN, AlInGaN, AlInN, and AlN.

(27) A thickness of the barrier layer 103 may be tens nm or less, and the barrier layer 103 may be a layer to which a small amount of impurities are added or may be a layer to which impurities are not added. The semiconductor layer 102 and the barrier layer 103 may include semiconductor materials having different lattice constants, and the barrier layer 103 may have a band gap which is wider than that of the semiconductor layer 102.

(28) The 2-DEG layer 102A may be formed in the semiconductor layer 102 on the basis of band discontinuity occurring in an energy band gap and polarization occurring in an interface in hetero joining the semiconductor layer 102 to the barrier layer 103. The 2-DEG layer 102A may be directly and electrically connected to the source electrode and the drain electrode in the HEMT device and may be used as a channel (or a channel layer) through which electrons move.

(29) Although not shown in the drawing, an interface layer may be further disposed between the semiconductor layer 102 and the barrier layer 103. The interface layer may improve an interface characteristic of the semiconductor layer 102 and the barrier layer 103 to enhance an electron concentration and an electron mobility of the 2-DEG layer 102A. The interface layer may include a material such as AlN of several nm or less.

(30) Subsequently, referring to FIG. 2H, metal patterns 201 having conductivity may be formed (patterned or deposited) on the semiconductor layer 102, the barrier layer 103, and the 2-DEG layer 102A exposed at the surface of the semiconductor layer 102. Accordingly, the 2-DEG layer 102A may be electrically and directly connected to the metal patterns 201.

(31) The metal patterns 201 may be used as the drain electrode 202 and the source electrode 203 illustrated in FIG. 1, on the basis of positions thereof. The metal patterns 201 may include, for example, titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), palladium (Pd), copper (Cu), cobalt (Co), platinum (Pt), or alloy thereof. A thickness of the metal patterns 201 deposited may be several nm to several m.

(32) A method of forming the metal patterns 201 may use a photolithography process, a metal deposition process, and a liftoff process. Such processes may be processes widely known to those skilled in the art, and their detailed description may be replaced by known technology.

(33) Subsequently, referring to FIG. 2I, a process of diffusing the metal patterns 201, formed on the semiconductor layer 102, the barrier layer 103, and the 2-DEG layer 102A exposed at the surface of the semiconductor layer 102, into the barrier layer 103 and the semiconductor layer 102 may be performed through a rapid thermal process (RTP). The metal patterns 201 diffused into the barrier layer 103 and the semiconductor layer 102 may be respectively formed as the drain electrode 202 (a drain region) and the source electrode 203 (a source region).

(34) The metal patterns 201 may form an ohmic contact and may be diffused into the semiconductor layer 102 and the barrier layer 103, and under such a condition, the RTP is not limited. The drain electrode 202 and the source electrode 203 may form an ohmic contact alloy through the RTP, and the RTP may be performed in a vacuum atmosphere of 1,100 degrees C. (for example, 850 degrees C.) for 30 seconds. Although not shown, after the drain electrode 202 and the source electrode 203 are formed, device isolation may be performed by using an ion implantation process or an etching process. Additionally, after the drain electrode 202 and the source electrode 203 are formed, a thermal treatment process may not be performed based on a level of a resistance.

(35) Subsequently, referring to FIG. 2J, a process of depositing the passivation layer 204 on the semiconductor layer 102, the drain electrode 202, the source electrode 203, and the barrier layer 103 formed between the drain electrode 202 and the source electrode 203 may be performed.

(36) The passivation layer 204 may have a single-layer or multi-layer structure including one or more of SiO, SiN, and a dielectric having a high dielectric constant. The deposition process may be one of a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process, or may be a combination thereof.

(37) Subsequently, referring to FIG. 2K, in order to apply a bias voltage to the drain electrode 202 and the source electrode 203, a process of etching the passivation layer 204 formed on the drain electrode 202 and the source electrode 203 to form an opening portion 20 upward exposing a surface of each of the drain electrode 202 and the source electrode 203 may be performed. Simultaneously, a process of removing a portion of the passivation layer 204 formed between the drain electrode 202 and the source electrode 203 to form the opening portion 20 for upward exposing the barrier layer 103 may be performed. The gate electrode 205 described below may be formed on the upward exposed barrier layer 103.

(38) An etching process for forming the opening portions may be, for example, a dry etching process, a wet etching process, or a combination thereof. An etched area and thickness of the passivation layer 204 for forming the gate electrode 205 may be hundreds M or less.

(39) Subsequently, referring to FIG. 2L, the gate electrode 205 may be formed on the upward exposed barrier layer 103. The gate electrode 205 may include Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or an alloy thereof. The gate electrode 205 may be formed in a T-shape or a F-shape where a width of an upper portion thereof is greater than a width of a lower portion thereof, in order to reduce a resistance. Accordingly, the gate electrode 205 may be formed all over a surface of the passivation layer 204 and the barrier layer 103 upward exposed by the opening portion (20 of FIG. 2K) formed in the passivation layer 204.

(40) The gate electrode 205 may be formed by using a photolithography process and/or an electron beam lithography process, and after a wiring pattern is formed, by using an electron beam evaporator, a multi-layer metal including Ni or Pt may be deposited and a liftoff process may be performed.

(41) In the HEMT according to the embodiments of the present invention, a 2-DEG layer may be naturally formed near an interface between a semiconductor layer and a barrier layer on the basis of an energy band gap difference and polarization occurring due to a junction of the semiconductor layer and the barrier layer. Electrons in the 2-DEG layer may move based on a voltage applied to a source electrode, a drain electrode, and a gate electrode. However, a resistance occurring based on a condition for forming the source electrode and the drain electrode may limit the movement of the electrons, and due to this, a current may be reduced, causing a degradation in frequency characteristic.

(42) In the HEMT device according to the embodiments of the present invention, the barrier layer may be formed on the semiconductor layer so that the 2-DEG layer is exposed at a surface of the semiconductor layer, and the source electrode and the drain electrode may be formed on the 2-DEG layer exposed at the surface of the semiconductor layer. Accordingly, the 2-DEG layer may be connected to the source electrode and the drain electrode, and thus, a resistance may be minimized and a frequency characteristic of the HEMT device may be enhanced.

(43) A number of exemplary embodiments have been described above. Nevertheless, it will be understood that various modifications may be made. For example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Accordingly, other implementations are within the scope of the following claims.