High-voltage transistor and method for fabricating the same

Abstract

A structure of a semiconductor device, including a substrate, is provided. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate. The second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer. A gate layer has a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer. A dielectric layer has a top dielectric layer and a bottom dielectric layer. The top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. A method for fabricating the semiconductor device is provided too.

Claims

1. A structure of a semiconductor device, comprising: a substrate; a first gate insulating layer, disposed on the substrate; a second gate insulating layer, disposed on the substrate, wherein the second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer; a gate layer, having a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer, the second part gate covering a top surface of the second gate insulating layer facing away from the substrate, and a top surface of the second part gate being higher than a top surface of the first part gate, wherein an outer sidewall of the second part gate is aligned with an outer sidewall of the second gate insulating layer; a dielectric layer, having a top dielectric layer, a vertical dielectric layer at a sidewall of the gate layer, and a bottom dielectric layer, wherein the top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate and the second gate insulating layer, wherein the top dielectric layer, the vertical dielectric layer, and the bottom dielectric layer are connected together, and wherein the top dielectric layer and the vertical dielectric layer consist of nitride layers, and the bottom dielectric layer consists of a nitride layer and an oxide layer; and a field plate layer, disposed on the dielectric layer, and comprising a depleted region, and is at least disposed on the bottom dielectric layer, wherein outer sidewalls of opposite ends of the dielectric layer are respectively aligned with outer sidewalls of opposite ends of the field plate layer, the field plate layer further comprises a doped polysilicon layer or a doped silicon layer on the depleted region.

2. The structure of the semiconductor device according to claim 1, wherein the depleted region of the field plate layer provides an insulation capability to the dielectric layer.

3. The structure of the semiconductor device according to claim 1, wherein the depleted region of the field plate layer is only on the bottom dielectric layer.

4. The structure of the semiconductor device according to claim 1, wherein the depleted region of the field plate layer covers the top dielectric layer and the bottom dielectric layer.

5. The structure of the semiconductor device according to claim 1, wherein the field plate layer and the gate layer are to be electrically connected to the same voltage source.

6. A method for fabricating a semiconductor device, comprising: providing a substrate; forming a first gate insulating layer and a second gate insulating layer abutting to the first gate insulating layer on the substrate, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, having a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer, the second part gate covering a top surface of the second gate insulating layer facing away from the substrate, and a top surface of the second part gate being higher than a top surface of the first part gate, wherein an outer sidewall of the second part gate is aligned with an outer sidewall of the second gate insulating layer; forming a dielectric layer, having a top dielectric layer, a vertical dielectric layer at a sidewall of the gate layer, and a bottom dielectric layer, wherein the top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate and the second gate insulating layer, wherein the top dielectric layer, the vertical dielectric layer, and the bottom dielectric layer are connected together, and wherein the top dielectric layer and the vertical dielectric layer consist of nitride layers, and the bottom dielectric layer consists of a nitride layer and an oxide layer; and forming a field plate layer on the dielectric layer, wherein the field plate layer comprises a depleted region, and is at least disposed on the bottom dielectric layer, wherein outer sidewalls of opposite ends of the dielectric layer are respectively aligned with outer sidewalls of opposite ends of the field plate layer, the field plate layer further comprises a doped polysilicon layer or a doped silicon layer on the depleted region.

7. The method for fabricating the semiconductor device according to claim 6, wherein the depleted region of the formed field plate layer provides an insulation capability to the dielectric layer.

8. The method for fabricating the semiconductor device according to claim 6, wherein the depleted region of the formed field plate layer is only on the bottom dielectric layer.

9. The method for fabricating the semiconductor device according to claim 6, wherein the depleted region of the formed field plate layer covers the top dielectric layer and the bottom dielectric layer.

10. The method for fabricating the semiconductor device according to claim 6, wherein the formed field plate layer and the gate layer are to be electrically connected to the same voltage source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the descriptions, serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device that is being looked into according to an embodiment of the disclosure.

(3) FIG. 2 is a schematic diagram of a cross-sectional structure of a semiconductor device according to another embodiment of the disclosure.

(4) FIG. 3 is a schematic diagram of a cross-sectional structure of a semiconductor device according to yet another embodiment of the disclosure.

(5) FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor device according to still another embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

(6) This disclosure relates to a semiconductor device and a method for fabricating the same. The semiconductor device is, for example, a structure of a high-voltage transistor. In an embodiment, the high-voltage transistor includes a field plate to assist in operating a gate structure to control a channel region in a substrate.

(7) In an embodiment, a structure of a transistor may be achieved by using a fabrication process that is compatible with a fabrication process of a general device in other regions, which can improve an insulation capability between the field plate and the substrate in a drain region.

(8) Some exemplary embodiments are listed below to illustrate the disclosure, but the disclosure is not limited thereto. Appropriate combinations between the multiple embodiments are also allowed.

(9) FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device that is being looked into according to an embodiment of the disclosure. With reference to FIG. 1, the disclosure looks into the performance of, for example, a LDMOS transistor. A gate structure 100 of the transistor is disposed on a substrate 50. The gate structure 100 includes a gate insulating layer 102 and a gate layer (G) 104. As usual, there will be some doped regions corresponding to the conductivity type in the substrate 50, which would not be described here. The doped region of the disclosure is not limited to a specific structure. With regards to the control of the gate, a field plate layer 108 is formed on the gate structure 100 at a drain end based on the need for a high-voltage operation. The field plate 108 is above the gate structure 100 and the substrate 50, and insulation is provided by a dielectric layer 106. In addition, a gap wall 110, for example, may also be formed on a side wall of the structure.

(10) The field plate layer 108 and the gate layer 104 are connected to a same gate voltage V.sub.G. A part of the field plate layer 108 is shown on the substrate 50 to provide assistance to a control function of a channel. The drain region of the gate structure 100 abuts the field plate layer 108 and receives a drain voltage V.sub.D. A source region of the gate structure 100 receives a source voltage V.sub.S.

(11) A dielectric layer 106 provides an insulation capability between the field plate layer 108 and the substrate 50. As per the looking into by the disclosure, if a thickness of the dielectric layer 106 is insufficient, for example, as illustrated by a marked area 112, it may generate an excessively high electric field and prone to causing a collapse. In the disclosure, the insulation capability between the field plate layer 108 and the substrate 50 is being improved under a condition that is compatible with the fabrication process of the devices in the other regions, after looking into the structure of the transistor as shown in FIG. 1.

(12) FIG. 2 is a schematic diagram of a cross-sectional structure of a semiconductor device according to another embodiment. With reference to FIG. 2, in an embodiment, an overall gate insulating layer may include a first gate insulating layer 102 and a second gate insulating layer 102a. The first gate insulating layer 102 abuts the second gate insulating layer 102a, and both layers are disposed on the substrate 50. A thickness of the second gate insulating layer 102a is, for example, greater than a thickness of the first gate insulating layer 102.

(13) The gate layer 104 is formed on the first gate insulating layer 102 and the second gate insulating layer 102a. The gate layer 104 has a first part gate 104a on the first gate insulating layer 102. The gate layer 104 also has a second part gate 104b on the second gate insulating layer 102a. In this way, the gate layer 104 and the substrate 50 will achieve a greater insulation capability near the drain end. The second gate insulating layer 102a is, for example, a structure of a field oxide layer, so as to obtain a greater thickness, but is not limited thereto.

(14) In an embodiment, for example, both the first gate insulating layer 102 and the second gate insulating layer 102a are oxides. In an embodiment, a dielectric layer 102b that is an oxide may also be formed on the substrate 50 first according to a change in the fabrication process. The dielectric layer 102b is configured to provide insulation between the substrate 50 and a subsequently formed field plate layer 206.

(15) In an embodiment, the dielectric layer 102b may be a part of an overall dielectric layer 200. In an embodiment, the dielectric layer 200 includes a top dielectric layer 200a covering the gate layer 104, such as covering the second part gate 104b. The dielectric layer 200 also includes a bottom dielectric layer 200c covering the substrate 50. The dielectric layer 200 also includes a vertical layer 200b at a side wall of the gate layer 104, which connects the bottom dielectric layer 200c and the top dielectric layer 200a. As mentioned previously, the bottom dielectric layer 200c includes the bottom dielectric layer 102b.

(16) In an embodiment, the dielectric layer 200 is, for example, a nitride or an oxide, and the top dielectric layer 200a, the vertical layer 200b, and the bottom dielectric layer 200c may be formed together. The dielectric layer 102b may be formed first during the process of forming other devices, but is not limited thereto.

(17) In an embodiment, both the top dielectric layer 200a and the vertical layer 200b are nitride layers, and the bottom dielectric layer 200c is a stacked layer of an oxide and a nitride.

(18) In an embodiment, the field plate layer 206 is formed on the dielectric layer 200. It should be noted here that a material of the field plate layer 206, in an embodiment, forms a doped layer 202 such as a doped silicon layer or a doped polysilicon layer according to, for example, a deposition manner or an epitaxial growth manner. In addition, the depleted region 204 may be formed in the field plate layer 206 according to the technology of the doping process. The depleted region 204 may, for example, also be an undoped region or at a level close to being undoped. A function of the depleted region 204 may be to provide the insulation capability. Therefore, in actual effect, the depleted region 204 is formed through the control of the doping technology during the process of forming the field plate layer 206, so as to substantially provide the function of an insulating layer. In such an embodiment, the bottom dielectric layer 200c of the dielectric layer 200 may not need to form an insulating layer to increase thickness, so as to achieve the insulation capability. The insulation capability may be provided by the depleted region 204 of the field plate layer 206. The depleted region 204 may provide an additional insulating layer in the substantial effect.

(19) The formation of the depleted region 204 may be controlled or adjusted by, for example, an implanting process. In an embodiment, when the depleted region 204 uses an epitaxial growth process, it may be formed by controlling the dopants during the growth process. The formation of the depleted region 204 is not limited to a specific manner.

(20) FIG. 3 is a schematic diagram of a cross-sectional structure of a semiconductor device according to yet another embodiment of the disclosure. With reference to FIG. 3, in an embodiment, the formation of the depleted region 204 may also be to cover the dielectric layer 200 completely. The formation of the dielectric layer 200 is as described previously and will not be reiterated here.

(21) FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor device according to still another embodiment. With reference to FIG. 4, in an embodiment, the dielectric layer 200 may be a single-layer structure of the same material according to a change in the fabrication process. The bottom dielectric layer 200c is, for example, an oxide or a nitride, instead of a stacked layer of an oxide and a nitride.

(22) The dielectric layer 200 of the disclosure may be compatibly formed according to the fabrication process of the devices in the other regions. The depleted region 204 is formed during the formation of the field plate layer 206, under a condition of a thickness that the dielectric layer 200 may be formed, which may further provide the function of an insulating layer to improve the insulation capability at the drain end, thereby increasing the collapse voltage.

(23) Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the disclosure, and are not intended to limit them. Although the disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still make changes and modifications to the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure is defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated.