METHOD OF FORMING A FINFET STRUCTURE

Abstract

A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi.sub.2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Claims

1. A method for manufacturing a FET semiconductor structure, the method comprising: providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET; selectively depositing a TiSi.sub.2 film with C54 structure directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate; and replacing the dummy gate with a replacement metal gate.

2. The method of claim 1, wherein the selectively depositing the TiSi.sub.2 film is performed before the replacing of the dummy gate with the replacement metal gate.

3. The method of claim 1, where the selectively depositing the TiSi.sub.2 film comprises exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas.

4. The method of claim 3, wherein the titanium-containing precursor gas comprises TiCl.sub.4.

5. The method of claim 3, wherein the silicon-containing precursor gas comprises at least one of SiH.sub.4, SiH.sub.2Cl.sub.2, SiHCl.sub.3, and SiCl.sub.4.

6. The method of claim 3, wherein the process gas comprises TiCl.sub.4 and SiH.sub.4.

7. The method of claim 3, wherein the process gas further comprises H.sub.2 gas.

8. The method of claim 3, further comprising: maintaining gas pressure between about 1 mTorr and about 50 mTorr; and maintaining a substrate temperature between about 700° C. and about 800° C.

9. The method of claim 1, further comprising depositing, after depositing the TiSi.sub.2 film, an etch stop layer over the at least one source/drain contact, the dummy gate, the gate spacer, and the TiSi.sub.2 film.

10. The method of claim 9, further comprising depositing a dielectric over the etch stop layer.

11. The method of claim 1, further comprising cleaning the at least one source/drain contact using a cleaning process prior to the selectively depositing of the TiSi.sub.2 film.

12. The method of claim 11, wherein the cleaning process comprises exposing the source/drain contact to a thermal H2 gas at a gas pressure between about 100 mTorr and about 700 mTorr, at a substrate temperature between about 600° C. and about 800° C., for a time period between about 10 sec and about 60 sec.

13. The method of claim 11, wherein the cleaning process comprises exposing the source/drain contact to a thermal NH3 and HF gas at a gas pressure between about 1 Torr and about 3 Torr, at a substrate temperature between about 35° C. and about 100° C., for a time period between about 10 sec and about 60 sec.

14. The method of claim 11, wherein the cleaning process comprises exposing the source/drain contact to a thermal NF3 and H2 gas at a gas pressure between about 1 Torr and about 3 Torr, at a substrate temperature between about 20° C. and about 100° C., for a time period between about 10 sec and about 60 sec.

15. The method of claim 1, wherein no anneal step is performed between the selectively depositing and the replacing steps.

16. The method of claim 1, further comprising an anneal step performed between the selectively depositing and the replacing steps.

17. A field effect transistor (FET) semiconductor device comprising: a substrate containing at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a gate of the at least one FET and comprising an upper portion which is line-of-sight from a top of the substrate and a lower portion which is line-of-sight from a bottom of the substrate; and a TiSi.sub.2 film with C54 structure conformally covering both the top and bottom portions of the at least one source/drain contact.

18. The FET semiconductor device of claim 17, wherein the source/drain contact comprises epitaxial Si.

19. The FET semiconductor device of claim 17, further comprising a gate spacer between the at least one source/drain contact and the gate.

20. The FET semiconductor device of claim 19, wherein the gate spacer comprises SiN.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or reduced for clarity of discussion.

[0027] FIG. 1 shows a conventional method for FinFET manufacturing compared to a method for FinFET manufacturing in accordance with an example embodiment of the present disclosure;

[0028] FIG. 2 shows a schematic of a FinFET structure in accordance with an example embodiment of the present disclosure;

[0029] FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I and 3J illustrate various process steps for a conventional method to manufacture a FinFET;

[0030] FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate various process steps for a new method to manufacture a FinFET in accordance with an example embodiment of the present disclosure; and

[0031] FIGS. 5A and 5B illustrate a comparison of a conventional FinFET structure to a FinFET structure in accordance with an example embodiment of the present disclosure.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0032] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0033] The present invention will be described in terms of various illustrative example processes for fabricating FET semiconductor structures on a circuit supporting substrate. These fabrication processes may be used to fabricate planar FET semiconductor devices, FinFET semiconductor devices, or both types of semiconductor devices, on a circuit supporting substrate.

[0034] FIG. 1 shows process flows for conventional gate first FinFET manufacturing process 300 in comparison to a method for FinFET manufacturing 400 according to an embodiment of the invention. The conventional FinFET manufacturing is represented by flow steps 3A-3J which includes the formation of a replacement metal gate (RMG) in step 3D before forming a titanium silicide (TiSi.sub.2) film on a source/drain contact in steps 3G-3I. Forming the TiSi.sub.2 film is achieved by non-selective physical vapor deposition (PVD) of Ti metal on epitaxial Si of the source/drain contact in step 3G, followed by deposition of a TiN liner on the Ti metal in step 3H, and thereafter in step 3I an anneal is performed that reacts the Ti metal with Si in the source/drain contact to form a low-resisitivity titanium silicide (i.e., TiSi.sub.2 with C54 structure). The Ti metal PVD is a line-of-sight deposition method and the Ti metal deposition can therefore not be used for wrap-around deposition on the source/drain contacts. Additional details related to the conventional FinFET will be discussed with respect to correspondingly numbered FIGS. 3A-3J.

[0035] The conventional FinFET manufacturing method has a number of potentially problematic issues that can lead to poor quality of TiSi.sub.2 formation, such as residual contact etch stop layer (CESL) SiN, damaged epitaxial Si after reactive-ion etching (ME), reduced metal contact area, and partial formation of TiSi.sub.2by thermal anneal due to thermal budget of (WF) materials.

[0036] In contrast, embodiments of the disclosure provide a method of FinFET manufacturing where the RMG is formed after forming a titanium silicide film on a source/drain contact as shown by example process steps 4A-4H in FIG. 1. Additional details related to these steps will be discussed with respect to correspondingly numbered FIGS. 4A-4H. The titanium silicide may be deposited as a fully formed TiSi.sub.2 film with C54 structure, thereby making a subsequent anneal optional. The titanium silicide may, for example, be selectively deposited on the source/drain contact by exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the process gas can contain SiH.sub.4 and TiCl.sub.4.

[0037] Embodiments of the disclosure, provide a one-step wrap-around TiSi.sub.2 film formation on source/drain contacts with significantly improved interface quality compared to conventional methods. The TiSi.sub.2 film is fully formed with low electrical resistance and does not rely on Si diffusion from the source/drain contact. The method enables a novel integrated process flow which eliminates damage to epitaxial Si source/drain contacts, eliminates formation of an etch stop layer residual formed on the source/drain contacts, and reduces source/drain contact resistance.

[0038] FIG. 2 schematically shows a FinFET. The FinFET includes a fin 201, epitaxial Si source/drain (S/D) contacts 203 on the fin 201, a gate dielectric 205 over the fin 201, and a metal gate 207 over the gate dielectric 205. A fin cut A-A′ is indicated across the epitaxial Si source/drain 203 and the fin 201, and a gate cut B-B′ is indicated along the length of the fin 201. Similar fin cuts and a gate cuts across a FinFET are shown in FIGS. 3A-3J and 4A-4H, discussed later herein.

[0039] FIGS. 3A-3J schematically show a conventional method of forming a FinFET according a gate first process. Each of FIGS. 3A-3J includes a top illustration of a gate cut view such as B-B′ in FIG. 2, and a bottom illustration of a fin cut view such as A-A′ of FIG. 2. Unlike the FinFET in FIG. 2, the gate cut views of FIGS. 3A-3J show three adjacent gates, and the fin cut views show two adjacent S/D contacts. FIG. 3A shows S/D contacts 301, gate spacers 303, dummy gates 305, contact holes 306, and fins 307. For example, the S/D contact 301 can include epitaxial Si, the fin 307 can include Si, the gate spacer 303 can include SiN, and/or the dummy gate 305 can include poly Si. While the fin cut views of FIGS. 3A-3J show S/D contacts 301 physically connected to each other to form a common S/D for a two fin device, the S/D contacts 301 may be separated from each other and associated with respective single fin devices.

[0040] FIG. 3B shows the FinFET following deposition of a conformal etch stop layer (ESL) 309. As seen, ESL 309 is deposited on downward facing surfaces of the S/D contacts 301 except for the middle region which is not exposed to the deposition gas due to physical connection of the S/D contacts 301 into a common S/D as noted above. With embodiments including a single S/D contact, or adjacent S/D contacts physically separated from each other, the ESL 309 is deposited on all downward facing surfaces exposed to the gas environment for depositing the ESL. In one example, the ESL 309 can contain SiN.

[0041] FIG. 3C shows the FinFET following a blanket deposition of a dielectric 311 layer over the ESL 309 and which fills the contact holes 306.

[0042] FIG. 3D shows the FinFET following planarization and the replacement of the dummy gate 305 with a replacement metal gate (RMG) 313.

[0043] FIG. 3E shows the FinFET following an anisotropic oxide etch that exposes the ESL 309 in the contact holes 306.

[0044] FIG. 3F shows the FinFET following an anisotropic nitride etch that exposes the S/D contact 301 in the contact holes 306.

[0045] FIG. 3G shows the FinFET following deposition of Ti metal 315 in the contact holes 306 by PVD which deposits Ti metal 315 only on the S/D contact 301 and not on the sidewall.

[0046] FIG. 3H shows the FinFET following conformal deposition of a TiN layer 317 in the contact holes 306

[0047] FIG. 3I shows the FinFET following an annealing that forms a TiSi.sub.2 layer 319 by reaction of the Ti metal 315 and Si in the epitaxial Si S/D contact 301.

[0048] FIG. 3J shows the FinFET following filling of the contact hole 306 with a metal 321.

[0049] FIGS. 4A-4H schematically show a method of forming a FinFET according a gate last process according to an embodiment of the present disclosure. Each of FIGS. 4A-4H includes a top illustration of a gate cut view such as B-B′ in FIG. 2, and a bottom illustration of a fin cut view such as A-A′ of FIG. 2. Unlike the FinFET in FIG. 2, the gate cut views of FIGS. 4A-4J show three adjacent gates, and the fin cut views show two adjacent S/D contacts. FIG. 4A shows S/D contacts 401, gate spacers 403, dummy gates 405, contact holes 406, and fins 407. For example, the S/D contact 401 can include epitaxial Si, the fin 407 can include Si, the gate spacer 403 can include SiN, and/or the dummy gate 405 can include poly Si. While the fin cut views of FIGS. 4A-4H show S/D contacts 401 physically connected to each other to form a common S/D for a two fin device, the S/D contacts 401 may be separated for from each other and associated with respective single fin devices.

[0050] A surface of the epitaxial Si S/D contact 401 may be cleaned of any SiO.sub.2 by using a cleaning process. A cleaning process may be used that provides good selectivity between SiO.sub.2 and a SiN gate spacer 403. The cleaning process facilitates good subsequent deposition of a TiSi.sub.2 film on the epitaxial Si. In one example, the cleaning process can include a thermal H.sub.2 gas exposure at a gas pressure between about 600 mTorr and about 700 mTorr, a substrate temperature between about 700° C. and about 800° C., and a time period between about 10 sec and about 30 sec. In another example, the cleaning process can include a thermal H.sub.2 gas exposure at a gas pressure between about 100 mTorr and about 700 mTorr, a substrate temperature between about 600° C. and about 800° C., and a time period between about 10 sec and about 60 sec. In another example, the cleaning process can include a thermal NH.sub.3 and HF gas exposure at a gas pressure between about 1 Torr and about 3 Torr, a substrate temperature between about 35° C. and about 100° C., and a time period between about 10 sec and about 30 sec, or alternatively a time period between about 10 sec and about 60 sec. In yet another example, the cleaning process can include a thermal NF.sub.3 and H.sub.2 gas exposure at a gas pressure between about 1 Torr and about 3 Torr, a substrate temperature between about 20° C. and about 100° C., and a time period between about 10 sec and about 30 sec, or alternatively a time period between about 10 sec and about 60 sec.

[0051] FIG. 4B shows the FinFET following selective deposition of a TiSi.sub.2 film 409 with C54 structure directly on and fully covering the S/D contact 401 relative to a vertical sidewall of the gate spacer 403 between the S/D contact 401 and the dummy gate 405. Importantly, the TiS.sub.2 film 419 may be deposited as a fully formed TiSi.sub.2 film 419 with C54 structure, thereby making a subsequent anneal optional. TiSi.sub.2 film 419 wraps-around the S/D contact 401, including lower surfaces that are not line-of-sight from above the substrate. The selectively deposition can include exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the titanium-containing precursor gas can include TiCl.sub.4. For example, the silicon-containing precursor gas can include SiH.sub.4, SiH.sub.2Cl.sub.2, SiHCl.sub.3, or SiCl.sub.4. In one example, the process gas can contain SiH.sub.4 and TiCl.sub.4. The process gas may further include H.sub.2 gas. The gas pressure can, for example, be between about 1 mTorr and about 50 mTorr, or between about 5 mTorr and about 20 mTorr. A substrate temperature can, for example, be between about 700° C. and about 800° C.

[0052] FIG. 4C shows the FinFET following deposition of a conformal etch stop layer (ESL) 409. As seen, ESL 409 is deposited on downward facing surfaces of the S/D contacts 401 except for the middle region which is not exposed to the deposition gas due to physical connection of the S/D contacts 401 into a common S/D as noted above. With embodiments including a single S/D contact, or adjacent S/D contacts physically separated from each other, the ESL 409 is deposited on all downward facing surfaces exposed to the gas environment for depositing the ESL. In one example, the ESL 409 can contain SiN.

[0053] FIG. 4D shows the FinFET following a blanket deposition of a dielectric 411 layer that fills the contact holes 406.

[0054] FIG. 4E shows the FinFET following the replacement of the dummy gate 405 with a replacement metal gate (RMG) 413. In one example, the replacement may be performed by planarizing the structure down to the ESL 409 using chemical mechanical planarization (CMP), forming a patterned mask that exposes the dummy gate 405, removing the dummy gate 405 (e.g., poly Si) by a plasma etching process, thereby forming a recessed feature, depositing a conformal high-k dielectric layer (not shown) in the recessed feature, partially filling the recessed feature with tungsten (W) metal, and filling the remaining portion of the recessed feature with SiN.

[0055] FIG. 4F shows the FinFET following an anisotropic etch that exposes the ESL 409 in the contact holes 406.

[0056] FIG. 4G shows the FinFET following an anisotropic etch that exposes the TiSi.sub.2 film 419 on the S/D contact 401 in the contact holes 406.

[0057] FIG. 4H shows the FinFET following filling of the contact hole 406 with a metal 415. As can be seen, since the dummy gate 405 is replaced with the RMG 414 after the TiSi.sub.2 film 409 has been deposited, the FinFET has TiSi.sub.2 film 409 deposited around the entire perimeter of the S/D contact 401 (apart from the portion of the perimeter in contact with the fin 407). This direct formation of the TiSi.sub.2 film 409 on the S/D contact 401 can improve interface quality, reduce contact resistance from the increased contact area, and mitigate thermal budget concerns due to the high thermal stability of the TiSi.sub.2 film 409.

[0058] Therefore, it can be appreciated that the devices discussed herein, and variations thereof, can be viewed as a system. In one embodiment, a FET semiconductor device comprises: a substrate containing at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a gate of the at least one FET; and a TiSi2 film with C54 structure directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the gate. One example of such a system is shown in FIG. 4H.

[0059] FIG. 5A is a schematic representation of the structure resulting from a conventional FinFET manufacturing method. As seen, the structure includes residual contact etch stop layer (CESL) SiN 387, and damaged epitaxial Si 381 after reactive-ion etching (RIE) process. The TiSi.sub.2layer 385 is only partially formed due to low thermal budgets for (WF) materials. Further, TiSi.sub.2 has a reduced metal contact area 383. FIG. 5B is a schematic representation of the structure resulting from a FinFET manufacturing method according to embodiments disclosed herein where the RMG is formed after forming a titanium silicide film on a source/drain contact as discussed in FIGS. 4A-4H. As seen, the TiSi.sub.2 film 419 is fully formed with a lower portion 419′ that is not line of sight from the top of the substrate. This enables a low electrical resistance and does not rely on Si diffusion from the source/drain contact. Further, the disclosed method eliminates damage to epitaxial Si source/drain contacts, eliminates formation of an etch stop layer residual formed on the source/drain contacts, and reduces source/drain contact resistance.

[0060] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0061] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

[0062] “Substrate” or “wafer” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0063] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.