Integrated Structures Containing Vertically-Stacked Memory Cells
20170373081 ยท 2017-12-28
Assignee
Inventors
- Haitao Liu (Boise, ID, US)
- Chandra Mouli (Boise, ID)
- Sergei Koveshnikov (Boise, ID, US)
- Dimitrios Pavlopoulos (Boise, ID, US)
- Guangyu Huang (Boise, ID, US)
Cpc classification
H10B43/27
ELECTRICITY
H10D64/035
ELECTRICITY
International classification
Abstract
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
Claims
1. An integrated structure comprising: a stack of alternating dielectric levels and conductive levels; vertically-stacked memory cells within the conductive levels, each of the vertically stacked memory cells comprising a charge trapping region; an opening extending through the stack; and channel material within the opening and along the memory cells, with at least some of the channel material comprising germanium, the channel material being spaced from the charge trapping regions by gate dielectric material.
2. The integrated structure of claim 1 wherein an entirety of the channel material comprises Si.sub.(1-x)Ge.sub.x; where x is a number greater than zero, and less than or equal to 1.
3. The integrated structure of claim 1 wherein said at least some of the channel material comprises a concentration of germanium within a range of from about 10 atomic percent to about 30 atomic percent.
4. The integrated structure of claim 1 wherein the channel material comprises a horizontally-extending gradient of germanium concentration.
5. The integrated structure of claim 4 wherein the channel material has an exterior surface along a sidewall of the opening and an interior region horizontally offset from the exterior surface, and wherein the germanium concentration increases along a direction from the exterior surface toward the interior region.
6. The integrated structure of claim 4 wherein the channel material has an exterior surface along a sidewall of the opening and an interior region horizontally offset from the exterior surface, and wherein the germanium concentration decreases along a direction from the exterior surface toward the interior region.
7. The integrated structure of claim 1 wherein the channel material comprises a liner of non-germanium-containing material and a region of germanium-containing material, with the liner being between a sidewall of the opening and said region of germanium-containing material.
8. The integrated structure of claim 1 further comprising at least one dopant within a germanium-containing region of the channel material; the dopant being p-type, n-type or i-type.
9. The integrated structure of claim 8 wherein the germanium-containing region of the channel material comprises a horizontally-extending gradient of dopant concentration.
10. The integrated structure of claim 8 wherein the germanium-containing region of the channel material comprises a horizontally-extending gradient of dopant concentration and a horizontally-extending gradient of germanium concentration.
11. The integrated structure of claim 1 wherein the channel material completely fills the opening.
12. The integrated structure of claim 1 wherein the channel material lines sidewalls of the opening to leave a hollow within the opening.
13. The integrated structure of claim 1 wherein the gate oxide is disposed entirely within the conductive levels.
14. An integrated structure comprising, along a cross-section: a stack of alternating dielectric levels and conductive levels; vertically-stacked memory cells within the conductive levels, the vertically stacked memory cells comprising a charge storage material and a charge blocking material, and having a planar surface across the charge blocking material and the charge storage material, the planar surface contacting dielectric material of the dielectric levels; an opening extending through the stack; germanium-containing channel material liners within the opening and along the memory cells; and an insulator-filled hollow within the opening and between the germanium-containing liners.
15. The integrated structure of claim 14 wherein the germanium-containing channel material liners comprise horizontally-extending gradients of germanium concentration.
16. The integrated structure of claim 15 wherein the germanium-containing channel material liners have exterior surfaces along sidewalls of the opening and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each liner increases along a direction from the exterior surface toward the interior region.
17. The integrated structure of claim 15 wherein the germanium-containing channel material liners have exterior surfaces along sidewalls of the opening and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each liner decreases along a direction from the exterior surface toward the interior region.
18. The integrated structure of claim 15 wherein the germanium-containing channel material liners have first exterior surfaces along sidewalls of the opening, second exterior surfaces along the insulator-filled hollow, and interior regions between the first and second exterior surfaces; and wherein the germanium concentration of each liner increases along a first direction from the first exterior surface toward the interior region, and increases along a second direction from the second exterior surface toward the interior region.
19. An integrated structure comprising, along a cross-section: a stack of alternating dielectric levels and conductive levels; vertically-stacked memory cells within the conductive levels, the vertically-stacked memory cells comprising a charge storage material and a charge blocking material, and having a planar surface across the charge blocking material and the charge storage material, the planar surface contacting dielectric material of the dielectric levels; an opening extending through the stack; non-germanium-containing channel material liners along sidewalls of the opening and along the memory cells; germanium-containing channel material liners within the opening and along the non-germanium-containing material liners; and an insulator-filled hollow within the opening and between the germanium-containing liners.
20. The integrated structure of claim 19 wherein the germanium-containing channel material liners comprise horizontally-extending gradients of germanium concentration.
21. The integrated structure of claim 20 wherein the germanium-containing channel material liners have exterior surfaces along the non-germanium-containing channel material liners and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each germanium-containing channel material liner increases along a direction from the exterior surface toward the interior region.
22. The integrated structure of claim 20 wherein the germanium-containing channel material liners have exterior surfaces along the non-germanium-containing channel material liners and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each germanium-containing channel material liner decreases along a direction from the exterior surface toward the interior region.
23. The integrated structure of claim 20 wherein the germanium-containing channel material liners have first exterior surfaces along the non-germanium-containing channel material liners, second exterior surfaces along the insulator-filled hollow, and interior regions between the first and second exterior surfaces; and wherein the germanium concentration of each germanium-containing channel material liner increases along a first direction from the first exterior surface toward the interior region, and increases along a second direction from the second exterior surface toward the interior region.
24. The integrated structure of claim 19 wherein the non-germanium-containing channel material liners comprise semiconductor material.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0005]
[0006]
[0007]
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
[0008] Some embodiments include utilization of germanium or silicon/germanium within the channel material of vertical NAND configurations. Germanium has better mobility than the silicon conventionally utilized for the channel material, which may improve current conduction along a NAND string. Example embodiments are described with reference to
[0009] Referring to
[0010] The levels 18 and 20 may be of any suitable thicknesses; and may, for example, have thicknesses within a range of from about 5 nm to about 300 nm. In some applications, the levels 18 may be thinner than the levels 20. For instance, levels 18 may be about 20 nm thick and levels 20 may be about 30 nm thick.
[0011] Charge-storage material 24 is adjacent the conductive levels 20, and is spaced from the conductive material of levels 20 by charge-blocking material 22.
[0012] The charge-storage material 24 may comprise any suitable composition or combination of compositions; and in some embodiments may comprise floating gate material (for instance, doped or undoped silicon) or charge-trapping material (for instance, silicon nitride, metal dots, etc.).
[0013] The charge-blocking material 22 may comprise any suitable composition or combination of compositions; and in some embodiments may comprise one or more of silicon dioxide, hafnium oxide, zirconium oxide, silicon nitride, etc.
[0014] Gate dielectric 26 is adjacent charge-storage material 24. The gate dielectric may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, for example, silicon dioxide.
[0015] An opening 27 extends through the stack 15, and in the shown embodiment such opening is entirely filled with channel material 28. The channel material comprises germanium. For instance, the channel material may comprise Si.sub.(1-x)Ge.sub.x; where x is a number greater than zero, and less than or equal to 1. In some embodiments, the channel material may comprise, consist essentially of, or consist of, silicon and germanium. The germanium may be present to, for example, a concentration within a range of from about 5 atomic percent to about 80 atomic percent. As another example, the germanium may be present to a concentration within a range of from about 10 atomic percent to about 30 atomic percent.
[0016] In some embodiments, the channel material may comprise one or more dopants. In such embodiments, the dopants may be p-type, n-type and/or i-type.
[0017] The various materials 22, 24 and 26, together with regions of conductive levels 20 and channel material 28, form a first series of vertically-stacked memory cells 30a and 30b, and a second series of vertically-stacked memory cells 31a and 31b. The vertically-stacked memory cells 30a and 30b may be considered to form a first NAND string, and the vertically-stacked memory cells 31a and 31b may be considered to form a second NAND string. The memory cells may be considered to be within the conductive levels 20 (i.e., elevationally coextensive with the conductive levels) in the illustrated embodiment.
[0018] The number of memory cells in each vertical string is determined by the number of conductive levels 20. The stack may comprise any suitable number of conductive levels. In some embodiments, the stack 15 may comprise 8 conductive levels, 16 conductive levels, 32 conductive levels, 64 conductive levels, 1024 conductive levels, etc.
[0019] The cross-section section of
[0020] The channel material 28 of
[0021] Referring to
[0022] The germanium concentration gradient may increase from any suitable first concentration to any suitable second concentration. For instance, in some embodiments the first concentration may be about 0 atomic percent germanium and the second concentration may be about 100 atomic percent germanium. As another example, the first concentration may be about 0 atomic percent germanium and the second concentration may be about 85 atomic percent germanium. As another example, the first concentration may be about 5 atomic percent germanium and the second concentration may be about 85 atomic percent germanium. As another example, the first concentration may be about zero atomic percent germanium and the second concentration may be about 30 atomic percent germanium. As another example, the first concentration may be about 10 atomic percent germanium and the second concentration may be about 30 atomic percent germanium.
[0023]
[0024] The embodiments of
[0025] Although the embodiments of
[0026] The embodiments of
[0027] The liners 44 and 46 comprise liner material 45. Such liner material may be a non-germanium-containing material. In some embodiments, the liner material may be non-germanium-containing semiconductor material (and in particular embodiments may be a wide band-gap containing semiconductor material). For example, the liner material may comprise silicon (which may be monocrystalline, polycrystalline, amorphous, etc.), III/V semiconductor material, II/VI semiconductor material, etc. For instance, the liners may comprise silicon carbide, gallium arsenide, zinc oxide, indium oxide, tin oxide, etc. The liners may be doped in some embodiments, and in other embodiments may be undoped.
[0028] In the embodiment of
[0029] The liners 44 and 46 may have any suitable thicknesses, and in some embodiments may have thicknesses within a range of from about one monolayer to about 60 , thicknesses within a range of from about 20 to about 50 , etc.
[0030] The liners may advantageously enable channel material properties to be tailored for specific applications. For instance, in some embodiments the liners may be kept thin enough so that channel conduction of vertically-stacked memory cells (e.g., memory cells 30a, 30b, 31a and 31b) extends through the semiconductor material of the liners, and also through a region of the germanium-containing material 28 adjacent the liners (as shown). Accordingly, the compositions of the liners and the germanium-containing material 28 may be independently adjusted to tailor electrical, physical and/or chemical properties for specific applications. In some embodiments, the liners may increase a distance from tunnel dielectric 26 of the memory cells (e.g., 30a, 30b, 31a and 31b) to channel material 28, which may reduce coulombic scattering.
[0031] The embodiments of
[0032] Referring to
[0033] The liners 48 and 50 may have any suitable thicknesses T; and in some embodiments may have thicknesses within a range of from about 2 nanometers (nm) to about 50 nm.
[0034] The germanium-containing material 28 of liners 48 and 50 may comprise any of the compositions described above with reference to the germanium-containing material 28 of
[0035] Referring to
[0036] The liners 48 and 50 may be considered to comprise interior regions 60 and 62 respectively (with such interior regions being inward of the exterior surfaces, and thus being horizontally-offset relative to the exterior surfaces), and the embodiment of
[0037]
[0038]
[0039] An advantage of the configuration of
[0040] The embodiments of
[0041] Although the embodiments of
[0042] In some embodiments, the germanium-containing liners of
[0043] In the embodiment of
[0044] The germanium-containing material 28 of liners 48 and 50 may be homogeneous, or may comprise horizontally-extending germanium gradients of the types described above with reference to
[0045] The structures described above may be supported by an underlying substrate (not shown). The substrate may comprise semiconductor material (for example, may comprise, consist essentially of, or consist of monocrystalline silicon), and may be referred to as a semiconductor substrate. The term semiconductor substrate means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term substrate refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
[0046] The integrated structures described herein may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
[0047] Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.
[0048] Both of the terms dielectric and electrically insulative may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term dielectric in some instances, and the term electrically insulative in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.
[0049] The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.
[0050] The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.
[0051] When a structure is referred to above as being on or against another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being directly on or directly against another structure, there are no intervening structures present. When a structure is referred to as being connected or coupled to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being directly connected or directly coupled to another structure, there are no intervening structures present.
[0052] Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
[0053] Some embodiments include an integrated structure comprising, along a cross-section, a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an opening extending through the stack, germanium-containing channel material liners within the opening and along the memory cells, and an insulator-filled hollow within the opening and between the germanium-containing liners.
[0054] Some embodiments include an integrated structure comprising, along a cross-section, a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an opening extending through the stack, non-germanium-containing channel material liners along sidewalls of the opening and along the memory cells, germanium-containing channel material liners within the opening and along the non-germanium-containing material liners, and an insulator-filled hollow within the opening and between the germanium-containing liners.
[0055] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.