MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device

Abstract

A mask used to form an n.sup.+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n.sup.+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n.sup.+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Claims

1. A manufacturing method of a MOS-driven semiconductor device, comprising: selectively forming a channel layer of a second conducting type in a surface layer of a first semiconductor layer of a first conducting type; selectively forming a nitride film on a surface of the channel layer; forming a first mask on the nitride film and an exposed face of the channel layer, the first mask being used to form a trench; forming the trench that passes through the channel layer to the first semiconductor layer, using the first mask; removing the first mask to expose the nitride film; forming a gate insulating film on an inner wall of the trench; embedding a gate electrode in the trench through the gate insulating film such that a height of a surface of the gate electrode is along a side face of the channel layer; ion-implanting, in a surface layer of the channel layer and using the gate electrode and the nitride film as a second mask, an impurity of the first conducting type to form a second semiconductor layer that is of the first conducting type and has an L-shape; removing the nitride film, and forming an oxide film that is made of an LP-TEOS film or an HTO film, such that a recess remains at an upper portion of the trench, the recess being above the gate electrode and extending to side walls of the trench; forming a non-doped poly-silicon layer on the gate electrode to fill the recess through the oxide film; ion-implanting into the surface of the channel layer, an impurity of the second conducting type to form a third semiconductor layer that is of the second conducting type and has an impurity concentration that is higher than that of the channel layer and that is lower than that of the second semiconductor layer; activating, by annealing, the ion-implanted impurities of the first and the second conducting types; and forming a main electrode that is in contact with the second semiconductor layer and the third semiconductor layer.

2. The manufacturing method of a MOS-driven semiconductor device according to claim 1, wherein a thickness of the oxide film is 0.1 micrometer or more and 0.3 micrometer or less.

3. The manufacturing method of a MOS-driven semiconductor device according to claim 1, wherein an interval of the trench is 0.2 micrometer or more and 0.8 micrometer or less.

4. The manufacturing method of a MOS-driven semiconductor device according to claim 1, wherein a heat treatment process to oxidize and insulate the non-doped poly-silicon layer is not performed.

5. A manufacturing method of a MOS-driven semiconductor device, comprising: selectively forming a channel layer of a second conducting type in a surface layer of a first semiconductor layer of a first conducting type; forming a first mask on a surface of the channel layer, the first mask being used to form a trench; forming the trench that passes through the channel layer to the first semiconductor layer, using the first mask; forming a gate insulating film on an inner wall of the trench; embedding a gate electrode in the trench through the gate insulating film such that a height of a surface of the gate electrode is along a side face of the channel layer; ion-implanting, in a side wall of the trench and using at least the gate electrode as a second mask, an impurity of the first conducting type to form a second semiconductor layer that is of the first conducting type; forming an oxide film that is made of an LP-TEOS film or an HTO film, such that a recess remains at an upper portion of the trench, the recess being above the gate electrode and extending to side walls of the trench; filling the recess and forming a non-doped poly-silicon layer on the gate electrode through the oxide film; ion-implanting into the surface of the channel layer, an impurity of the second conducting type to form a third semiconductor layer that is of the second conducting type and has an impurity concentration that is higher than that of the channel layer and that is lower than that of the second semiconductor layer; activating, by annealing, the ion-implanted impurities of the first and the second conducting types; and forming a main electrode that is in contact with the second semiconductor layer and the third semiconductor layer, wherein a heat treatment process to oxidize and insulate the non-doped polysilicon layer is not performed.

6. The manufacturing method of a MOS-driven semiconductor device according to claim 5, wherein a thickness of the oxide film is 0.1 micrometer or more and 0.3 micrometer or less.

7. A manufacturing method of a MOS-driven semiconductor device, comprising: selectively forming a channel layer of a second conducting type in a surface layer of a first semiconductor layer of a first conducting type; selectively forming a nitride film on a surface of the channel layer; forming a first mask on the nitride film and an exposed face of the channel layer, the first mask being used to form a trench; forming the trench that passes through the channel layer to the first semiconductor layer, using the first mask; removing the first mask to expose the nitride film; forming a gate insulating film on an inner wall of the trench; embedding a gate electrode in the trench through the gate insulating film such that a height of a surface of the gate electrode is along a side face of the channel layer; ion-implanting, in a surface layer of the channel layer and using the gate electrode and the nitride film as a second mask, an impurity of the first conducting type to form a second semiconductor layer that is of the first conducting type and has an L-shape; removing the nitride film, and forming an insulation film on the gate electrode; ion-implanting into the surface of the channel layer an impurity of the second conducting type to form a third semiconductor layer that is of the second conducting type and has an impurity concentration that is higher than that of the channel layer and that is lower than that of the second semiconductor layer; activating, by annealing, the ion-implanted impurities of the first and the second conducting types; and forming a main electrode that is in contact with the second semiconductor layer and the third semiconductor layer.

8. The manufacturing method of a MOS-driven semiconductor device according to claim 7, wherein the forming the insulation film on the gate electrode includes: forming an oxide film being made of an LP-TEOS film or an HTO film such that a recess remains at an upper portion of the trench, the recess being above the gate electrode and extending to side walls of the trench; forming a non-doped poly-silicon layer on the gate electrode to fill up the recess through the oxide film; and a heat treatment process to oxidize and insulate the non-doped polysilicon layer.

9. The manufacturing method of a MOS-driven semiconductor device according to claim 7, wherein an interval of the trench is 0.2 micrometer or more and 0.8 micrometer or less.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional view of components of a MOS-driven semiconductor device according to a first embodiment of the present invention.

(2) FIG. 2 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to a second embodiment of the present invention.

(3) FIG. 3 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(4) FIG. 4 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(5) FIG. 5 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(6) FIG. 6 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(7) FIG. 7 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(8) FIG. 8 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(9) FIG. 9 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(10) FIG. 10 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(11) FIG. 11 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(12) FIG. 12 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(13) FIG. 13 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(14) FIG. 14 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(15) FIG. 15 is a cross-sectional view of a MOS-driven semiconductor device, depicting a manufacturing method according to the second embodiment of the present invention.

(16) FIG. 16 is a cross-sectional view of components of a MOS-driven semiconductor device according to a third embodiment of the present invention.

(17) FIG. 17 is a cross-sectional view of the MOS-driven semiconductor device, depicting a manufacturing method according to the third embodiment of the present invention.

(18) FIG. 18 is a cross-sectional view of components of a MOS-driven semiconductor device according to a fourth embodiment of the present invention.

(19) FIG. 19 is a cross-sectional view of the MOS-driven semiconductor device, depicting a manufacturing method according to the fourth embodiment of the present invention.

(20) FIG. 20 is a cross-sectional view of the MOS-driven semiconductor device, depicting a manufacturing method according to the fourth embodiment of the present invention.

(21) FIG. 21 is a cross-sectional view of components of a conventional power MOSFET.

(22) FIG. 22 is a cross-sectional view of a void generated in an interlayer insulating film.

(23) FIG. 23 is an electron microscope photograph of a silicon (Si) substrate viewed along a surface thereof.

(24) FIG. 24 is an electron microscope photograph of a silicon (Si) substrate viewed along a surface thereof.

DESCRIPTION OF EMBODIMENTS

(25) Preferred embodiments of a manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the embodiments and the accompanying drawings, identical structures are given identical reference numerals and redundant description is omitted. + and that are superscripts for n and p respectively mean that a layer or an area with + or has a higher impurity concentration or a lower impurity concentration than that of a layer or an area without a superscript. A first conducting type will be described as n type and a second conducting type will be described as p type.

(26) In the present invention, a poly-silicon layer that is formed being doped with an impurity source during deposition is referred to as a doped poly-silicon layer, and a poly-silicon layer that is formed being not doped with any impurity source during deposition is referred to as a non-doped poly-silicon layer. A non-doped poly-silicon layer that is doped with an impurity source after deposition is also referred to as a non-doped poly-silicon layer.

(27) (First Embodiment)

(28) FIG. 1 is a cross-sectional view of components of a MOS-driven semiconductor device according to a first embodiment of the present invention. As depicted in FIG. 1, a power MOSFET 100 of the present invention includes an n.sup. epitaxial layer (hereinafter, n.sup. epi layer) 2 that is disposed on an n.sup.+ semiconductor substrate 1; a p-channel layer 3 that is disposed on the n.sup. epi layer 2; trenches 7 that pass through the p-channel layer 3 to the n.sup. epi layer 2; n.sup.+ source layers 11 that are selectively disposed in surface layers of a side face and a top face of the p-channel layer 3; and p.sup.+ contact layers 14 that are disposed in a surface layer of the p-channel layer 3.

(29) The n.sup.+ semiconductor substrate 1 is an n.sup.+ drain layer. The n.sup.+ epi layer 2 is an n.sup. drift layer. The n.sup. epi layer 2 corresponds to the first semiconductor layer. The p-channel layer 3 is a p-base layer. Preferably, each interval between adjacent trenches 7 (hereinafter, trench interval A in FIG. 1) is 0.2 micrometer or wider and 0.8 micrometer or narrower. The reason for this will be described later. The n.sup.+ source layers 11 each have an L-shape that is disposed spanning from the top face of the p-channel layer 3 to the surface layer of a side face thereof. Each of the n.sup.+ source layers 11 corresponds to the second semiconductor layer.

(30) The p.sup.+ contact layers 14 each have an impurity concentration that is higher than that of the p-channel layer 3 and that is lower than that of the n.sup.+ source layers 11. The p.sup.+ contact layers 14 cover a lower area of the n.sup.+ source layers 11 that are selectively disposed in the surface layer in the top surface of the p-channel layer 3. The lower area of the n.sup.+ source layers 11 is an area on the n.sup.+ semiconductor substrate 1 side of the n.sup.+ source layers 11. Each of the p.sup.+ contact layers 14 corresponds to a third semiconductor layer.

(31) The power MOSFET 100 further includes gate insulating films (gate oxide films) 9 that are disposed on the inner wall of the trenches 7, respectively; gate electrodes 10a that are embedded in the trenches 7 through the gate insulating films 9; oxide films (CVD oxide films) 12 that are formed using a CVD method to be disposed on the gate electrode 10a and on the side wall of each of the trenches 7, and having a half-square-pipe shape; non-doped poly-silicon layers 13 that are disposed on of the CVD oxide films 12, respectively and that are not oxidized; a source electrode 15 that is disposed spanning across the n.sup.+ source layers 11, the p.sup.+ contact layers 14, and the non-doped poly-silicon layers 13; and a drain electrode 16 that is disposed on a back face of the n.sup.+ semiconductor substrate 1 that is the n.sup.+ drain layer. The source electrode 15 corresponds to the main electrode.

(32) Each boundary between the gate electrodes 10a and the CVD oxide films 12 is at a position that is closer to the n.sup.+ semiconductor substrate 1 than each boundary between the n.sup.+ source layers 11 and the source electrode 15. Each boundary between the gate electrodes 10a and the CVD oxide films 12 is also positioned between a lower area of the n.sup.+ source layers 11 disposed on the side wall of the p-channel layer 3 and the surface of the n.sup.+ source layers 11. In a vicinity of the surface of each of the gate electrodes 10a, the gate electrodes 10a and the n.sup.+ source layers 11 respectively disposed on a side wall of the p-channel layer 3 are adjacent to each other across each of the gate insulating films 9.

(33) The CVD oxide films 12 form a recess 18 at an upper portion of each of the trenches 7. The CVD oxide films 12 are made of Low Pressure TetraEthOxySilane (LP-TEOS) films or HTO films. Preferably, the thickness of the CVD oxide films is 0.1 micrometer or more and 0.3 micrometer or less. The reason for this is as follows. A breakdown voltage of 60 V can be secured between the gate and the source by setting the film thickness of the CVD oxide films 12 to be 0.1 micrometer or more. Generation of a void in the CVD oxide films 12 can be prevented by setting the thickness of the CVD oxide films 12 to be 0.3 micrometer or less.

(34) The non-doped poly-silicon layers 13 are disposed in the recesses 18 that are formed on the CVD oxide films 12 in the trenches 7, to fill gaps formed by the recesses 18 and the surfaces of the n.sup.+ source layers 11. Thereby, a void that is generated in the source electrode 15 by the gaps (the recesses 18) formed by the CVD oxide films 12 is suppressed. By suppressing this void, the bonding strength of wire bonded to the source electrode 15 may be prevented from getting weak. An increase in the resistance of the source electrode 15 caused by a void may be prevented.

(35) (Second Embodiment)

(36) FIGS. 2 to 15 are cross-sectional views of a MOS-driven semiconductor device, depicting a manufacturing method according to a second embodiment of the present invention. In FIGS. 2 to 15, the manufacturing method is depicted in order of processes. The manufacturing method of the MOS-driven semiconductor device depicted in FIG. 1 will be described herein using an n-channel MOSFET assuming the first conducting type to be n type.

(37) An n.sup. epitaxial layer (n.sup. epi layer) 2 having a resistivity of, for example, 1.0 Ohm*cm or less is formed on an n.sup.+ semiconductor substrate 1 to be used as a drain layer. The n.sup. epi layer 2 may be formed after forming on the n.sup.+ semiconductor substrate 1, an n.sup.+ buffer layer having a higher impurity concentration than that of the n.sup.+ semiconductor substrate 1. In an activated portion of the power MOSFET, an impurity is introduced from the surface of the n.sup. epi layer 2 and is diffused, thereby a p-channel layer 3 is formed. At this time, the p-channel layer 3 is formed such that the diffusion depth of the p-channel layer 3 is about 1.4 micrometer. The p-channel layer 3 is not formed in a guard ring portion (not depicted) that is a breakdown voltage structure portion of the power MOSFET. The thickness and the impurity concentration of the n.sup. epi layer 2 and the diffusion profile of the p-channel layer 3 are set according to the specification of the breakdown voltage and the ON-resistance of a device. A buffer oxide film 4 having a thickness of several 10 nm is formed on the entire surface of the n.sup. epi layer 2 (FIG. 2). The buffer oxide film 4 has a function of preventing the silicon surface such as that of the p-channel layer 3 from becoming rough at etching to pattern a nitride film formed on the surface of the buffer oxide film 4 at processes executed later.

(38) A nitride film 5 is deposited on the surface of the p-channel layer 3 through the buffer oxide film 4. The nitride film 5 is selectively etched using, for example, photo-resist, not depicted, as a mask and thereby, is patterned. Thereby, the nitride film 5 remains on the portions that are formed with p.sup.+ contact layers (FIG. 3). Photo-resist 6 is applied and patterning of the photo-resist 6 is executed to form openings therein on the areas to form trenches. Trenches 7 are formed by dry etching using the photo-resist 6 as a mask. Trench bottom portions 7a pass through the p-channel layer 3 to the n.sup. epi layer 2 (FIG. 4). The photo-resist 6 corresponds to a first mask.

(39) The width of each of the trenches 7 may be, for example, 1.0 micrometer or less. Preferably, each trench interval A is, for example, 0.2 micrometer or more and 0.8 micrometer or less. The reason for this is that, when each interval of the trenches is less than 0.2 micrometer, each of the intervals between the nitride film 5 that is patterned and an end of an opening of each of the trenches 7 (the width of the surface of the n.sup.+ source layer) is not secured to be sufficiently large and therefore, electrical contact between the n.sup.+ source layers 11 and a source electrode 15 becomes incomplete. The reason for each interval of the trenches to be 0.8 micrometer or less will be described later. The mask pattern width B in FIG. 3 is, for example, 0.1 micrometer or more and 0.7 micrometer or less. Here, the reason the patterned nitride film 5 is formed before formation of the trenches 7 is, if the patterned nitride film 5 is formed after formation of the trenches, the nitride film 5 is formed in the trenches also and complete removal of the nitride film 5 remaining in the trenches 7 is difficult.

(40) The photo-resist 6 used to form the trenches 7 is removed and the nitride film 5 is exposed. A sacrificial oxide film 8 is formed over the entire surface of the n.sup. epi layer 2 including the trench bottom portions 7a and trench side walls 7b. Thereby, a damaged layer produced during the formation of the trenches 7 is removed (FIG. 5). Thereafter, the sacrificial oxide film 8 is removed (FIG. 6). At this time, the buffer oxide film 4 that is exposed at the surface of the substrate is also removed together with the sacrificial oxide film 8, and the buffer oxide film 4 remains only beneath the nitride film 5. A gate insulating film (gate oxide film) 9 is formed over the entire surface of the n.sup. epi layer 2 including the trench bottom portions 7a and the trench side walls 7b (FIG. 7). A doped poly-silicon 10 is deposited such that the inside of each of the trenches 7 is completely filled (FIG. 8).

(41) The doped poly-silicon 10 is deposited on the entire surface of the n.sup. epi layer 2 that is formed thereon with the p-channel layer 3. An unnecessary portion of the doped poly-silicon 10 is removed by etching back and the remaining portions of the doped poly-silicon 10 are used as gate electrodes 10a. At this time, the etching back is executed until the surfaces of the gate electrodes 10a in the trenches 7 becomes deeper than the surface of the p-channel layer 3 by, for example, about 1 micrometer (FIG. 9). The surfaces of the gate electrodes 10a are used as a mask for forming the n.sup.+ source layers 11 at a later process. Therefore, the etching back is executed such that the surfaces of the gate electrodes 10a are positioned to be shallower than the diffusion depth of the p-channel layer 3.

(42) An impurity ion such as, for example, arsenic (As) is ion-implanted 20 in an oblique direction using these gate electrodes 10a and the nitride film 5 formed at the process depicted in FIG. 3, as a mask. This mask corresponds to a second mask. In this case, the ion implantation 20 may be executed at an accelerating voltage of about 80 KeV and with a dose of about *3*10.sup.15/cm.sup.2. The incidence angle of the oblique implantation of the ion implantation 20 may be 7 degrees or 40 degrees (FIG. 10). This incidence angle is an angle relative to a direction that is perpendicular to the silicon face. The ion implantation 20 is not limited to being obliquely executed and may be executed in a direction that is perpendicular to the silicon face. Because the n.sup.+ source layers 11 are formed using the gate electrodes 10a as a mask, the side face of each of the gate electrodes 10a assuredly overlap a side face of each of the n.sup.+ source layers 11. Thereby, a channel that is a path for electron to pass through may be formed in the p-channel layer 3 that is adjacent to the gate electrodes 10a across the gate insulating film 9. The width of the nitride film 5 is narrower than each trench interval A and therefore, the ion implantation 20 is also executed from the surface of the p-channel layer 3. Thereby, the n.sup.+ source layers 11 are each formed in an L-shape.

(43) The nitride film 5 is removed. A CVD oxide film 12 is deposited to be 0.1 micrometer or more and 0.3 micrometer or less thick (FIG. 11). In this deposition of the CVD oxide film 12, the CVD oxide film 12 is deposited such that a recess 18 remains at an upper portion of each of the trenches 7. For example, the depth from the upper end of each of the trenches 7 to the surface of each of the gate electrodes 10a before the deposition of the CVD oxide film 12 is about 1 micrometer. Therefore, even when the CVD oxide film 12 is deposited to be 0.1 micrometer to 0.3 micrometer thick, the recesses 18 remain on the CVD oxide films 12 in the trenches 7. Preferably, the CVD oxide film 12 is an oxide film that is made of an LP-TEOS film or an HTO film, and is formed using a thermal CVD method. The reason for this is as follows. For a plasma oxide film, charge is present in the film and adversely affects the reliability of the film such as variation of the threshold voltage. In contrast, for LT-TEOS film or HTO film, the amount of charge in the film is small compared to that of a plasma oxide film and therefore, the affect on the reliability of the film such as variation of the threshold voltage is not problematic. The temperature may be set to be at 700 degrees C. or higher and lower than 850 degrees C. and the time for the formation may be several 10 minutes, as formation conditions for depositing an LP-TEOS film or an HTO film. When the CVD oxide film 12 is deposited under these conditions, the diffusion profile of each of the n.sup.+ source layers 11 is not significantly affected. The formation of the LP-TEOS film is executed under a reduced pressure of several 10 Torr.

(44) A non-doped poly-silicon layer 13 that is not doped with any impurity source is deposited and the recesses 18 are filled (FIG. 12). The reason a doped poly-silicon layer that is formed being doped with an impurity source is not deposited but rather the non-doped poly-silicon layer is deposited, is that a doped poly-silicon layer introduces therein an impurity gas during the deposition and therefore, an impurity from the gas becomes movable charge and degradation of the reliability such as variation of a threshold voltage tends to occur.

(45) The non-doped poly-silicon layer 13 is etched back and the CVD oxide film 12 that is formed at the surface of the p-channel layer 3 is exposed (FIG. 13). The non-doped poly-silicon layer 13 only remains in the recesses 18. No heat treatment to oxidize the non-doped poly-silicon layer 13 is executed. The CVD oxide film 12 that is exposed is etched back. The surface of the non-doped poly-silicon layer 13 is further etched to planarize the surface of the semiconductor substrate (FIG. 14).

(46) To form a p.sup.+ contact layer 14 on the surface of the p-channel layer 3, an impurity ion such as, for example, boron (B) is ion-implanted into the surface of the semiconductor substrate. The p.sup.+ contact layer 14 is formed to have an impurity concentration that is higher than that of the p-channel layer 3 and that is lower than that of the n.sup.+ source layers 11. The accelerating voltage of the ion implantation may be about 50 KeV and the dose thereof may be about 2*10.sup.14/cm.sup.2. Alternatively, boron fluoride (BF.sub.2) ion may be implanted at an accelerating voltage of about 50 keV and with a dose of about 1*10.sup.15/cm.sup.2. Due to this ion implantation, ion is also implanted into areas of the n.sup.+ source layers 11 to form the p.sup.+ contact layer 14. However, the total amount of the impurity in the n.sup.+ source layers 11 is greater compared to the amount of p-type impurity ion implanted thereinto and therefore, the resistance of the n.sup.+ source layer 11 is not increased. Due to this ion implantation, ion to form the p.sup.+ contact layer 14 is also implanted into the non-doped poly-silicon layer 13. However, differing from the areas in the surface of the semiconductor substrate such as the n.sup.+ source layers 11, ion is implanted only into a shallow area having a depth of, for example, 0.15 micrometer or less of the surface layer.

(47) The ion that is implanted by the ion implantation is activated. The activation of the ion is executed by lamp annealing for several minutes at a heat treatment temperature of 900 degrees C. in a nitrogen gas (N.sub.2) atmosphere. The arsenic ion in the n.sup.+ source layers 11 is also simultaneously activated by this annealing. The ion that is ion-implanted into the surface layer of the non-doped poly-silicon layer 13 is also activated by this annealing (FIG. 15). The impurity source is doped into the surface layer of the non-doped poly-silicon layer 13 by this annealing. However, after depositing the non-doped poly-silicon layer 13, the impurity doped into the surface layer thereof becomes fixed charge. Therefore, the probability that movable ion is generated in an interlayer insulating film is very low compared to that of the doped poly-silicon. Even when ion implantation to form the p.sup.+ contact layer 14 is executed for the entire non-doped poly-silicon layer 13, movable ion is hardly generated. As a result, even in a case where an impurity source is doped in the non-doped poly-silicon layer 13 that is not doped with any impurity source when deposited, after the deposition thereof, adverse effects on the reliability of the non-doped poly-silicon layer 13 such as variation of the threshold value are slight. In processes thereafter, no annealing process in an oxidizing atmosphere is executed and therefore, the non-doped poly-silicon layer 13 is not oxidized. No annealing at 850 degrees C. or higher is executed in processes after this lamp annealing.

(48) A source electrode 15 is formed on the surface of the p-channel layer 3. A drain electrode 16 is formed on the back face of the n.sup.+ semiconductor substrate 1 after a back-wrapping process (FIG. 1). A protective film not depicted is deposited on a source pad area not depicted and the surface of the n.sup. epi layer 2 excluding gate pad areas and thereby, the power MOSFET depicted in FIG. 1 is completed.

(49) (Third Embodiment)

(50) FIG. 16 is a cross-sectional view of components of a MOS-driven semiconductor device according to a third embodiment. FIG. 17 is a cross-sectional view of the MOS-driven semiconductor device, depicting a manufacturing method according to the third embodiment of the present invention. In the first embodiment, the n.sup.+ source layers 11 may be disposed only in the surface layers of side faces of the p-channel layer 3. In the second embodiment, the trenches 7 may be formed using a silicon oxide film 26 as a mask instead of the photo-resist 6 that is used as the first mask.

(51) As depicted in FIG. 16, in the third embodiment, n.sup.+ source layers 21 are disposed in the surface layer of the side faces of the p-channel layer 3 and each have an I-shape. The p.sup.+ contact layers 14 are selectively disposed in the surface layer of the upper face of the p-channel layer 3 and are each in contact with the n.sup.+ source layers 21. Other structures are same as those in the first embodiment (see FIG. 1).

(52) A manufacturing method of the MOS-driven semiconductor device depicted in FIG. 16 will be described. The n.sup. epi layer 2 and the p-channel layer 3 are first formed on the n.sup.+ semiconductor substrate 1 similarly to the second embodiment (see FIGS. 1 and 2). As depicted in FIG. 17, a silicon oxide film 26 is formed instead of the photo-resist 6 (see FIG. 4) that is formed in the second embodiment. The trenches 7 are formed using the silicon oxide film 26 as a mask. In the third embodiment, the nitride film 5 is not formed. The silicon oxide film 26 corresponds to the first mask. Similarly to the second embodiment, after the damaged layer produced when the trenches 7 are formed is removed using the sacrificial oxide film 8, the sacrificial oxide film 8 is removed (see FIGS. 5 and 6). In this case, the silicon oxide film 26 is not removed. Similarly to the second embodiment, after the gate insulating film 9 is formed, the trenches 7 are filled with the doped poly-silicon 10 and the doped poly-silicon 10 is etched back to be the gate electrodes 10a (see FIGS. 7 to 9).

(53) Arsenic (As) is ion-implanted using the silicon oxide film 26 and the gate electrodes 10a as a mask. In this ion implantation, the ion implantation is only executed for the side face of each of the trenches. At this time, ion implantation is executed using at least the gate electrodes 10a as a mask. The gate electrodes 10a correspond to the second mask. Thereafter, the silicon oxide film 26 is removed by wet etching and, similarly to the second embodiment, the CVD oxide film 12 is formed such that the recesses 18 remain (see FIG. 11).

(54) Similarly to the second embodiment, the recesses 18 are filled with the non-doped poly-silicon layer 13. Similarly to the second embodiment, the non-doped poly-silicon layer 13 and the CVD oxide film 12 are sequentially etched back. Thereafter, the non-doped poly-silicon layer 13 is etched and thereby, the surface of the semiconductor substrate is planarized (see FIGS. 12 to 14).

(55) Similarly to the second embodiment, boron fluoride (BF.sub.2) is ion-implanted into the entire surface of the p-channel layer 3 that includes the CVD oxide film 12 and the non-doped poly-silicon layer 13 and annealing is executed. Thereby, arsenic and boron that are ion-implanted are activated and n.sup.+ source layers 21 and the p.sup.+ contact layer 14 are formed (FIG. 15). The source electrode 15 is formed on the surface of the p-channel layer 3, and the drain electrode 16 is formed on the back side of the n.sup.+ semiconductor substrate 1 after a back-wrapping process. Thereby, the power MOSFET depicted in FIG. 16 is completed.

(56) Other manufacturing methods are same as that of the second embodiment. The above manufacturing method is a manufacturing method obtained by partially changing the second embodiment, and the same processes as those of the second embodiment may be executed similarly to those of the second embodiment.

(57) As described, even when the ion implantation to form the n.sup.+ source layer 21 is only executed for each trench side wall, the recesses 18 are formed on the gate electrodes 10a and the non-doped poly-silicon layer 13 is formed to fill the recesses 18. In addition, the non-doped poly-silicon layer 13 is not oxidized. Thereby, the profile of each of the diffusion layers, such as the n.sup.+ source layer 21, is not varied. By filling the recesses 18 of the trenches 7 with the non-doped poly-silicon layer 13, generation of a void in the source electrode 15 can be prevented.

(58) (Fourth Embodiment)

(59) FIG. 18 is a cross-sectional view of components of a MOS-driven semiconductor device according to a fourth embodiment of the present invention. FIGS. 19 and 20 are cross-sectional views of the MOS-driven semiconductor device, depicting a manufacturing method according to the fourth embodiment of the present invention. In the first embodiment, an insulating layer 24 that is formed by oxidizing a non-doped poly-silicon layer may be formed instead of the non-doped poly-silicon layer 13 that is not oxidized. In the second embodiment, the insulating layer 24 may be formed by depositing a non-doped poly-silicon layer as a filler 23 on the CVD oxide film 12 and oxidizing the non-doped poly-silicon layer instead of the process of forming the non-doped poly-silicon layer 13 on the CVD oxide film 12.

(60) In the fourth embodiment, as depicted in FIG. 18, the inside of each of the recesses is filled with the insulating layer 24. Other structures are same as those in the first embodiment (see FIG. 1).

(61) A manufacturing method of such a MOS-driven semiconductor device will be described. Similarly to the second embodiment, the n.sup. epi layer 2, the p-channel layer 3, the trenches 7, the gate insulating films 9, the gate electrodes 10a, the n.sup.+ source layers 11, the CVD oxide films 12, the recesses 18, and a non-doped poly-silicon layer are formed on the n.sup.+ semiconductor substrate 1 (see FIGS. 2 to 12). In this case, the non-doped poly-silicon layer is the fillers 23 that fill the recesses 18.

(62) As depicted in FIG. 19, the fillers 23 and the CVD oxide film 12 are etched back similarly to that of the second embodiment and thereby, the surface of the semiconductor substrate is planarized. Thereafter, as depicted in FIG. 20, the fillers 23 are oxidized to be the insulating layer 24. In this case, the fillers 23 are polished by chemical mechanical polishing (CMP) using the CVD oxide film 12 as a stopper. The insulating layers 24 are formed by oxidizing the fillers 23. The surface of the semiconductor substrate is planarized by etching back the insulating layers 24 and the CVD oxide film 12. Processes to be executed thereafter are executed similarly to those of the second embodiment and thereby, the power MOSFET depicted in FIG. 18 is completed.

(63) Other manufacturing methods are same as the second embodiment. The above manufacturing method is a manufacturing method obtained by partially changing the second embodiment and the processes that are same as those of the second embodiment may be executed similarly to those of the second embodiment.

(64) In the fourth embodiment, the n.sup.+ source layers 11 are formed using the nitride film 5 as a mask and thereby, the n.sup.+ source layers 11 may be formed assuredly on the planar surface of the p-channel layer 3. As a result, the n.sup.+ source layers 11 may be brought into stable electrical contact with the source electrode 15. In a power-MOSFET that employs fine cells whose trench intervals A each are 0.8 micrometer or less, the n.sup.+ source layers 11 and the source electrode 15 may be assuredly in electrical contact with each other. A trench interval A that is less than 0.2 micrometer is currently the limit for manufacturing apparatuses and therefore, it is desirable that the trench interval A is 0.2 micrometer or wider.

(65) In the fourth embodiment, a process of forming the non-doped poly-silicon layer as the fillers 23 and oxidizing the non-doped poly-silicon layer is added. Because the profile of each of the n.sup.+ source layers 11 is varied due to this process, preferably, the MOSFET is designed taking into account in advance the effect of the variation. To eliminate the effect on the profile of each of the n.sup.+ source layers 11, preferably, the relation between, for example, the lateral diffusion width of each of the n.sup.+ source layers 11 and the trench interval A is understood before the design of the MOSFET.

(66) As described, in the fourth embodiment, the process of oxidizing the non-doped poly-silicon layer is added compared to the first embodiment. Therefore, to oxidize the non-doped poly-silicon layer, design of the MOSFET that takes into account the influence on the profile is necessary. However, as described, the n.sup.+ source layers 11 may be formed assuredly on the planar surface of the p-channel layer 3 similarly to the first embodiment. As a result, the n.sup.+ source layers 11 can be brought into stable electrical contact with the source electrode 15.

EXAMPLE

(67) The state of the nitride film that was formed as the mask to be used to form the n.sup.+ source layers was observed. FIGS. 23 and 24 are electron microscope photographs of a silicon (Si) substrate viewed along a surface thereof. A scanning electron microscope (SEM) was used to observe the silicon substrate. On the silicon substrate 70 depicted in FIG. 23, trenches 72 were formed according to the above embodiments after a nitride film 71 was formed as a mask to be used to form the n.sup.+ source layers (hereinafter, example). The trench interval A was 0.8 micrometer. The mask pattern width was 0.5 micrometer. For comparison, on the silicon substrate 80 depicted in FIG. 24, trenches 82 were formed similarly to the example after a photo-resist 81 was formed as the mask to be used to form the n.sup.+ source layers (hereinafter, comparative example). In the comparative example, the photo-resist was a single layer of an organic material. An anti-reflection film that prevents the reflection of light from, for example, the silicon face was not formed. Other conditions were same as those of the example.

(68) From the result depicted in FIG. 24, the side wall pattern of the photo-resist 81 running parallel to the trenches 82 was not a straight line in the comparative example that used the photo-resist 81. The pattern was drawn on a photo mask into a pattern having a constant mask pattern width. However, irregularity occurred to the mask pattern width after patterning due to an influence of halation. The influence of the halation became stronger and dispersion in the processing of the patterning became more conspicuous as the trench interval A became narrower.

(69) In contrast, from the result depicted in FIG. 23, in the example that used the nitride film 71 as the mask, no irregularity occurred to the mask pattern width after the processing and the problem arising when the photo-resist was used as above could be solved. As described, when the trench interval A was 0.8 micrometer, it was found that occurrence of the irregularity to the mask pattern width of the nitride film 71 after the trenches were formed could be prevented. Similarly, even when the trench interval A was narrower than 0.8 micrometer, the nitride film 71 could be patterned.

(70) As described, according to the first to the fourth embodiments, effects described in the following (1) to (3) are achieved. (1) The nitride film 5 having openings that correspond to areas to form the n.sup.+ source layers 11 is formed as a mask (to be used to form the n.sup.+ source layers 11 before the trenches 7 are formed. The width of the mask is set to be a width that is narrower than the interval between adjacent trenches 7 (trench interval A). The n.sup.+ source layers 11 are formed using, as a mask, the nitride film 5 and the gate electrodes 10a that are formed in the trenches 7. Thereby, the n.sup.+ source layers 11 may be formed assuredly on the planar surface of the p-channel layer 3. As a result, the n.sup.+ source layers 11 can be brought into stable electrical contact with the source electrode 15. The n.sup.+ source layers 11 and the source electrode 15 can be assuredly in electrical contact with each other even in a power MOSFET that employs fine cells whose trench interval A is narrower than 0.8 micrometer. It is desirable that the trench interval A is 0.2 micrometer or wider.

(71) (2) The thickness of the CVD oxide film 12 is set to be 0.1 micrometer or more and 0.3 micrometer or less. The thickness of the CVD oxide film 12 that is immediately beneath the non-doped poly-silicon layer 13 is set to be 0.1 micrometer or more. Thereby, the breakdown voltage between the gate and the source is set to be 60 V. Therefore, the non-doped poly-silicon layer 13 does not need to be oxidized to secure the breakdown voltage. The breakdown voltage of the CVD oxide film 12 is at least 6 MV/cm and therefore, the breakdown voltage is 60 V when the film thickness is 0.1 micrometer or more. The rated voltage between the gate and the source of a device is at highest 20 V. Therefore, when a breakdown voltage of 60 V is secured, the gate and the source are not short-circuited therebetween by a surge voltage. By setting the thickness of the CVD oxide film 12 to be 0.3 micrometer or less, generation of a void in the CVD oxide film 12 can be suppressed.

(72) (3) By not oxidizing the non-doped poly-silicon layer 13, the profile of each of the diffusion layers such as the n.sup.+ source layers 11 is not varied. By filling the recesses 18 of the trenches 7 with the non-doped poly-silicon layer 13, generation of a void in the source electrode 15 can be prevented.

(73) The present invention has been described herein taking an example of the power MOSFET. However, the present invention may also be applied to a MOS-driven semiconductor device such as an insulated gate bipolar transistor (IGBT) obtained by replacing the n.sup.+ semiconductor substrate with a p.sup.+ semiconductor substrate and using the n.sup.+ source layers 11 as the n.sup.+ emitter layers in the embodiments. The MOS-driven semiconductor device may be a p-channel semiconductor apparatus whose conducting types are inversed to be the p and the n types respectively as the first and the second conducting types. The recesses are formed by the oxide film formed using the CVD method (CVD oxide film). However, not only the CVD oxide film but also an oxide film that is formed not to include any impurity may be used.

INDUSTRIAL APPLICABILITY

(74) As described, the MOS-driven semiconductor device and the method for manufacturing the MOS-driven semiconductor device according to the present invention are suitable for a semiconductor apparatus that has a trench structure.

REFERENCE SIGNS LIST

(75) 1 n.sup.+ semiconductor substrate 2 n.sup. epi layer (n.sup. epitaxial layer) 3 p-channel layer 4 buffer oxide film 5 nitride film 6 photo-resist 7 trench 7a trench bottom portion 7b trench side wall 8 sacrificial oxide film 9 gate insulating film 10 doped poly silicon 10a gate electrode 11 n.sup.+ source layer 12 CVD oxide film 13 non-doped poly-silicon layer 14 p.sup.+ contact layer 15 source electrode 16 drain electrode 18 recess