GATE WITH SELF-ALIGNED LEDGE FOR ENHANCEMENT MODE GaN TRANSISTORS

Abstract

An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Claims

1. An enhancement-mode GaN transistor, comprising: a GaN layer; a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer; a p-type gate material formed above the barrier layer, the p-type gate material having side surfaces extending towards the barrier layer; and a gate metal disposed on the p-type gate material, the gate metal having sidewalls extending towards the p-type gate material, wherein the p-type gate material comprises a pair of horizontal ledges that extend past the respective sidewalls of the gate metal, the pair of horizontal edges having substantially equal widths from the sidewalls of the gate metal to the side surfaces of the p-type gate material, respectively.

2. The enhancement-mode GaN transistor according to claim 1, further comprising a source contact and a drain contact disposed on the barrier layer.

3. The enhancement-mode GaN transistor according to claim 2, wherein the pair of horizontal ledges of the p-type gate material extend toward the source contact and drain contact, respectively.

4. The enhancement-mode GaN transistor according to claim 3, wherein the side surfaces of the p-type gate material extend horizontally towards the source contact and drain contact, respectively, and contact the barrier layer.

5. The enhancement-mode GaN transistor according to claim 1, wherein the pair of horizontal ledges of the p-type gate material are self-aligned.

6. The enhancement-mode GaN transistor according to claim 1, wherein the barrier layer comprises aluminum gallium nitride (AlGaN).

7. The enhancement-mode GaN transistor according to claim 1, wherein the p-type gate material has a first width between the side surfaces of the p-type gate material and the gate metal has a second width between sidewalls of the gate metal, the second width being less than the first width.

8. An enhancement-mode GaN transistor, comprising: a GaN layer; a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer; a source contact and a drain contact disposed on the barrier layer; a p-type gate material formed above the barrier layer and between the source and drain contacts; and a gate metal disposed on the p-type gate material, wherein the p-type gate material comprises a pair of self-aligned ledges that extend past sidewalls of the gate metal towards the source contact and drain contact, respectively.

9. The enhancement-mode GaN transistor according to claim 8, wherein the p-type gate material further comprises side surfaces extending horizontally towards the source contact and drain contact, respectively, and contacting the barrier layer.

10. The enhancement-mode GaN transistor according to claim 8, wherein the barrier layer comprises aluminum gallium nitride (AlGaN).

11. The enhancement-mode GaN transistor according to claim 8, wherein the pair of self-aligned ledges are symmetric with respect to the gate metal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

[0013] FIG. 1 illustrates a schematic of a conventional enhancement-mode GaN transistor.

[0014] FIG. 2 illustrates a schematic diagram of two gate leakage current paths of a conventional enhancement-mode GaN transistor.

[0015] FIG. 3A illustrates a schematic diagram of test structure of an enhancement-mode GaN transistor.

[0016] FIG. 3B illustrates a schematic diagram of test structure of another enhancement-mode GaN transistor.

[0017] FIG. 4 illustrate a graphical comparison of the gate leakage currents of structures shown in FIGS. 3A and 3B.

[0018] FIG. 5 illustrates a schematic diagram of a transistor device according to an exemplary embodiment of the present invention.

[0019] FIGS. 6A-6C illustrates a fabrication process to manufacture a gate of a transistor device with self-aligned ledges according to an exemplary embodiment.

[0020] FIG. 7A illustrates a cross-sectional image of a conventional gate structure without a ledge.

[0021] FIG. 7B illustrates a cross-sectional image of a gate structure with a self-aligned ledge according to an exemplary embodiment.

[0022] FIG. 8 illustrates a graphical comparison of gate leakage current of the gate structures illustrated in FIGS. 7A and 7B.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0023] In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.

[0024] FIG. 5 illustrates a schematic diagram of a transistor device according to an exemplary embodiment of the present invention. As shown, the transistor includes a source metal 510 (i.e., source contact) and a drain metal 512 (i.e., drain contact) with a gate contact disposed between the source and drain metals. In particular, a GaN base layer 501 is provided with a barrier layer 502 formed over the GaN base layer 501 and a two dimensional electron gas (2DEG) region formed at the interface between the GaN base layer and the barrier layer 502. In the exemplary embodiment, the barrier layer 502 is formed from aluminum gallium nitride (AlGaN).

[0025] As further shown, the gate contact includes a p-type gate material 503 formed on the barrier layer 502 and includes ledges 506 that are created by a self-aligned process at the top corners of the p-type gate material 503 as will be discussed in detail below. A gate metal 504 is disposed over the p-type gate material 503. As shown, the gate metal 504 has a smaller width (i.e., the width between sidewalls of the gate metal 504) than the width of the p-type gate material 503 (i.e., the width between side surfaces of the p-type gate material 503), effectively forming the pair of horizontal ledges 506 on each side of the gate metal 504. The pair of ledges 506 that extend past sidewalls of the gate metal 504 have equal or substantially equal widths, i.e., the respective ledges are symmetric from the respective sidewalls of the gate metal to the side surfaces of the p-type gate material, which is due to the self-aligned manufacturing process.

[0026] The primary benefits of using a self-aligned manufacturing process is to: (1) enable the creation of a p-type gate with a minimum critical dimension (CD), (2) lower processing cost because a second mask is not required, and (3) create ledges 506 that are symmetric to the gate metal 504 disposed on the p-type gate material. As indicated by the arrows (denoted by reference numbers 505) shown on ledges 506 and the side surfaces of the p-type gate material 503, when a positive voltage V.sub.g is applied to the gate metal 504, the gate current path 505 first travels horizontally along the upper edge of the p-type gate material 503 and, once it reaches the ledges 506, the current path 505 follows the diagonal path along the edge of the p-type gate material 503. This structure results in reduced gate leakage current as discussed below with respect to FIG. 8.

[0027] FIGS. 6A-6C illustrate a manufacturing process for fabricating a gate with self-aligned ledges in accordance with an exemplary embodiment of the present invention. As shown in FIG. 6A, the base structure of the device is first formed with a base layer 601 of gallium nitride (GaN), a barrier layer 602 of aluminum gallium nitride (AlGaN) formed on the GaN layer 601, and a layer of p-type gate material 603 formed on the barrier layer 502, over which the gate metal 604 is deposited.

[0028] Next, as shown in FIG. 6B, a photoresist 605 is deposited and the gate metal 604 is then etched. The p-type gate material 603 is also etched in a manner that results in the gate structure depicted in FIG. 6B. As shown in FIG. 6C, the gate metal 604 is then etched isotropically, which results in the gate metal have a width less than the planar upper surface of the p-type gate material 603. This second etching step results in the formation of the ledges 506 of the p-type gate material 603.

[0029] Finally, the manufacturing process includes a step of removing the photoresist 605, which is not shown, and results in the gate with self-aligned ledge shown in FIG. 5. It should also be appreciated that contact metals for the drain and source contacts can be separately deposited using conventional fabrication techniques, but their formation will not be described herein so as to not unnecessarily obscure the aspects of the invention.

[0030] FIGS. 7A-7B illustrate a transmission electron microscopy (TEM) image of a cross-sectional view of a conventional transistor gate and an x-ray of a cross-sectional view of a gate with a self-aligned ledge according to the exemplary embodiment disclosed herein. FIG. 8 illustrates a graph comparing the gate leakage current of the present invention (shown in FIG. 7B) with the gate leakage current of a conventional transistor (shown in FIG. 7A). As can be clearly seen in FIG. 8, the gate with self-aligned ledges has significantly lower gate leakage current than conventional gates without ledges when the transistor device is in the ON state.

[0031] Finally, it is noted that the self-aligned process illustrated in FIGS. 6A-6C is vastly superior to forming gate ledges using separate masks. In the process of using separate masks, a photoresist mask is applied to the unetched structure after the p-type gate material is deposited on the barrier layer of the device. In this instance, the first mask is used to pattern and etch the gate metal to a minimum CD. A second mask is then used to pattern and etch the p-type material with a wider CD than the gate metal. One significant disadvantage of this two mask process is the possibility of misalignment between the gate metal and the p-type gate material.

[0032] The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.