Optical sensor

Abstract

An optical sensor, especially an artificial retina, that includes at least one photosensitive cell. Each cell includes a integration capacitor, a read circuit the operation of which depends on the charge of the integration capacitor, at least one MOS transistor operating subthreshold, and the drain-source current of which influences the charge on the integration capacitor, and at least one photodiode operating in photovoltaic mode and connected to the gate of this transistor, such that the drain-source current of the MOS transistor depends on the optical power received by the photodiode.

Claims

1. An optical sensor comprising at least one photosensitive cell, each cell including: an integration capacitor, a read circuit the operation of which depends on the charge on the integration capacitor, at least one MOS transistor operating subthreshold, and the drain-source current of which influences the charge on the integration capacitor, at least one photodiode operating in photovoltaic mode, wherein the photodiode is (a) forward biased or operating with a positive voltage across its anode-cathode (PN) junction and (b) connected to the gate of this transistor, such that the drain-source current of the MOS transistor depends on the optical power received by the photodiode.

2. The optical sensor according to claim 1, the transistor being an activation transistor arranged to charge the integration capacitor when the photodiode connected to its gate is illuminated.

3. The optical sensor according to claim 2, the activation transistor being of PMOS type.

4. The optical sensor according to claim 1, the transistor being a deactivation transistor arranged to discharge the integration capacitor when the photodiode connected to its gate is illuminated.

5. The optical sensor according to claim 4, the deactivation transistor being of NMOS type.

6. The optical sensor according to claim 1, the cell including a plurality of activation transistors mounted in parallel and each controlled by one photodiode connected to a respective gate and operating in photovoltaic mode, each activation transistor being arranged to charge the integration capacitor when the photodiode is illuminated.

7. The optical sensor according to claim 1, the cell including a plurality of deactivation transistors mounted in parallel and each controlled by one photodiode connected to a respective gate and operating in photovoltaic mode, each deactivation transistor being arranged to discharge the integration capacitor when the photodiode is illuminated.

8. The optical sensor according to claim 1, the cell including: at least one MOS activation transistor, operating subthreshold, and the drain-source current of which influences the charge on the integration capacitor, at least one photodiode operating in photovoltaic mode and connected to the gate of this activation transistor, such that the drain-source current depends on the optical power received by the photodiode, the activation transistor being arranged to charge the integration capacitor when the photodiode is illuminated, at least one MOS deactivation transistor, operating subthreshold, and the drain-source current of which influences the charge on the integration capacitor, and at least one photodiode operating in photovoltaic mode and connected to the gate of this deactivation transistor, such that the drain-source current depends on the optical power received by the photodiode, the deactivation transistor being arranged to discharge the integration capacitor when the photodiode is illuminated.

9. The optical sensor according to claim 8, the cell being of “ON” type, including a plurality of deactivation transistors and associated photodiodes, the photodiode associated with the activation transistor being surrounded by the photodiodes associated with the deactivation transistors.

10. The optical sensor according to claim 8, the cell being of “OFF” type, including a plurality of activation transistors and associated photodiodes, the photodiode associated with the deactivation transistor being surrounded by the photodiodes associated with the activation transistors.

11. The optical sensor according to claim 9, the photodiodes associated with the deactivation transistors in the case of an “ON” cell or the photodiodes associated with the activation transistors in the case of an “OFF” cell, being arranged in a polygonal grid.

12. The optical sensor according to claim 1, including a stand-alone electrical power source.

13. The optical sensor according to claim 12, the stand-alone electrical power source including a plurality of photodiodes placed around a matrix of photosensitive cells or distributed between the photosensitive cells.

14. The optical sensor according to claim 1, the read circuit including at least one artificial neuron.

15. The optical sensor according to claim 14, the artificial neuron generating spikes at a frequency that depends on the optical power received by at least one photodiode.

16. The optical sensor according to claim 14, the artificial neuron including: an external synaptic current input defined by a terminal of the integration capacitor and which performs the algebraic sum of the activation and deactivation currents, a negative-feedback spiking circuit, including: a bridge comprising PMOS and NMOS transistors in series and the drains of which are connected by a midpoint to the integration capacitor, this midpoint defining the output of the artificial neuron, at least one so-called delay capacitor between the gate and the source of one of the transistors of the bridge, only two CMOS inverters in cascade, each consisting of two transistors, the input of the first inverter being connected to the integration capacitor and its output to the input of the second inverter and to the gate of one of the transistors of the bridge, the output of the second inverter being connected to the gate of the other transistor of the bridge, or only three CMOS inverters, two inverters of which are in cascade, each consisting of two transistors, the input of the first inverter being connected to the integration capacitor and its output to the input of the second inverter, the output of the second inverter being connected to the gate of one of the transistors of said bridge, the input of the third CMOS inverter being connected to the integration capacitor and the output of the third CMOS inverter being connected to the gate of the other transistor of said bridge.

17. The optical sensor according to claim 1, each photosensitive cell including a plurality of photodiodes and associated transistors, forming as many pixels of the sensor, and a single read circuit per cell.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will possibly be better understood on reading the following detailed description of nonlimiting examples of implementation thereof, and on examining the appended drawing, in which:

(2) FIGS. 1 and 2 are schematic representations of a sensor according to the invention;

(3) FIG. 3 illustrates an example of adjustment of synaptic weight in the case of a photodiode associated with a transistor operating subthreshold by way of excitatory synapse;

(4) FIG. 4 shows an elementary association of an activating transistor and a deactivating transistor within a sensor according to the invention;

(5) FIGS. 5 and 6 illustrate the implementation of an ON cell and of an OFF cell, respectively;

(6) FIGS. 7 and 8 are matrix representations of an ON or OFF cell showing a central pixel and its neighbours, in a rectangular grid and hexagonal grid arrangement, respectively;

(7) FIG. 9 illustrates an example of control of the frequency of the spikes depending on the optical power received by a certain number of pixels;

(8) FIGS. 10 and 11 show the arrangement of a photovoltaic power supply external to or integrated into the sensor, respectively;

(9) FIG. 12 illustrates an example of an integrated photovoltaic power supply; and

(10) FIGS. 13 and 14 show structural examples of an artificial neuron comprising two inverters and three inverters, respectively.

DETAILED DESCRIPTION

(11) FIGS. 1 and 2 schematically show an optical sensor 1 according to the invention. Such a sensor may include, as illustrated, a PMOS transistor 3, a photodiode 2, an integration capacitor C.sub.m and a read circuit 10.

(12) In FIG. 1, the photodiode 2 is connected to the gate of the transistor 3 by its cathode, its anode being connected to the supply voltage V.sub.dd. The drain of the transistor 3 is connected to a terminal of the integration capacitor C.sub.m also forming an input-output of the read circuit 10.

(13) The photodiode 2 operates in open-circuit photovoltaic mode in which the voltage across its terminals is strictly positive, V.sub.co>0, and the current flowing through it is zero. In this mode, the photodiode is capable of generating power, contrary to the usual mode (receiver mode) in which the photodiode is reverse biased.

(14) The transistor 3 operates subthreshold, and the drain current in the latter varies exponentially with the gate-source voltage, and therefore with the open-circuit voltage of the photodiode 2. The transistor 3 operating subthreshold is comparable to an excitatory synapse.

(15) From the current-voltage relationship of the PMOS transistor, a relationship between the open-circuit voltage V.sub.c0 generated by the photodiode and the current I.sub.ds output by the transistor is obtained:

(16) $\begin{array}{cc}{I}_{\mathrm{ds}}=G_p.Math.\exp \left(-\frac{V_{\mathrm{gs}}}{\eta .Math.V_t}\right).Math.\left(V_{\mathrm{dd}}-V_m\right)=G_p.Math.\exp \left(\frac{V_{\mathrm{CO}}}{\eta .Math.V_t}\right).Math.\left(V_{\mathrm{dd}}-V_m\right)& \left(1\right)\end{array}$

(17) In equation (1), G.sub.p is the conductance of the transistor, η is the ideality factor of the current-voltage characteristic I.sub.ds(V.sub.gs) of the transistor and V.sub.m is the voltage across the terminals of the capacitor such as shown.

(18) The cathode of the photodiode is connected to the gate of the PMOS transistor. This de facto means that the total current I of the photodiode, which is given by the following expression, will be zero:

(19) $\begin{array}{cc}I=I_s\left(\exp \left(\frac{V}{n{V}_t}\right)-1\right)-I_{ph}& \left(2\right)\end{array}$

(20) where V.sub.t=kT/q is the thermal voltage, I.sub.s is the saturation current of the PN junction forming the photodiode and I.sub.ph the photocurrent generated by the photodiode, which current is defined by:

(21) $\begin{array}{cc}{I}_{\mathrm{ph}}=\frac{{\mathrm{qQP}}_{\mathrm{opt}}}{\mathrm{hv}}& \left(3\right)\end{array}$

(22) where q is the charge on an electron, h Planck's constant, ν the frequency of the optical signal, Q the quantum efficiency and P.sub.opt optical power.

(23) As a result, the illumination produces an open-circuit photovoltaic voltage V.sub.co that may be expressed thus:

(24) $\begin{array}{cc}{V}_{\mathrm{co}}={\mathrm{nV}}_t.Math.\mathrm{Ln}\left(1+\frac{I_{\mathrm{ph}}}{I_s}\right)& \left(4\right)\end{array}$

(25) where n is the ideality factor of the voltage-current characteristic of the photodiode.

(26) Inserting (4) into (1), the following is obtained:

(27) $\begin{array}{cc}{I}_{\mathrm{ds}}=G_p.Math.{\left(1+\frac{I_{\mathrm{ph}}}{I_S}\right)}^{\frac{n}{\eta }}.Math.\left(V_{\mathrm{dd}}-V_m\right)& \left(5\right)\end{array}$

(28) Assuming that the ideality factors n and η are of the same order of magnitude, the expression of the drain-source current of the transistor 3 that influences the charge on the integration capacitor C.sub.m is obtained:

(29) $\begin{array}{cc}{I}_{ds}=G_p.\left(1+\frac{I_{ph}}{I_S}\right)\left(V_{dd}-V_m\right)& \left(6\right)\end{array}$

(30) In the most frequent case, the photo-current I.sub.ph is much larger than the reverse current I.sub.s of the unbiased junction. Thus:

(31) $\begin{array}{cc}{I}_{ds}=\frac{G_{\rho }}{I_s}.Math.I_{\mathrm{ph}}.Math.\left(V_{\mathrm{dd}}-V_m\right)& \left(7\right)\end{array}$

(32) A substantially linear relationship between the drain-source current and the photocurrent, and therefore between the drain-source current and the received optical power, is thus obtained.

(33) In FIG. 2, the photodiode 2 is connected to the gate of the transistor 3 by its anode, its cathode being connected to the supply voltage V.sub.ss. The drain of the transistor 3 is connected to a terminal of the integration capacitor C.sub.m also forming an input-output of the read circuit 10. The transistor 3 operating subthreshold is comparable to an inhibitory synapse.

(34) If the read circuit 10 is an artificial neuron, this drain-source current may be called a synaptic current. The ‘weight’ of the synapse may be adjusted for example: by suitably choosing the dimensions of the transistor, and in particular the conductance G.sub.p of the transistor, which is proportional to the width of the gate and inversely proportional to its length, using an (N or P) adjustment transistor 4 placed between the transistor 3 that operates subthreshold and the integration capacitor C.sub.m (when the transistor 3 may be likened to an excitatory synapse, said adjustment transistor 4 is placed between the drain of the transistor 3 operating subthreshold and the integration capacitor C.sub.m, as shown in FIG. 3).

(35) The overall synaptic current may excite or inhibit the artificial neuron, inter alia depending on the role of the transistor 3 operating subthreshold (excitatory or inhibitory synapse, respectively).

(36) The neuron may be easily connected to the neighbouring photovoltaic cells in order to create cells that are sensitive to contrast, as in a biological retina.

(37) FIG. 4 illustrates an example of elementary connection of photodiodes in an excitation or inhibition configuration.

(38) Without applied optical power, the neuron 10 may be stable (does not generate spikes) or unstable (generation of spikes at low frequency).

(39) The photodiode 21 is connected to a PMOS transistor 31 that is equivalent to an excitatory synapse of the artificial neuron 10. It tends to promote the generation of spikes by the neuron 10 or to increase the frequency of said spikes. The photodiode is connected to an NMOS transistor 32 that is equivalent to an inhibitory synapse. It tends to decrease the aforementioned frequency. Since the photodiodes operate in open circuit, the same photodiode may be connected to various synapses without modification of the properties thereof.

(40) As a variant, more complex processing of the received optical signals may be performed by associating a plurality of photodiodes with the same neuron 10.

(41) Any combination of activation and deactivation transistors is possible, because all the currents will be added algebraically at the same node i.e. the node forming the input-output of the neuron.

(42) It is thus possible to for example create equivalents of the ON and OFF cells of the biological retina.

(43) FIG. 5 shows an artificial implementation of an ON cell with a photodiode 21 associated with an activating transistor 31 playing the role of excitatory synapse at the centre and a plurality of photodiodes 22 associated with deactivating transistors 32 arranged in parallel and playing the role of inhibitory synapses on the perimeter. The number of photodiodes 22 associated with the deactivating transistors 32 will be chosen depending on the application and on the targeted characteristics.

(44) FIG. 6 shows an artificial implementation of an OFF cell with a photodiode 22 associated with a deactivating transistor 32 playing the role of inhibitory synapse at the centre and a plurality of photodiodes 21 associated with activating transistors arranged in parallel and playing the role of excitatory synapses on the perimeter.

(45) FIG. 7 describes an elementary association, a “square” (square or rectangular) type matrix of 40 pixels being considered, among which pixels subsets formed of central pixels 50 and peripheral pixels 55 may be considered. If parallels are drawn to FIG. 5 (schematic showing an ON cell), the pixel 50 at the centre of FIG. 7 corresponds to the photodiode the cathode of which is connected to the gate of the activating PMOS transistor (excitatory synapse), whereas the four peripheral pixels 55 encircling the pixel of the centre 50 have their cathode connected to ground and their anode connected to the gate of a deactivating NMOS transistor (inhibitory synapse).

(46) For a uniform illumination of the photodiodes, the artificial neuron will have a relatively low, or even zero spike frequency.

(47) If the pixel 50 at the centre is strongly illuminated, the overall excitation current delivered to the membrane of the neuron will increase and the pulse frequency also.

(48) If the peripheral pixels 55 of the perimeter are strongly illuminated, the sum of the inhibition currents will be higher than the excitation current and the neuron will no longer generate spikes (or very few; i.e. the spike frequency is relatively low, or even zero as in the case of uniform illumination).

(49) An architecture that is the twin of that of the circuit of FIG. 7 may also be used in order to obtain an OFF cell such as shown in FIG. 6 in which the pixel 50 of the centre is associated with an inhibitory synapse (photodiode connected to a deactivating transistor) and the four peripheral pixels 55 of the perimeter are associated with excitatory synapses (photodiodes connected to activating transistors).

(50) The topology organized into a “square” type matrix may be changed into a hexagonal configuration such as that shown in FIG. 8. Any polygonal topology is of course possible.

(51) Generally, for an association of N exciting pixels and M inhibiting pixels, the total synaptic current I.sub.tot applied to the neuron is expressed thus:

(52) $\begin{array}{cc}{I}_{\mathrm{tot}}=\left(V_{\mathrm{dd}}-V_m\right)\underset{i=1}{\overset{N}{.Math.}}{G}_{\mathrm{exc},i}.Math.\left(1+\frac{I_{\mathrm{exc},i}^{\mathrm{ph}}}{I_{s,i}}\right)-\left(V_m\right)\underset{j=1}{\overset{M}{.Math.}}{G}_{\mathrm{inh},j}.Math.\left(1+\frac{I_{\mathrm{inh},j}^{\mathrm{ph}}}{I_{s,j}}\right).& \left(8\right)\end{array}$

(53) In a normal operation of the photodiode, the photo-current I.sub.ph is much larger than the reverse current I.sub.s of the various junctions. Then:

(54) $\begin{array}{cc}{I}_{\mathrm{tot}}=\left(V_{\mathrm{dd}}-V_m\right)\underset{i=1}{\overset{N}{.Math.}}\frac{G_{\mathrm{exc},i}}{I_{s,i}}.Math.I_{\mathrm{exc},i}^{\mathrm{ph}}-\left(V_m\right)\underset{j=1}{\overset{M}{.Math.}}\frac{G_{\mathrm{inh},j}}{I_{s,j}}.Math.I_{\mathrm{inh},j}^{\mathrm{ph}}.& \left(9\right)\end{array}$

(55) Depending on the application, the conductances G.sub.exc,i and G.sub.ihh,i of the transistors will possibly be adjusted by adjusting parameters of the transistors (gate width and length for example).

(56) As the human eye does very well, it is desirable for an artificial vision system to be able to adapt to the average luminance of a scene and to be able to detect outlines and shapes both at low and high luminosities. To do this, it is possible to use, as illustrated in FIG. 9, a plurality of deactivating transistors 32. Thus, for high luminosities, the neuron will be hyperpolarized by a high current in the deactivating transistors 32, thereby creating a leakage that discharges the integration capacitor, and in case of low luminosity, the neuron will be depolarized by the decrease or disappearance of this leakage current.

(57) FIGS. 10 and 11 show two ways of producing the power required for the operation of an optical sensor 1. In FIG. 10, photovoltaic supply cells 100 are placed around the pixels, and in FIG. 11, these cells are arranged in rows alternating with those of the pixels. In the case where the power supply is integrated into the sensors, to generate a sufficient voltage, of a few hundred mV, two or more diodes 25 will possibly be placed in series, as illustrated in FIG. 12.

(58) FIG. 13 schematically illustrates an example embodiment of the artificial neuron 10. In this example, the artificial neuron 10 includes two inverters 5 and 6 that are connected in cascade, the output of the first being connected to the input of the second. The output of the first inverter 5 is connected to the gate of a PMOS transistor 8. The output of the second inverter is connected to the gate of an NMOS transistor 7.

(59) The transistors 7 and 8 are electrically connected in series and form a bridge between the supply voltage V.sub.dd and ground. The midpoint 9, which is defined by the connection of the drains of the transistors of the bridge, is connected to a terminal of the integration capacitor C.sub.m. The other terminal of the integration capacitor C.sub.m is connected to ground.

(60) A capacitor C.sub.k is connected between ground and the gate of the NMOS transistor 7. A capacitor C.sub.na is connected between V.sub.dd and the gate of the PMOS transistor 8.

(61) I.sub.ex is the external excitation current, which charges or discharges the integration capacitor C.sub.m and which originates from the one or more activation or deactivation transistors.

(62) When the potential across the terminals of the integration capacitor C.sub.m reaches the threshold voltage of the first inverter 5, a corresponding potential is then transmitted, after a first inversion by the inverter 5, to the gate of the PMOS transistor, activating the latter after a delay defined by the capacitor C.sub.na. Thus, the integration capacitor C.sub.m is charged by the open conduction channel of the PMOS transistor 8. This charge corresponds to the rising front of the output action potential.

(63) When the threshold voltage of the second inverter 6 is reached, a corresponding potential is transmitted to the gate of the NMOS transistor 7, activating the latter after a delay defined by the delay capacitor C.sub.k, which is in the considered example longer than the activation delay of the PMOS, because of the choice of C.sub.k>C.sub.na. Thus, after having had the time to charge, the integration capacitor C.sub.m starts to discharge on the opening of the conduction channel of the NMOS transistor 7. This discharge corresponds to the falling front of the output action potential.

(64) FIG. 14 schematically shows an artificial neuron 10 according to another example embodiment, which differs from that of FIG. 13 in that a third inverter 12 has been added, the first inverter 13 transmitting the output potential after inversion to the gate of the PMOS transistor 8 of the bridge and the two other inverters 11 and 12, which are connected in cascade, transmitting the output potential to the gate of the NMOS transistor 7.

(65) The inputs of the inverters 13 and 11 are connected to the midpoint 9 of the bridge and to the integration capacitor, and the input of the inverter 12 is connected to the output of the inverter 11.

(66) The addition of the third inverter allows the commands of the transistors of the bridge to be optimized independently, by independently adjusting the threshold voltages of the inverters.

(67) The adjustment of the voltage gain and of the threshold voltages of the inverters influences the operation of the artificial neuron 10.

(68) Preferably, the threshold voltage of the neurone that produces the action potential is the threshold voltage of the inverter supplying the PMOS transistor of the bridge with power. The number of inverters used may be defined depending on speed or power-consumption objectives.

(69) Among the variants in which the read circuit comprises not a single neuron comprising transistors operating subthreshold but rather a network of neurons comprising transistors operating subthreshold, the subvariants in which the synaptic circuit possesses two inputs and includes two transistors that are connected in series by their drains will be preferred, at least one of said transistors being of NMOS type and being controlled by a gate potential corresponding to the first input of the synaptic circuit, the gate of the second transistor corresponding to the second input of the synaptic circuit, and the output of the synaptic circuit, corresponding to the source of the NMOS transistor, being connected to the output potential of the post-neuron.

(70) By way of example, said synaptic circuit may correspond to: an excitatory synapse wherein the second input of the synaptic circuit is connected to the output of an inverter (preferably the first inverter of the pre-neuron) having for input the membrane potential of the pre-neuron, and in particular to the gate of the PMOS transistor of the bridge of the pre-neuron, or an inhibitory synapse wherein the second input of the synaptic circuit is connected to the output of two inverters in series (preferably the two inverters in cascade of the pre-neuron) the input of the first of which is subjected to the membrane potential of the pre-neuron, or an inhibitory synapse wherein the second input of the synaptic circuit is connected to the gate of the NMOS transistor of the bridge of the pre-neuron.

(71) Of course, the invention is not limited to the example embodiments that have just been described.

(72) The invention is most particularly applicable to retinal implants, but nevertheless covers a broad spectrum of applications. It may for example be used in robotics, home automation, the processing of images and videos, etc. The architecture of the artificial neuron associated with a cell of the optical sensor according to the invention may be different from the architectures described above.