METHOD FOR WRITING INTO AND READING A MULTI-LEVELS EEPROM AND CORRESPONDING MEMORY DEVICE

Abstract

During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.

Claims

1. A device comprising: a plurality of memory cells, each memory cell having a transistor with a floating gate, a control gate, a source region and a drain region; and a write circuit configured to write a selected memory cell with an item of data, wherein the write circuit comprises a programming circuit configured to: apply a first voltage to the source region; control the numerical value of the item of data to be written by a control voltage level applied to the control gate; apply a second voltage to the drain region, the second voltage being higher than the first voltage, the second voltage applied until the cell is put into conduction so that, the item of data is written when the cell is put into conduction with a numerical value corresponding to the control voltage level applied; and wherein the cell being put into conduction stops the programming; wherein the item of data is able to take n different numerical values; wherein the write circuit comprises a generation circuit configured to generate a set of at least n1 different programming values for the control voltage corresponding respectively to at least n1 different conduction thresholds of the cell respectively associated with at least n1 different numerical values of the item of data; and wherein the write circuit is configured to apply to the control gate of the transistor the control voltage having the programming value corresponding to a desired numerical value of the item of data.

2. The device according to claim 1, wherein n is greater than or equal to 3.

3. The device according to claim 2, wherein n is equal to 3.

4. The device according to claim 1, wherein the cell is erasable by Fowler-Nordheim effect; wherein the generation circuit is configured to generate a set of n values for the control voltage comprising an erase value corresponding to a first conduction threshold of the cell associated with a first numerical value of the item of data and n1 different programming values corresponding respectively to n1 other different conduction thresholds of the cell associated respectively with n1 other different numerical values of the item of data; wherein the write circuit further comprises an erase circuit configured to couple the drain and the source of the transistor to ground and to apply to the control gate a control voltage having the erase value; and wherein the write circuit is configured to apply to the control gate of the transistor the control voltage having the programming value corresponding to a desired numerical value of the item of data and taken from among the n1 different programming values of the set.

5. The device according to claim 1, wherein at least some of the programming values are negative.

6. The device according to claim 1, wherein the write circuit comprises a voltage generator with current limited to the value of the current of the cell put into conduction, the voltage generator configured to apply the second voltage to the drain of the transistor.

7. The device according to claim 1, wherein the write circuit comprises: a voltage generator configured to apply the second voltage to the drain of the transistor; a measuring circuit configured to measure a value of current consumed by the cell; a comparator configured to compare the value of the current consumed with a threshold and to deliver a control signal if the value of the current consumed exceeds the threshold; and a control circuit configured to deactivate the voltage generator in response to the control signal.

8. A device comprising: a plurality of memory cells, each memory cell having a transistor with a floating gate, a control gate, a source region and a drain region; and a write circuit configured to write a selected memory cell with an item of data, wherein the write circuit comprises a voltage generator and a control circuit configured to: cause a first voltage to be applied to the source region; control a numerical value of the item of data to be written by a control voltage level applied to the control gate; and cause the voltage generate to apply a second voltage to the drain region, the second voltage being higher than the first voltage, the second voltage applied until the cell is put into conduction so that, the item of data is written when the cell is put into conduction with the numerical value corresponding to the control voltage level applied, the voltage generator having current limited to a value of the current of the cell put into conduction, wherein the cell being put into conduction stops the writing.

9. The device of claim 8, wherein the item of data is capable of taking n different numerical values, wherein n>2, wherein the write circuit comprises a generation circuit configured to generate a set of at least n1 different voltage levels defined for the control voltage to be applied to the control gate of the transistor during the writing and respectively corresponding to at least n1 different conduction thresholds of the cell respectively associated with at least n1 different numerical values of the item of data.

10. The device of claim 9, wherein at least some of the control voltage levels are negative.

11. The device according to claim 8, wherein the write circuit comprises: a voltage generator configured to apply the second voltage to the drain of the transistor; a measuring circuit configured to measure a value of current consumed by the cell; a comparator configured to compare the value of the current consumed with a threshold and to deliver a control signal if the value of the current consumed exceeds the threshold; and a control circuit configured to deactivate the voltage generator in response to the control signal.

12. A method of operating a memory cell, the method comprising: reading an item of data written in a memory cell, the memory cell comprising a transistor having a floating gate, a control gate, a source region and a drain region, the memory cell capable of having n different numerical values corresponding respectively to n different conduction thresholds of the cell, the reading comprising: generating a set of at least n1 reference values for a read voltage to be applied to the control gate of the transistor during a read cycle, the n1 reference values being respectively situated between the n conduction thresholds; applying a third voltage to the drain; applying, to the control gate, a read voltage having a lowest reference value; and if the cell is cut off, applying, to the control gate, a read voltage having a reference value adjacent to a previously applied reference value and repeating with further reference values until a conducting cell is obtained or until all of the reference values have been exhausted.

13. The method of claim 12, further comprising programming the memory cell, the programming comprising: applying a first voltage to a source region of a transistor, the transistor having a floating gate, a control gate, the source region, and a drain region; and applying a second voltage that is higher than the first voltage to the drain region and applying a control voltage to the control gate until the cell is put into conduction, the conduction of the cell being between the source region and the drain region, a numerical value of an item of data to be written being controlled by the control voltage applied to the control gate, the control voltage being smaller in absolute value than the second voltage, wherein the cell being put into conduction stops the programming.

14. The method according to claim 13, wherein applying the first voltage to the source region comprises connecting the source region to ground during the programming.

15. The method according to claim 13, wherein applying the first voltage to the source region comprises connecting a non-zero first voltage to the source region during the programming.

16. The method according to claim 13, wherein the item of data to be written is capable of taking n different numerical values, wherein n>2 and wherein a set of at least n1 different programming values is defined for the control voltage to be applied to the control gate of the transistor during the programming and respectively corresponding to at least n1 different conduction thresholds of the cell respectively associated with at least n1 different numerical values of the item of data, and wherein, applying the control voltage to the control gate during the programming comprises applying the control voltage having the programming value corresponding to a desired numerical value of the item of data.

17. The method according to claim 16, wherein n=3.

18. The method according to claim 16, wherein at least some of the programming values are negative.

19. The method according to claim 13, wherein applying the second voltage to the drain region comprises applying the second voltage with a voltage generator with current limited to the current consumed by the cell put into conduction.

20. The method of claim 12, further comprising erasing the memory cell, the erasing comprising: coupling the drain and the source of the transistor to ground; and applying a control voltage having an erase value to the control gate so as to give the cell a first conduction threshold associated with a first numerical value of the item of data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other advantages and features of the invention will become apparent on examination of the detailed description of implementations and embodiments that are in no way limiting and of the appended drawings in which:

[0049] FIGS. 1 to 14 are diagrammatic illustrations of different implementations and embodiments of write methods and of read methods according to the invention and of a memory device according to the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0050] In FIG. 1, the memory device DIS here comprises a memory cell CEL, for example a memory cell of the EEPROM type, comprising a transistor TR having in conventional manner a control gate CG, a floating gate FG, a drain region D and a source region S.

[0051] The device DIS also comprises a programming circuit MPR intended for, as will be seen in detail below, applying appropriate voltages to the drain, source and control gate regions.

[0052] The device DIS also comprises an erase circuit MEF intended to place the memory cell CEL in an erased state as well as a read circuit MLT configured to read the item of data written in memory cell CEL.

[0053] The read conduction threshold, or more simply the conduction threshold, of the cell CEL is the voltage V.sub.t that must be applied during reading to the control gate in order to make the cell conduct. This conduction threshold V.sub.t is defined by the following formula (1):

A.Math.V.sub.t+B.Math.V.sub.dr+Q/C.sub.tot=V.sub.t0+V.sub.S(1)

in which V.sub.dr denotes the voltage applied to the drain during reading, V.sub.t0 is the threshold voltage of the state transistor of the cell, that is to say the buried transistor, seen from the floating gate, Q denotes the charge stored on the floating gate (typically Q is negative for an erased cell, zero for a blank cell and positive for a programmed cell), C.sub.tot is the total capacitance seen from the floating gate (floating gate capacitively coupled with the control gate, the drain, the channel, the source and the substrate), A=C1/C.sub.tot where C1 denotes the coupling capacitance between the control gate and the floating gate, B=C2/C.sub.tot where C2 denotes the coupling capacitance between the floating gate and the drain, V.sub.S denotes the voltage applied to the source region.

[0054] Typically, for a cell of the EEPROM type, A varies from 0.6 to 0.75 and B varies from 0.2 to 0.3 depending on the embodiment of the cell.

[0055] The charge Q is therefore defined by the following formula (2):

Q=[V.sub.t0+V.sub.SA.Math.V.sub.tB.Math.V.sub.dr].Math.C.sub.tot(2)

[0056] For a given charge Q, the stopping of the programming occurs when the voltage V.sub.FG on the floating gate is equal to V.sub.t0+V.sub.S which is then represented by the following equation (3):

A.Math.V.sub.CG+B.Math.V.sub.d+Q/C.sub.tot=V.sub.t0+V.sub.S(3)

in which V.sub.CG denotes the voltage applied to the control gate during programming, V.sub.d denotes the voltage applied to the drain during programming.

[0057] Considering the equation (2), the following equation (4) is therefore obtained

A.Math.[V.sub.CGV.sub.t]+B.Math.[V.sub.dV.sub.dr]=V.sub.S(4)

[0058] As the programming is stopped during injection, the voltage V.sub.FG is equal to (V.sub.t0+V.sub.S), and (V.sub.dV.sub.FG) is substantially equal to V.sub.FN where V.sub.FN denotes the Fowler-Nordheim injection voltage.

[0059] When the programming is stopped, the following equation (5) is therefore obtained:

V.sub.d=V.sub.FN+V.sub.t0+V.sub.S(5)

[0060] Combining the equations (4) and (5) then provides the following equation (6):

V.sub.CG=V.sub.t+[B/A].Math.[V.sub.drV.sub.FNV.sub.t0+V.sub.S(1B/A)](6)

[0061] Moreover, making the hypothesis that the voltage V.sub.dr is substantially equal to the voltage V.sub.t0, which is typically the case, the following equation (7) is then obtained.

V.sub.CG=V.sub.t[B/A].Math.V.sub.FN+V.sub.S(1B/A)(7)

[0062] This formula (7) biunivocally determines the voltage V.sub.CG to be applied to the control gate of the transistor TR at the time when the cell begins to conduct in order to obtain a final threshold voltage (final conduction threshold) of the cell equal to V.sub.t.

[0063] Thus, if the programming of a cell is stopped when it is put into conduction, the value V.sub.CG makes it possible to control the conduction threshold of a cell having undergone a programming cycle.

[0064] In other words, it has been shown that there is a unique relationship between the voltage to be applied to the control gate and the conduction threshold of the cell, which makes it possible, for a target conduction threshold, to define the value of the voltage to be applied to the control gate in order to reach this target conduction threshold.

[0065] Moreover, if this target conduction threshold is associated with a numerical value of the item of data to be written, it is therefore possible to associate this numerical value of the item of data with a voltage to be applied to the control gate.

[0066] In other words, during the phase of programming the cell, a voltage is applied to the drain region that is higher than the voltage applied to the source region until the cell is put into conduction, the numerical value of the item of data to be written being controlled by the level of the control voltage applied to the control gate and this item of data is de facto written with the numerical value when the cell is put into conduction, the programming then being stopped.

[0067] It is thus easy to store in the memory cell numerical items of data able to take several different numerical values, for example items of data encoded in two or more bits, simply by controlling the charge injected in real time into the cell by application to the control gate of a voltage corresponding to the conduction threshold of the cell associated with the numerical value desired for the item of data. No iterative algorithms with successions of programming and reading are therefore used. There is no impact on the programming time.

[0068] Such a method does not necessitate a complex machine and, for a memory plane whose cells are capable of storing two bits corresponding to four charge level domains, a doubling of the density is obtained for the same area of the memory plane.

[0069] An example of such a programming is shown in greater detail in FIG. 2.

[0070] Thus, for an item of data DD able to take n different numerical values dd.sub.1-dd.sub.n, n conduction thresholds V.sub.t1-V.sub.tn are defined for the cell, respectively corresponding to the n numerical values dd.sub.i of the item of data DD to be written. It is then possible to define n values V.sub.CGi for the voltage applied to the control gate during the programming, each of these values V.sub.CGi corresponding to the conduction threshold V.sub.ti and therefore to the numerical value dd.sub.i of the item of data DD to be written.

[0071] This being so, as will be seen in greater detail below, it is possible to define only n1 values of voltage to be applied to the control gate during the programming and to use a voltage applied to the control gate during the erasing of the cell in order to define a conduction threshold that corresponds to one of the possible numerical values of the item of data DD.

[0072] If it is desired to write the item of data DD with the numerical value dd.sub.j, then the corresponding voltage V.sub.CGj is applied (step 20) to the control gate CG. Moreover the voltage V.sub.s1 is applied to the source region S of the transistor TR of the cell (step 21). This value V.sub.s1 can be equal to zero (source connected to ground) or equal to a non-zero voltage V.sub.S0.

[0073] Moreover, a second voltage V.sub.d2 is applied to the drain D of the transistor (step 22), this voltage V.sub.d2 being higher than the voltage V.sub.s1 applied to the source in order to be able to put the cell CEL into conduction.

[0074] Moreover, when this cell is effectively put into conduction (step 23), the programming is then stopped, the cell CEL de facto containing on its floating gate the corresponding charge Q, the cell CEL therefore being de facto written with the item of data DD having the numerical value dd.sub.j corresponding to the value V.sub.CGj of the programming voltage applied to the control gate CG.

[0075] There are several possible ways of stopping the programming of the cell when it is put into conduction.

[0076] Two of these are shown diagrammatically in FIGS. 3 and 4.

[0077] More precisely, in FIG. 3, the voltage V.sub.d2 applied to the drain D of the transistor TR during the programming is provided by a voltage generator GEM limited in current to the value of the current consumed by the cell when the latter is conducting, for example 10 nanoamps.

[0078] Consequently, as shown in FIG. 3, during the putting into conduction, the programming of the cell is automatically stopped by the drop in the drain voltage towards the source voltage.

[0079] The other way, illustrated in FIG. 4, uses for applying the voltage to the drain D, a voltage generator GEN2 that is not current limited. On the contrary, the device DIS then comprises a measuring circuit MES configured to measure the current consumed by the cell. A comparator CMP compares the measured current value with a threshold SE, typically 10 nanoamps. The output of the comparator CMP delivers a control signal SACT to the control circuit MCM which are configured to deactivate or not the generator GEN2. More precisely, when the value of the current consumed by the cell, that is to say the value of the bit lines current, exceeds the threshold SE, this signifies a putting into conduction of the cell CEL and the control circuit then deactivates the generator GEN2 in order to stop the programming.

[0080] The cell CEL can also be erased by the Fowler-Nordheim effect. The writing of an item of data in such a cell, for example of the EEPROM type, comprises an erase cycle preceding the programming phase.

[0081] This conventional erase cycle is shown in FIG. 5. More precisely, the erase circuit MEF is configured to couple the drain and the source of the transistor to ground (steps 50 and 51), and to apply to the control gate (step 52) a control voltage having an erase value VCGe, typically 13 volts.

[0082] Moreover, at the end of this programming cycle, the cell CEL has a first conduction threshold Vt1 which can then be associated with a first numerical value dd1 of the item of data DD.

[0083] In these conditions, it is then only necessary to define n1 different programming values V.sub.CG2-V.sub.CGn for the control voltage to be applied to the control gate of the transistor during the programming phase 55, these n1 different programming values corresponding respectively to n1 other different conduction thresholds of the cell associated respectively with the other n1 different numerical values dd.sub.2-dd.sub.n of the item of data DD.

[0084] FIG. 6 is a diagrammatic illustration of an implementation of the method of reading an item of data DD written in the memory cell CEL, this item of data DD being able to have n different numerical values respectively corresponding to n different conduction thresholds V.sub.t1-V.sub.tn of the cell.

[0085] In this respect, there is generated (step 60) a set of at least n1 reference values V.sub.refk,k+1 for the read voltage to be applied to the control gate of the transistor during a read cycle, k varying from 1 to n1.

[0086] These n1 reference values V.sub.refk,k+1 are respectively situated between the n conduction thresholds V.sub.tk and V.sub.tk+1.

[0087] Preferably, for each reference value situated between two conduction threshold values, a reference value that is sufficiently distant from the corresponding thresholds will be chosen, for example situated in the middle of the interval.

[0088] During this read cycle, a voltage V.sub.d3 is applied (step 61) to the drain D of the transistor, typically of the order of 1 volt, the source is coupled to ground and a read voltage having a reference value V.sub.refk,k+1 taken from among the set of reference values is applied to the control gate (step 62). In practice, the lowest reference value (k=n1) will be applied firstly, that is to say V.sub.refn-1,n.

[0089] Then it is tested (step 63) if the cell CEL is conducting or not.

[0090] If the cell is conducting, then this signifies (step 64) that the cell was written with the value dd.sub.k+1 corresponding to the conduction threshold V.sub.tk+1.

[0091] In the opposite case, that is to say if the cell is cut off, steps 62 and 63 are repeated with another reference value taken from among the set of reference values until a conducting cell is obtained.

[0092] In practice, the increasing read voltages will be applied to the control gate CG in the decreasing order of their rank (decrementation of k: step 65).

[0093] Moreover if, during the application of a read voltage having the first highest reference value V.sub.ref1,2, the cell is still cut off (steps 63 and 66) this signifies that the cell was written with the numerical value dd.sub.1 corresponding to the last highest conduction threshold V.sub.t1.

[0094] Although this is possible, it is in fact not necessary in practice to apply a read voltage higher than the last conduction threshold V.sub.t1 to the control gate of the cell CEL in order to ensure that the cell is then fully conducting.

[0095] In the embodiment shown in FIG. 7, the device DIS this time comprises a memory plane PM of cells CEL.sub.i,j, organized in lines and columns.

[0096] It is also assumed in this embodiment that each item of data DD to be written in a memory cell CEL.sub.i,j is encoded in two bits, that is to say that it is capable of taking four different numerical values dd.sub.1-dd.sub.4, for example the values 00, 01, 10 and 11.

[0097] It is also assumed in this embodiment, by way of example, that among all the memory cells of the memory plane, the cells CEL.sub.g1 belonging to a first group de memory cells are intended to be written with the numerical value dd.sub.1 (00).

[0098] The memory cells CEL.sub.g2 of a second group are intended to be written with the numerical value dd.sub.2 (01).

[0099] The cells CEL.sub.g3 of a third group are intended to be written with the numerical value dd.sub.3 (1,0).

[0100] The cells CEL.sub.g4 of a fourth group are intended to be written with the numerical value dd.sub.4 (1,1).

[0101] Moreover, by way of example, four target conduction thresholds V.sub.t1-V.sub.t4 corresponding respectively to the four numerical values dd.sub.1-dd.sub.4 are defined.

[0102] More precisely, by way of example, the values of these conduction thresholds V.sub.t1-V.sub.t4 are fixed at 2.9 volts, 1.6 volt,

0.3 volt and 1 volt respectively

[0103] If, by way of example, it is considered that the value V.sub.FN of the Fowler-Nordheim voltage is equal to 9 volts, V.sub.t0 is equal to V.sub.dr and to 0.9 volt, A is equal to 0.7 whilst B is equal to 0.25, then from this it is derived, taking account of the above equation (7), that the programming value V.sub.CG of the voltage to be applied to the control gate during the programming phase is then defined by the following formula (8):

V.sub.CG=V.sub.t3.2 volts(8)

[0104] The four programming values V.sub.CG1-V.sub.CG4 corresponding respectively to the four target conduction thresholds mentioned above and respectively associated with the four numerical values dd.sub.1-dd.sub.4 of the item of data DD are then as follows: [0105] Value dd.sub.1 (00): V.sub.CG1=0.3 volt, [0106] Value dd.sub.2 (01): V.sub.CG2=1.6 volt, [0107] Value dd.sub.3 (10): V.sub.CG3=2.9 volts, [0108] Value dd.sub.4 (11): V.sub.CG4=4.2 volts.

[0109] In fact, as will now be seen in greater detail, the value V.sub.CG1 is in fact useless because the first conduction threshold will be obtained at the end of the erase cycle.

[0110] In this respect, reference will now be made more particularly to FIG. 8.

[0111] In this figure, the curve CV1 shows the variation of the voltage V.sub.CG applied to the control gate of the different cells during the write cycle (erasing then programming).

[0112] The curve CV2 shows the corresponding variation of the drain voltage upstream of a current limiter associated with the generator delivering this voltage whilst the curve CV3 shows the drain voltage downstream of this current limiter.

[0113] Firstly, the erase circuit executes an erase cycle bringing all the cells of the four groups CEL.sub.g1, CEL.sub.g2, CEL.sub.g3 and CEL.sub.g4 to the conduction threshold V.sub.t1 (2.9 Volts). Consequently, all of the numerical values (00, 01, 10, 11) are involved here.

[0114] During this erase cycle, the erase circuit applies a gradient rising from 0 to 13 volts in 0.5 milliseconds to the control gate, for example, followed by a level section at 13 volts for a duration of 0.5 milliseconds. The erase circuit also couples the drain and the source to ground.

[0115] The programming phase will then comprise three successive programming cycles CP1, CP2 and CP3.

[0116] During the first programming cycle CP1, the programming circuit selects only cells CEL.sub.g2, CEL.sub.g3 and CEL.sub.g4 by excluding the cells of the first group CEL.sub.g1 which have to be programmed only with the numerical value 00.

[0117] During this first programming cycle, the programming value V.sub.CG2=1.6 volt is applied to the control gate of the transistors of the selected cells.

[0118] The programming circuit moreover applies, before current limitation, a voltage V.sub.d2 to the drain in the form of a gradient rising from 0 to 12 volts in 0.4 milliseconds followed by a level section of 0.4 milliseconds. Taking account of the current limitation, the voltage on the drain is limited to 9 volts and then drops during the putting into conduction of the cells, which causes, as explained above, the stopping of the programming.

[0119] At the end of this first programming cycle, all of the cells CEL.sub.g2, CEL.sub.g3 and CEL.sub.g4 finish with a conduction threshold of 1.6 volts.

[0120] During the second programming cycle CP2, this time it is the cells CEL.sub.g1 and CEL.sub.g2 that are excluded from the programming and only the cells CEL.sub.g3 and CEL.sub.g4 are selected.

[0121] During this second programming cycle CP2, the programming value V.sub.CG2, equal to 2.9 volts, is applied to the control gates of the selected cells whilst the programming circuit applies, during this cycle, a voltage V.sub.d2 to the drain, equivalent to the one applied during the first programming cycle.

[0122] At the end of this second programming cycle, the cells CEL.sub.g3 and CEL.sub.g4 finish with a conduction threshold equal to 0.3 volt.

[0123] During the third programming cycle CP3, this time it is the cells CEL.sub.g1, CEL.sub.g2 and CEL.sub.g3 that are excluded from the programming, and only the cells CEL.sub.g4 are selected.

[0124] Here again, the voltage applied to the drain is identical to that applied during the preceding two programming cycles. On the contrary, during this third programming cycle CP3, the reference value V.sub.CG4, equal to 4.2 volts is applied to the control gates of the selected cells.

[0125] Moreover, at the end of this third programming cycle, the cells CEL.sub.g4 finish with a conduction threshold of 1 volt.

[0126] Thus, at the end of these three programming cycles, the cells CEL.sub.g1 have been programmed with the value 00, the cells CEL.sub.g2 have been programmed with the value 01, the cells CEL.sub.g3 have been programmed with the value 10 and the cells CEL.sub.g4 have been programmed with the value 11.

[0127] Reference will now be made more particularly to FIG. 9 in order to describe an embodiment of a device according to the invention applicable to a memory plane of the EEPROM type having 512 lines and 512 columns with a granularity of the byte type.

[0128] Taking account of this byte granularity, the memory cells of a same line can be grouped in blocks of 8 and the 512 homologous blocks situated respectively on the 512 lines share the same line CGL connected to all of these cells. There are therefore 64 lines CGL for 512 bit lines BL and 512 word lines WL.

[0129] Moreover, in the continuation of the description the term column will globally denote a block of 8 bit lines.

[0130] The erase circuit MEF comprises positive charge pump PCHP, of conventional structure and known per se, followed by a positive gradient generation circuit GRP.

[0131] The programming circuit MPR comprises a negative charge pump PCHN of conventional structure and known per se, followed by a negative gradient generation circuit GRN.

[0132] The write circuitry, which groups the programming circuit MPR and erase circuit MEF, also comprises a switch SW that makes it possible to switch between the negative and positive voltages as a function of the erase and programming cycles.

[0133] The write circuitry also comprises a write controller CTRE, which can be embodied, for example, by software within a microcontroller or by means of logic circuits and that are intended to control the erasing and the programming of the selected cells.

[0134] The read circuit MLT comprises a read sequencer SQL, a unit RL intended to generate the different reference values of the read voltages, and conventional read amplifiers SA connected to the read sequencer and to the unit RL.

[0135] A conventional state machine MET makes it possible to monitor these different circuits.

[0136] The device comprises moreover in a conventional manner a bidirectional data register RD, an address register RAD and a bus interface INTB. Finally, these different programming, erase and read circuit comprises a first decoder DCD1 configured to make selections (to decode) from among the 64 lines CGL and the 512 bit lines BL and a second decoder DCD2 configured to make selections from among the 512 word lines WL.

[0137] The decoder DCD1 comprises one BLCG unit per CGL line, shown in FIG. 10, the function of which is now described.

[0138] During the erase cycle, it must send the erase value (13 volts) on the CGL line of a selected column and 0 volt, for example, on the CGL line of a non-selected column.

[0139] The Column signal is at 1 for a selected column and at 0 for a non-selected column.

[0140] During the programming phase, it must send the successive values of the programming voltages (1.6 volt, 2.9 volts, 4.2 volts) on the CGL line of a selected column and 0 volt (for example) on the CGL line of a non-selected column.

[0141] For this purpose, the unit BLCG comprises a conventional latch memory MV1 supplied between ground and Vcc (for example 3 volts) followed by a level translator TRLN the N-type MOS transistors of which, having a fourth substrate connection, are produced using triple well technology, for isolating the substrate because of the presence of negative voltages.

[0142] The level translator TRLN comprises two NMOS transistors T1 and T2 controlled by a signal Prog and two NMOS transistors T3 and T4 controlled by a signal EfouLit.

[0143] The level translator TRLN also comprises two other NMOS transistors T5 and T6 controlled by a signal Vcasc and another latch memory MV2 and an inverter INV1 whose PMOS transistor P1 receives on its source the voltage VSP and whose output INVS delivers the voltage applied to the CGL line.

[0144] Table 1 summarizes, according to the different operations (read, erase, programming) the values of the various signals and voltages applied to the BLCG unit and delivered by the latter.

TABLE-US-00001 TABLE 1 Read Erase Programming Col Col not Col Col not Col Col not select. select. select. select. select. select. Vcc 3 V 3 V 3 V 3 V 3 V 3 V Out 0 3 V 0 3 V 0 3 V Nout 3 V 0 3 V 0 3 V 0 EfouLit 3 V 3 V 3 V 3 V 0 0 Prog 0 0 0 0 3 V 3 V Vcasc 3 V 3 V 3 V 3 V V.sub.CGp < 0 V.sub.CGp < 0 Vpp 3 V 3 V V.sub.CGe >> 0 V.sub.CGe >> 0 0 0 V.sub.SP V.sub.CGr > 0 V.sub.CGr > 0 V.sub.CGe >> 0 V.sub.CGe >> 0 0 0 Vpn 0 0 0 0 V.sub.CGp < 0 V.sub.CGp < 0 INVS 0 V.sub.CGr > 0 0 V.sub.CGe >> 0 0 V.sub.CGp < 0

[0145] The latch memory MV1 is reinitialized by a write and read pulse RAZ.

[0146] In this Table 1, col is the abbreviation of column, select is the abbreviation of selected and VCGr, VCGe, VCGp respectively denote the voltages to be applied to the control gate when reading, erasing or programming.

[0147] The different voltages come from positive or negative charge pump circuits.

[0148] Thus, according to whether it is an erase (or read) or programming operation, the connections between the latch memory MV1 and the level translator TRLN are switched such that a selected CGL line receives the high level from the level translator during erasing or reading (13 volts and 1 volt respectively) and the low level from the level translator during programming (1.6 volt/2.9 volts/4 volts).

[0149] The decoder DCD1 also comprises one bit line decoding unit DCBL per bit line, an example embodiment of which is shown in FIG. 11.

[0150] The function of the bit line decoder DCBL is, during writing, to store the data of a byte for the purpose of a future writing and to switch or not switch the high voltage to the bit line during the programming cycle according to the binary value to be programmed and, during reading, to multiplex the bit lines in order to route the bit lines belonging to the selected column to the read amplifiers.

[0151] In the example described here, taking account of the fact that an item of data is encoded in two bits, the BCBL unit comprises two latch memories MVA and MVB respectively allocated to the most significant bit DatMsb of the item of data and to the least significant bit DatLsb of the item of data and a module MCTL for controlling the state of the bit line BL in question.

[0152] The outputs SMVA and SMVB of the two latch memories MVA and MVB control the gates of the transistors N14-N16 and N13, N17 of the module MCTL. Moreover, three two-state signals pulse1, pulse2, pulse3 respectively allocated to the three programming cycles CP1-CP3 described above control the gates of three transistors N10-N12. In an active state (high) the signal pulse i (i=1, 2 or 3) rises to the high voltage (15 V for example) and in an inactive state (low) the signal is at the low voltage (0 V for example).

[0153] As mentioned above, one solution consists in limiting the bit line current in order to stop the programming naturally when the cell is put into conduction. This is here the function of the PMOS transistor P2 connected in a common gate configuration and operating as a current copier (typically 10 nanoamps). The gate voltage VrefP of the transistor P2 of the module MCTL is equal to Vpp1 volt, which makes it possible to give it a gate-source voltage close to its threshold voltage.

[0154] The bit lines must receive from 0 to 3 programming cycles respectively controlled by the logic signals pulse1, pulse2 and pulse3 according to the possible value of the item of binary data. This is the function of the transistors N10 to N17.

[0155] During erasure, pulse1, pulse2, pulse3 are at 0 volt, the source is at 0 volt and the bit line BL is floating. Therefore, for a cell selected by the selection transistor TSL, the drain also changes to 0 volt because the cell is conducting and the source line SL is at 0 volt.

[0156] Moreover, during erasure and during programming, the logic signal Read controlling the transistor N8 is at 0 whereas it is at 1 during a read operation.

[0157] The column signal controls a transistor N9.

[0158] The appended Table 2 summarizes the values of the different logic signals, of the outputs SMVA, SMVB and the states of certain transistors and of the bit line BL as a function of the numerical value of the item of data to be written.

TABLE-US-00002 TABLE 2 Data DatMsb DatLsb SMVA SMVB 00 0 0 0 0 01 0 1 0 1 10 1 0 1 0 11 1 1 1 1 Data N13 N14 N15 N16 N17 00 cut off cut off cut off cut off cut off 01 conduct- cut off cut off cut off conduct- ing ing 10 cut off conduct- conduct- conduct- cut off ing ing ing 11 conduct- conduct- conduct- conduct- conduct- ing ing ing ing ing Data Pulse 1 = 1 Pulse 2 = 1 Pulse 3 = 1 00 BL floating BL floating BL floating 01 BL selected BL floating BL floating 10 BL selected BL selected BL floating 11 BL selected BL selected BL selected

[0159] FIG. 12 is a figure similar to FIG. 9 but shows, in its lower section, the value of the logic signals pulse1, pulse2 and pulse3 corresponding to the three programming cycles CP1, CP2, CP3 mentioned above.

[0160] FIGS. 13 and 14 show an example embodiment of the read circuit.

[0161] More precisely, in FIG. 13, the unit RL provides on the line the reference value of the voltage applied to the control gate during the reading and also delivered to one of the inputs of the read amplifier as will be seen below.

[0162] In the example described here, taking account that there are four conduction thresholds corresponding to four different values of the item of data, the unit RL comprises three reference voltage generators V.sub.ref1, V.sub.ref2 and V.sub.ref3 as well as three switches SW1, SW2, SW3 controlled respectively by three logic signals read1, read2 and read3 in order to select the appropriate reference voltage for delivering on the line CG.sub.ref. It is appropriate to note that it is possible to have a similar unit for selecting the appropriate gate voltages during the erase and programming phases.

[0163] In the example described and taking account of the calculated conduction thresholds, these reference voltages V.sub.ref1, V.sub.ref2 and V.sub.ref3 are respectively taken as equal for example to 0.3 V, 0.95 V and 2.2 V.

[0164] The read circuit also comprises a unit BL2 (FIG. 14). This unit comprises a read amplifier SA and two latch memories MVA and MVB (since in the described example, the item of data is encoded in 2 bits). In practice there is one pair of latch memories MVA and MVB per bit line and multiplexed read amplifiers (8 read amplifiers for 512 bit lines).

[0165] The input of the read amplifier SA is connected to the bit line decoding unit DCBL (FIG. 11) by the bus RDB and another input is connected to the line CG.sub.ref of the unit RL. The output of the read amplifier SaOut is connected to the input of the two latch memories MVa and MVb whose states represent the 2-bit item of binary data derived from three successive reads with the three reference values V.sub.ref1-V.sub.ref3, beginning with the lowest value V.sub.ref1 and ending with the highest value V.sub.ref3.

[0166] The output SaOut is at 1 if the cell is conducting and at 0 if the cell is cut off.

[0167] The output Msb of the flip-flop MVa will contain the value of the most significant bit of the read data whilst the output Lsb of the flip-flop MVb will contain the value of the least significant bit of that item of data. Before the three successive reads, the two latch memories are reinitialized (pulse RAZ to the logic 1 state). Table 3 summarizes the content of the two flip-flops MVa and MVb according to different possibilities. In this table, the read1 result column indicates the different possible states of the read cell during the first read. The same applies to the read2 result and read3 result columns for the succeeding two reads.

TABLE-US-00003 TABLE 3 read1 read2 read3 Binary result result result Msb Lsb data Cell Cell Cell 1 1 11 conducting conducting conducting Cell cut Cell Cell 1 0 10 off conducting conducting Cell cut Cell cut Cell 0 1 01 off off conducting Cell cut Cell cut Cell cut 0 0 00 off off off

[0168] If of course a cell is conducting during a read associated with readi, it will be conducting during any following read and the Msb and Lsb values will not be modified during these following reads.

[0169] At the end of the three consecutive read steps, the content of the two latch memories MVa and MVb forms a binary word identical to the content of the latch memories MVA and MVB used for programming these items of data.

[0170] In all of the above, the various mathematical equations and the calculation of the conduction threshold values have been based, for reasons of simplification, on read currents identical to the bit line current limit during the programming (for example, 10 nA).

[0171] In practice the read currents can be higher, for example of the order of 1 microamp.

[0172] The conduction threshold of the cell depends on the injected current and a current shift gives rise to a shift of the conduction threshold. This shift is the same whether the cell is blank, written or erased.

[0173] In concrete terms, with respect to conduction thresholds calculated for a read current identical to the bit line current limit during programming (for example 10 nA), these conduction thresholds increase by 100 to 200 mV for a higher read current, for example of the order of 1 microamp.

[0174] However, this has no effect on the features of the invention.

[0175] In fact, in order to take account of this rising of the read current, and therefore of this rising of the conduction thresholds, in the determination of the read reference voltages, one solution consists in determining the conduction thresholds and the read reference voltages on the basis of read currents identical to the bit line current limit during programming (for example 10 nA) and to lower the values of the reference voltages thus obtained by a fixed value (200 mV for example) so that they correspond to the highest read currents (for example 1 microamp). Those skilled in the art will know how to determine this fixed value, knowing the value of the current limit and the real value of the read current.