Method of making a circuitized substrate

Abstract

A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Claims

1. A method of making a circuitized substrate, said method comprising: providing a first electrically conductive layer; providing at least one organic dielectric layer including first and second opposing surfaces; providing a second electrically conductive layer and positioning said second electrically conductive layer such that said at least one organic dielectric layer is located substantially between said first and second electrically conductive layers; forming at least one opening within said at least one organic dielectric layer and extending from said first electrically conductive layer to said second electrically conductive layer; and positioning a quantity of conductive paste within said at least one opening, said quantity of electrically conductive paste electrically coupling said first and second electrically conductive layers, said quantity of conductive paste including: a plurality of micro-particles having an average size of from about one micron to about fifty microns of at least one metallic component selected from the group: copper, silver, gold, silver-coated copper, gold-coated copper, and alloys thereof; a plurality of nano-particles having an average size of from about 0.01 microns to about one micron of said at least one metallic component selected from the group: copper, silver, gold, silver-coated copper, gold-coated copper, and alloys thereof; and a plurality of micro-particles particles having an average size of from about one micron to about fifty microns of at least one low melting point metallurgy selected from the group: tin-lead, bismuth-tin, bismuth-tin-iron, tin, tin-silver, tin-gold, tin-silver-zinc, tin-silver-zinc-copper, tin-bismuth-silver, tin-copper, tin-copper-silver, tin-indium-silver, tin-antimony, tin-zinc, tin-zinc-indium, copper-based solders, and alloys thereof.

2. The method of claim 1 wherein said forming of said at least one opening within, said at least one organic dielectric layer is accomplished using laser or mechanical drilling.

3. The method of claim 1 wherein said positioning of said conductive paste within said at least one opening is accomplished using printing or needle dispensing.

4. The method of claim 1 wherein said providing of said first and second electrically conductive layers is accomplished using photolithographic processing.

5. The method of claim 1 further including heating said circuitized substrate to a temperature sufficiently high enough to cause sintering of said plurality of micro-particles of at least one metallic component and said nano-particles of at least one metallic component.

6. The method of claim 5 wherein said heating of said circuitized substrate is also sufficiently high enough to cause melting of micro-particles having an average size of from about one micron to about fifty microns of at least one low melting point metallurgy during or after said sintering of said plurality of nano-particles of said at least one metallic component and said micro-particles of said at least one metallic component.

7. The method of claim 6 wherein said heating of said circuitized substrate is accomplished by laminating said circuitized substrate.

8. The method of claim 1 further including positioning an electronic component on said circuitized substrate and electrically coupling said electronic component to said circuitized substrate to form an electrical assembly.

9. The method of claim 1 wherein said nano-particles of said at least one metallic component have been deposited directly and uniformly from solution onto the surface of said micro-particles of said at least one metallic component.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1-4 are side elevational views, in section, showing the steps of making a circuitized substrate according to one embodiment of the invention;

(2) FIG. 5 illustrates an optional step which may be performed on the substrate of FIG. 4 to better enable it to perform as an interim substrate such as may be used in the assembly shown in FIG. 6 below;

(3) FIG. 6 is an exploded, side elevational view, in section, showing the various parts of a multilayered circuitized substrate assembly according to one embodiment of the invention;

(4) FIG. 7 is a side view of two examples of electrical assemblies which can utilize one or more of the circuitized substrates of the invention; and

(5) FIG. 8 is a perspective view of an information handling system adapted for using at least one circuitized substrate of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

(6) For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. Like figure numbers will be used from figure to figure to identify like elements in these drawings.

(7) By the term circuitized substrate as used herein in one embodiment is meant to include a substrate having at least one (and preferably more) dielectric layer(s), at least two (and preferably more) electrically conductive layers, and at least one (and preferably more) openings extending through the dielectric layer and interconnecting the two conductive layers. The electrically conductive layers may each include one or more conductors (e.g., signal lines and/or pads). Significantly, the dielectric material which constitutes the at least one dielectric layer must possess a melting point greater than that of the conductive pastes defined herein. Examples of such dielectric materials include: fiberglass-reinforced epoxy resin (FR-4), polytetrafluoroethylene (Teflon), polyimide, polyamide, cyanate resin, photo-imageable material, and other like materials. Some of these dielectric materials may also be defined as of the high temperature kind, meaning that such a layer can withstand temperatures greater than about 350 degrees C. for a time period long enough to enable successful lamination of the layer with other layers/substrates, usually a period of about two hours, without the dielectric material breaking down into low molecular weight fragments. One example of such material known today is sold under the product name RO2800 dielectric material by Rogers Corporation, Rogers, Conn. RO2800 is a trademark of Rogers Corporation. The material for the conductive layers, which may be power, signal and/or ground layers, may be copper or copper alloy, but may further include or be comprised of additional metals such as nickel, aluminum, gold, etc. or alloys thereof.

(8) By the term conducting polymer as used herein to define one of the elements of the solder paste compositions taught herein is meant a polymer material which is electrically conductive by itself, without the addition of other electrically conductive materials. Examples of such materials are described below.

(9) By the term conductive paste as used herein is meant an electrically conductive paste composition adapted for use in openings of substrates as well as between conductors which form parts of conductive planes of such a substrate. Examples of such conductive pastes are defined below.

(10) By the term electrical assembly is meant at least one circuitized substrate as defined herein in combination with at least one electrical component (defined below) electrically coupled thereto and forming part of the assembly. Examples of known such assemblies include chip carriers which include one or more semiconductor chips as the electrical components, the chips usually positioned on the substrate and coupled to wiring (e.g., pads) on the substrate's outer surface or to internal conductors using one or more thru-holes. Another example is a printed circuit board.

(11) By the term electrical component as used herein is meant components such as semiconductor chips and the like which are adapted for being positioned on the external conductive surfaces of circuitized substrates and electrically coupled to the substrate for passing signals from the component into the substrate whereupon such signals may be passed on to other components, including those mounted also on the substrate, as well as other components such as those of a larger electrical system which the substrate forms part of. This term is broad enough to encompass a chip carrier, because a chip carrier is also adapted for being positioned on and electrically coupled to a printed circuit board.

(12) By the term information handling system as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc.

(13) By the term micro-particles as used herein to define various particles within the compositions of this invention is meant particles having an average size of from about one micron (1,000 nanometers) to about fifty microns (50,000 nanometers).

(14) By the term nano-particles as used herein to define various particles within the compositions of this invention is meant particles with an average size of from less than about 0.01 micron (ten nanometers) to about one micron (1,000 nanometers).

(15) By the term organic as used herein to define one of the elements of the paste compositions defined herein is meant either a polymer or monomer material, a preferred example being epoxy resin of the same type used in present PCB dielectric layers.

(16) By the term sintering as used herein is meant to define a process of fusing or welding or growth of adjacent surfaces of particles in a powder by heating the powder to a temperature below the melting-point of the particles.

(17) The term thru-hole is defined in the above Background.

(18) FIGS. 1-4 illustrate the steps of making a circuitized substrate according to one aspect of the invention. In FIG. 1, a conductive layer 21, preferably a copper sheet, is etched (e.g., using an etching solution including cupric chloride) to define a plurality of openings 23 therein. Although only two openings are depicted in FIG. 1, this is meant to be representative only. In one example, a total of 2500 openings may be provided within a rectangular layer having dimensions of about 52.5 millimeters (mm) wide by about 52.5 mm long, and a thickness of about 0.0356 mm. Openings 23, in the embodiment shown here, are meant to form clearance openings in the finished substrate, such that conductive openings (thru-holes, as defined above) may be formed within the substrate and extend through the substrate without electrically contacting the conductive layer 21. Clearance openings are known in the PCB art and further definition is not deemed necessary. Layer 21 is preferred in the invention to provide an interim conductive layer which may be used as power or ground for some of the circuitry of the circuitized substrate of this invention. As will be defined below, at least one thru-hole to be used in the substrate will be electrically connected to layer 21, for this purpose.

(19) In FIG. 2, layer 21 is shown aligned with opposing dielectric layers 25 and 25, in addition to opposing conductive layers 27 and 27, these latter two conductive layers being oriented adjacent the outside surfaces of the respective dielectric layers 25 and 25, respectively. Layers 27 and 27 are also preferably copper and may possess the same dimensions as layer 21, although the thickness of said layers may be different than that of layer 21, with one example of such thickness being about 0.012 mm. In this embodiment (and also in other embodiments defined herein), each of the dielectric layers 25 and 25 is selected such that its melting temperature will be sufficiently high enough so as to allow sintering and, possibly, melting of the conductive paste (defined below) with the openings in these dielectric layers without melting the dielectric material itself. This represents an important aspect of the invention for reasons understood by the description below and elsewhere herein. In one embodiment, the dielectric material may be referred to as a high temperature dielectric layer, meaning that it can withstand temperatures greater than about 350 degrees C. for a time period long enough to enable successful lamination of the layers with other elements which are to form the substrate, or, in one embodiment, a multilayered substrate assembly comprised of two or more substrates laminated together. A preferred example of such material known today is the aforementioned RO2800 dielectric material sold by Rogers Corporation. RO2800 is a polytetrafluoroethylene (PTFE) composite material having a low dielectric constant and includes fused silica as one of the composition elements. It is rated with 0% water solubility and has a specific gravity of 2.1. Each layer 25 and 25 includes an initial thickness of about 0.05 mm. The aligned subassembly of FIG. 2 is now laminated together to form a sandwich, as now seen in FIG. 3. Conventional lamination processing and equipment may be used. In one example, the five layers shown in FIG. 2 may be laminated at a temperature of about 365 degrees C. using a pressure of about 2000 pounds per square inch (PSI) for a time period of about 125 minutes.

(20) Although the use of two dielectric layers and three conductive layers has been described, it is understood that in the broadest aspects of this invention, only one dielectric layer and two conductive layers are required, with the thru-hole connections to be formed herein (using the conductive pastes taught herein) designed to interconnect the two conductive layers through the interim dielectric layer. As also seen in FIG. 3, the laminating of the multiple layers of FIG. 2 in effect results in substantially single, combined dielectric layer due to the blending of both layers 25 and 25 during the lamination. As stated, the use of the interim conductive layer 21 adds more capability to the final substrate. The structure as shown in FIG. 3 may also be referred to as a core substrate, meaning that it may be aligned with and bonded to other substrates to form a multilayered substrate such as a PCB.

(21) The resulting laminated structure 31 is shown in FIG. 3. When compressed from the layers in FIG. 2 having the above initial thickness dimensions, the laminated structure 31 will possess a total thickness of about 0.160 mm. After lamination, a plurality of openings 33 are formed within structure 31, preferably using laser or mechanical drilling. In one example, a total of 5600 openings may be provided, each preferably having a diameter of about 0.050 mm. As mentioned above, the dielectric material of layers 25 and 25 has blended and thereby extended within the clearance openings 23 as a result of the lamination step, such that this combined (in this area) material now forms the side walls of the portion of the openings 33 located within layer 21. Further, it is noted that openings 23 have the conductive material of layers 27 and 27 for the walls in the outer portions of the laminated structure. FIG. 3 also shows that an opening 33 is formed within the structure at a location distant from the openings 23 such that the opening (to the right in FIG. 3) will physically contact middle conductive layer 21, as also mentioned above. Thus, this particular opening 33 will include side walls of conductive material at layer 21, unlike the other two openings to the left in FIG. 3. As explained below, this represents an alternative means of providing electrical coupling of selected elements of the invention.

(22) In FIG. 4, each of the openings 33 is plated, preferably with copper, to form inner conductive layers 35. Importantly, this is an optional step in making the substrate of the invention because it is possible to omit it and still provide conductive thru-holes here (by using the conductive paste defined below). The thin added plating is desired in some occasions to provide an even more enhanced connection. A preferred method of accomplishing the plating is to use a flash plating of electro-less copper. This plating process is typically comprised of four operations: cleaning; activation; acceleration; and deposition. During the cleaning phase, organic contaminants are removed from exposed metal surfaces. Activation includes a dip in a catalyst bath typically including hydrochloric acid and possibly tin or sodium chloride, and activation in a bath of hydrochloric acid, tin chloride and palladium chloride. The tin (Sn+2) ion reduces the palladium (Pd+2) to palladium, which is deposited on the substrate. Remaining Sn+2 and Sn+4 are selectively removed by an accelerator such as fluoboric or sulfuric acid with hydrazine. Key elements of the electro-less copper chemistry include sodium hydroxide, formaldehyde, EDTA (or other chelater) and a copper salt. During the complex reaction with the palladium as a catalyst, the formaldehyde reduces the copper ions to metallic copper. Each layer 35 has a thickness of only about 0.001 mm. It is seen in FIG. 4 that the plated opening to the right is electrically coupled to inner layer 21 because the plating is deposited on the exposed areas of layer 21. The plating of the other two openings to the left in FIG. 4 is in contact with the defined dielectric material of layers 25 and 25 in addition to the outer conductive layers 27 and 27. The right opening 33 is also in contact with the outer conductive layers 27 and 27. It is again to be understood that forming plated layers 35 is an optional step in forming a substrate as defined herein, but may be preferred in some circuit designs to further assure sound conductive paths in these portions of the structure.

(23) The next step, as also shown in FIG. 4, involves the deposition of conductive paste 41 within each of the plated openings. Such deposition may be accomplished using conventional paste printing processes or dispensing through convention needles. Significantly, the conductive paste as used in this embodiment includes a metal component including nano-particles. Metals which may form the nano-particles include copper, silver, gold, silver-coated copper, gold-coated copper, and alloys thereof. In one embodiment of the invention, a conductive paste having silver nano-particles may be used. Depending on the desired sintering (and, possibly, melting) temperature(s) desired to sinter (and, possibly, melt) the conductive paste and thereby form sound conductive paths through the paste, the conductive paste composition used herein may further include additional elements. Such elements may include micro-particles of metal (including silver), micro-particles of solder, and, in some situations, the addition of a conducting polymer and, even further, the addition of an organic. Several examples of the various compositions which may be used successfully herein are provided below. An important aspect of this invention, as understood, is that the conductive paste, once positioned with the respective opening, will be capable of undergoing a sintering phase in which selected ones of the nano-particles will sinter, thereby forming several contiguous circuit paths through the composition. In addition to sintering, the composition may also include elements (e.g., micro-particles of solder or a metal) which will melt to thereby form still further contiguous paths for circuit flow. Importantly, if these added elements are used, the melting is not to occur until at least sintering has begun and, possibly, after sintering has'been achieved. The result of this of course is the formation of both circuit paths formed by sintering and melting, thereby assuring an excellently conducting thru-hole due to the presence of the conductive paste therein.

(24) Suitable additional metal, including solder, elements for use in the compositions taught herein may be referred to as low melting point (LMP) metallurgies, and are mixed with the primary metal (e.g., silver or a silver-copper mixture) nano-particles. These include tin-lead, bismuth-tin, bismuth-tin-iron, tin, tin-silver, tin-gold, tin-silver-zinc, tin-silver-zinc-copper, tin-bismuth-silver, tin-copper, tin-copper-silver, tin-indium-silver, tin-antimony, tin-zinc, tin-zinc-indium, copper-based solders, and alloys thereof. These secondary LMP metallurgies include melting points greater than that of the primary metal and thereby melt, once the primary metal has effectively sintered, or these LMP metallurgies may begin melting during the sintering, depending on how close the melting point of same is relative to the corresponding melting point of the primary metal. A further understanding of this relationship is possible from the Examples and Table provided below.

(25) As further seen in the appended Examples and Table, some compositions taught herein may include a conducting polymer as part thereof. Acceptable conducting polymers include doped (or derivatives of) polyaniline, polypyrrole, polythiophene, and inherently conducting polymer. Such polymers are known in the art and further description is not considered needed.

(26) Still further, the compositions herein may include what is defined as an organic. As mentioned, one example of such an organic is epoxy resin. Others are possible.

(27) Finally, selected ones of the compositions are made using a solvent in order to form a slurry or ink of the composition and thus render is more suitable for needle dispensing or other form of precise deposition such as screen/stencil or ink jet printing. One specific example of a solvent usable herein is propylene glycol methyl ether acetate. Generally speaking, it was determined that when a conducting polymer was used, it some instances it was desirable to also use a solvent when the total organic content was less than about ten percent by weight of the composition.

(28) The following Table represents some examples of paste compositions which include the primary nano-particle metal silver combined in some examples with silver micro-particles and the resulting sintering temperature of same. To these particular compositions is added a suitable LMP metal which possesses a melting point greater than or even substantially the same as that of the corresponding primary metal(s). SAC is meant to be tin-silver-copper (SnAgCu), and in one more specific example, 96.5 percent by weight tin, 3 percent by weight silver and 0.5 percent by weight copper. Percentages shown are by weight, the silver being prior to addition of the LMP metallurgies.

(29) TABLE-US-00001 TABLE Suitable LMP Metallurgy Silver Composition (melting Point, degrees (particle size, Sintering Temperature Celsius - particle size, nanometers) (degrees Celsius) nanometers) Silver (5-10) 130 Tin-lead (183 - 10,000), tin (232 - 5,000), SAC (220 - 25,000) Silver (5000) -80% + 200 tin (232 - 5,000), Silver (15) - 20% SAC (220 - 25,000). Silver (5000) - 80% + 220 tin (232 - 5,000), Silver (15) - 10% + SAC (220 - 25,000). Silver (70) - 10% Silver (5000) -80% + 235-240 tin (232 - 5,000) Silver (70) Silver (5000) 350

(30) It is seen from this Table that the melting points of the LMP metallurgies is carefully selected so as to be greater than the corresponding sintering temperature of the silver (including the combined silvers), or, in some instances, substantially the same such that sintering of the silver will occur prior to or during melting of the LMP metallurgies. It is preferred that melting occurs after sintering to avoid possible sintering difficulties due to melt interference with the sintering process.

(31) It is also seen from this Table that sintering temperatures decrease with decreasing particle size. Further, the addition of nano-particles into powders including micro-particles also reduces overall sintering temperatures. The method defined in Example 3 below represents a new approach to combining both nano-particle and micro-particles.

(32) The above compositions and the Examples below are examples only and not intended to limit the scope of this invention. The following Examples also represent various combinations of conductive paste compositions, in addition to the processes used to prepare such paste compositions, according to various aspects of the invention.

Example 1

(33) Fifty grams (gm) of cycloaliphatic epoxy resin (e.g., one sold under product designation ERL-4211 by the Union Carbide Corporation, Danbury, Conn.) was mixed with about fifty gm of hexahydro-4-methylphthalic anhydride and 0.4 gm N, N dimethyl benzylamine. The mixed solution was stirred for ten minutes to assure uniform mixing. One gm of silver nano particles with average particle size fifteen nm and four gm of silver micro-particles with average particle size five microns was thoroughly mixed. Five gm of this mixed silver was added to one gm of the cycloaliphatic epoxy mixed solution and formed into a printable paste and a layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured paste (3 inch long and 0.003 square inch cross section area) measured about seven milliohms (m). Resistance of the paste after curing at 200 degrees C. for about two hours measured about 24 milliohms (m). A layer of this paste was also deposited on Cu foil and laminated at 200 degrees C. for 2 hrs. The mechanical strength of this laminate was about 2000 p.s.i. Resistance of four gm of this paste was added to another micro (average particle size 5 microns) filled silver epoxy system where the epoxy includes about 5% conducting polymer and formed into a printable paste. A layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured paste (three inch long and 0.003 square inch cross section area) measured about 27 milliohms (m). Resistance of the paste after curing at 200 degrees C. for about two hours measured about thirty-two milliohms (m). A layer of this paste was also deposited on Cu foil and laminated at 200 C. for two hrs. The mechanical strength of this laminate was about 3000 p.s.i.

Example 2

(34) Fifty grams (gm) of ERL-4211 epoxy resin was mixed with about fifty gm of hexahydro-4-methylphthalic anhydride and 0.4 gm N, N dimethyl benzylamine. The mixed solution was stirred for ten minutes to assure uniform mixing. Twenty gm of silver micro particles with average particle size five microns and five gm of silver nano particle having a D90 particle size of 0.07 micron (D90 meaning 90% of the particles have a diameter less than or equal to 0.07 micron) was thoroughly mixed. 25 gm of this mixed silver was added to four gm of the mixed cycloaliphatic epoxy mixed solution and formed into a printable paste. A layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured paste (three inch long and 0.003 square inch cross section area) measured about eighteen milliohms (m). Resistance of the paste after curing at 200 degrees C. for about three hours measured about 34 milliohms (m). A layer of this paste was also deposited on Cu foil and laminated at 200 degrees C. for two hrs. The mechanical strength of this laminate was about 1900 p.s.i. Four gm of this paste was added to a micro-particle (average particle size five microns) filled silver epoxy system where the epoxy contained 5% conducting polymer and formed into a printable paste. A layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured resistors (three inch long and 0.003 square inch cross section area) measured about 30 milliohms (m). Resistance of the paste after curing at 200 degrees C. for about three hours measured about 40 milliohms (m). A layer of this paste was also deposited on Cu foil and laminated at 200 degrees C. for 2 hrs. The mechanical strength of this laminate was about 2800 p.s.i.

Example 3

(35) Fifty gm of micro-particle silver were mixed with fifty gm silver nitrate solution and fifty gm soap solution and sonicated for sixty minutes. Fifty ml formaldehyde solution was added to the mixed silver solution and sonicated for additional ninety minutes and stirred for thirty minutes. The soap solution was used to reduce surface tension of the solution. Low surface tension solution will have better micro-particle silver dispersion. The silver nitrate was reduced to nano-particle sized silver colloids at room temperature by formaldehyde. Nano-particle sized silver with an average particle size of 50 nm was subsequently deposited uniformly at the surface of silver micro-particles. After completion of the chemical reduction, the suspension was washed with ethyl alcohol, which precipitated out the silver colloids. This washing step was repeated twice more to finally recover relatively pure silver nano-particle and micro-particle silver mixtures where silver nano-particles were uniformly distributed throughout the mixture. This mixed silver composition was air dried and heated at 125 degrees C. for one hour to remove residual organics from the mixture. The method defined in this Example 3 for incorporating nano-particles into a micro-particle composition represents a new method of doing so. As stated, this method involves the direct and uniform deposition of such nano-particles from solution onto the surfaces of the micro-particles (here, silver).

Example 4

(36) Fifty gm of ERL-4211 cycloaliphatic epoxy resin was mixed with about fifty gm of hexahydro-4-methylphthalic anhydride and 0.4 gm N, N dimethyl benzylamine. The mixed solution was stirred for ten minutes to assure uniform mixing. Ten gm of a silver nano-particle and micro-particle mixture (prepared in Example 3) and 0.5 gm of tin-silver-copper micro-particle (with average particle size ten microns) was added to two gm of the cycloaliphatic epoxy mixed solution and formed into a printable paste. A layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 265 degrees C. for about one hour. The resistance of the cured resistors (three inch long and 0.003 square inch cross section area) measured about ten milliohms (m).

Example 5

(37) Fifty gm of ERL-4211 cycloaliphatic epoxy resin was mixed with about fifty gm of hexahydro-4-methylphthalic anhydride and 0.4 gm N, N dimethyl benzylamine. The mixed solution was stirred for ten minutes to assure uniform mixing. Ten gm of a silver nano-particle and micro-particle mixture (prepared in Example 3) was added to two gm of the cycloaliphatic epoxy mixed solution and formed into a printable paste. A layer of this paste material was printed onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 265 degrees C. for about one hour. The resistance of the cured resistors (three inch long and 0.003 square inch cross section area) measured about 6.5 milliohms (m).

Example 6

(38) Eight gm SAC (Sn 95.5% by weight, Ag 3.9% by weight and Cu 0.6% by weight) paste was mixed with two gm silver nano-particles (average particle size 15 nm), four gm silver nano-particle (D90 particle size of 0.07 micron) and six gm micro-particle silver (average particle size five microns) was thoroughly mixed in methyl ethyl ketone (MEK) solvent. The sample was then air dried and one gm of PGMEA (propylene glycol methyl ether acetate) added to make a paste. A layer of this paste material was deposited onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured paste measured about eight milliohms (m). Four gm of this SAC-silver paste was mixed with 16.6 gm silver paste containing 90% by weight silver, 6% by weight epoxy and four % by weight PGMEA. This mixture contains 5% by weight conducting polymer. A layer of this paste material was deposited onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours. The resistance of the cured paste measured about 28 milliohms (m). Another layer of this paste material was deposited onto a copper substrate. This layer was then cured at approximately 200 degrees C. for about two hours and 240 degrees C. for about one hour. The resistance of the cured paste measured about nine milliohms (m).

Example 7

(39) A six mill thick dielectric with a twelve micron external copper layer was laser drilled to make fifty micron diameter holes, which were then filled with LMP-based conducting paste including ninety % by weight conducting filler (forty % by weight copper, forty % by weight tin and twenty % by weight tin-lead) eight % by weight epoxy and two % by weight PGMEA. This composition was then cured at 190 degrees C. for forty minutes. The dielectric with the cured paste was then dipped into a tin-lead electrolytic solution in an electroplating bath and stirred vigorously at 26 degrees C. A tin-lead rod was used as the anode and the dielectric with the cured paste was used as the cathode materials for the electroplating process. Around thirty amps per square foot of current were applied for tin-lead solder electroplating/coating of the copper surface. A thin layer of solder was deposited on the copper surface. The solder and copper coated cured conductive adhesive line was removed from the electrolytic solution and washed with water and air dried at room temperature.

Example 8

(40) A six mill thick dielectric with a twelve micron external copper layer was laser drilled to make fifty micron diameter holes, which were then filled with silver conducting paste containing eighty-eight % by weight silver micro-particles (average particle size being five microns) and twelve % by weight cycloaliphatic epoxy and then partially cured at 180 degrees C. for forty minutes. A thin layer of photo-resist was then applied, exposed, developed to expose the paste-filler holes. Dielectric with partially cured paste was then dipped into an immersion tin solution at sixty-five degrees C. The tin selectively coated only the exposed copper surface in the paste. A thin layer of tin was deposited on the copper surface. This tin-coated adhesive-filled substrate was then removed from the immersion tin solution and washed with water and air dried at room temperature. The photo-resist was stripped and the exposed, external copper was etched with ammoniacal solution.

(41) As understood, the function of the melted metallurgies (e.g., the solder micro-particles) is to provide an enhanced electrical connection through the paste in the final substrate structure. Significantly, the primary nano-particle metals as defined above will sinter and, if the additional LMP metallurgies are added, including possibly the additional conductive polymer (and, if desired, organic) these added LMP metallurgies will also melt during subsequent lamination procedures such as when the structure of FIG. 4 (or that of FIG. 5) is bonded to other dielectric and conductive layers, e.g., to form a larger, multilayered substrate such as a large PCB). The heat generated during such lamination is well known, and is necessary to adequately bond (laminate) the various layers together into such a thicker circuitized substrate. The elements of the paste composition will thus sinter and possibly melt form a series of interconnecting paths through the paste, thereby enhancing the connection formed. The dielectric layers of the structure are also not harmed because these layers have melting points greater than the sintering and melting temperatures and are able to withstand the lamination temperatures.

(42) It is also possible to deposit immersion tin, tin-lead, or a tin-gold coating on the outer, exposed surfaces of conductive paste 41 when the paste includes copper as its base component. The presence of such a coating (layer) aids in preventing copper etching which may occur during removal of outer conductive layers 27 and 27, thereby assuring the copper will maintain its desired conductivity as a result of the lamination.

(43) FIG. 5 represents an alternative structure 31 which may be formed from the substrate 31 of FIG. 4. As mentioned, substrate 31 may serve more effectively as an interconnecting substrate in which the conductive pastes will engage conductors on other substrates and thereby form a series of conducting paths from the coupled substrates. One example of such a formation is presented below in FIG. 6. This interim substrate 31 is thus able to provide a plurality of electrical connections through the paste using the sintered and possibly melt-formed electrical paths. Substrate 31 is similar to substrate 31 of FIG. 4 except that the outer conductive layers 27 and 27 (and the portions of the plated internal layers 35 on said layers 27 and 27) are removed. Such removal, preferably by etching, leaves portions of the conductive paste protruding externally of the substrate main body portion and thus more adaptable for engaging conductors of other substrates such as shown (and explained below) in FIG. 6. It should also be understood that the substrate 31 of FIG. 4 may serve as such an interconnecting structure, e.g., by providing interim sheets of dielectric (one example being known pre-preg dielectric) between substrate 31 and the other substrates, with openings formed therein to accommodate paste within the substrate's holes 41. When the substrates are laminated, this paste will move through the interim dielectric layers and into corresponding openings of the other substrate or against conductors or pads on the facing surfaces. Either way, effective connections are completed, using the paste as the interconnecting medium.

(44) FIG. 6 represents one example of a multilayered circuitized substrate assembly 51 according to one embodiment of the invention. Assembly 51 utilizes the circuitized substrate 31 of FIG. 5 as an interconnector to electrically couple two opposing substrates 53 and 55. Each substrate 53 and 55 may include at least one dielectric layer 57 (preferably two, including a second layer 57) with at least one conductive layer 61 (preferably two additional outer conductive layers 63 and 63 for each, one or both of these added layers being in the form of a signal layer having a plurality of electrical conductors 65 (in FIG. 6, these are preferably signal lines or pads) as part thereof. The dielectric material for each of the dielectric layers of the substrates 53 and 55 is preferably a high temperature dielectric and preferably the same material as that used for layers 25 and 25 of the interconnecting substrate 31 defined above. Substrates 53 and 55 may also include a plurality of thru-holes, including in the form of a PTH 71 or a blind via 71, for being electrically coupled to designated conductive elements of the substrates. The three substrates shown in FIG. 6 are aligned to assure subsequent electrical connection between corresponding conductive elements (especially between the projecting paste 41 segments and corresponding, facing conductive elements of the opposing substrates). For example, the paste 41 to the right of substrate 31 is shown to align with the corresponding lower conductor 65 on the undersurface of upper substrate 53, while the lower projecting segment of this same paste is aligned to connect to the upper conductive portion of a blind via (thru-hole) 71 located on the upper surface of the lower substrate 55. Such an upper conductive portion also understandably represents an electrical conductor such as the conductors 65 because it is capable of being engaged by paste and thus electrically coupled thereto. A sound electrical path is thus formed between the lower right pad 65 on upper substrate 53 and the inner conductive layer 61 of lower substrate 55 when the three substrates of FIG. 6 are laminated together. Several other electrical paths are readily discernible from the structure formed using these three substrates and further description is not considered necessary.

(45) The above lamination, using conventional lamination equipment, may be accomplished at temperatures and pressures known in the art, and, as stated, serves to sinter (and melt, if appropriate) the paste compositions in the manner defined. In one embodiment, lamination may be accomplished at a pressure within the range of from about 1700 PSI to about 2300 PSI for a total time period of about three hours. During this time period, the lamination temperature is raised from an initial ambient temperature of about 21 degrees C. to about 364 degrees C. in about 45 minutes and held at this elevated temperature for a period of about 125 minutes. The temperature is then decreased to about 260 degrees C. over a time period of about 100 minutes and then to a temperature of about 177 degrees C. over a period of the remaining minutes in the total time period defined above, after which it is dropped to the initial ambient temperature. This lamination procedure is deemed successful when laminating the substrates having the dielectric material and conductive paste defined above. Other temperatures, times and pressures will likely be required for alternative materials.

(46) The three substrate embodiment shown in FIG. 6 is representative only and not intended to limit the invention. It is within the scope of this invention to combine several additional substrates, including utilizing two or more interconnecting substrates as shown in FIG. 5 in combination with four or more substrates of the type represented by substrates 53 and 55, to form other multilayered assemblies having many additional conductive layers and thus operational capabilities. These additional substrates may be, understandably, also formed using the unique methodology taught herein. For example, substrate 53 may be formed by laminating two high temperature dielectric layers onto the interim conductive layer 61 (following clearance opening formation, if desired) and the thru-holes 71 and 71 then formed to the desired depths as shown. The outer circuit layers can be formed using conventional photolithographic processing known in the PCB art in which an outer copper layer is covered with a suitable photo-resist, the resist is developed to expose a pattern, and the structure is then etched to remove undesired (exposed) copper to produce the desired pattern. As stated, such processing is known and further explanation is not considered necessary. As explained above, the conductive paste may function as a conductive medium within a plated or non-plated opening with a designated dielectric layer (or layers). In addition, the paste may be used to simply couple electrical conductors on matching pairs of substrates. Such conductors may be formed using conventional photolithography processing, as mentioned, and serve as signal lines or pads for the layer-conductor sub-composite. These sub-composites are aligned with the respective conductors on a corresponding facing (e.g., first) surface thereof also facing one another. Conductive paste of the type defined herein is positioned between the facing conductors (e.g., using a needle dispenser or printing operation) by preferably applying it to one sub-composite (on the conductor(s) thereof). The sub-composites are then laminated using conventional equipment and a circuitized substrate is formed, this substrate thus including, at a minimum, the two conductors (preferably two conductive planes each including a plurality of such conductors) electrically coupled using the conductive paste taught herein. This structure will also include, as a minimum, the two dielectric layers which support the conductive planes, respectively, albeit the two blend essentially into one from the heat and pressure of the lamination. Other conductive and dielectric layers may also be added to form a thicker, multilayered structure.

(47) To produce an electrical assembly of the type defined above, a circuitized substrate as formed using the teachings herein is then coupled to one or more electrical components (e.g., a semiconductor chip). In one embodiment, such coupling may be accomplished using solder ball connectors and convention C-4 solder attach technology. C-4 stands for controlled collapse chip connection in which solder balls connect contact sites on the chip underside to conductors on the upper surface of the circuitized substrate. This form of connection is well known in the art and further explained below.

(48) FIG. 7 represents examples of such circuitized substrate electrical assemblies as taught herein in use within a larger electronic assembly 103. One assembly, referenced by the numeral 105, may form part of a larger chip carrier assembly 106, while the assembly represented by the numeral 107 may be a PCB, designed to have carrier assembly 106 positioned thereon and electrically coupled thereto. Therefore, each of the assemblies as taught herein may function in combination with other such assemblies and thus provide the enhanced conductive paste connections taught herein for a much larger structure. As mentioned above, each assembly includes one or more of the circuitized substrates taught herein. For example, the substrate assembly 105 for carrier 106 may be of the construction of the assembly formed in FIG. 6. In this case, assembly 105 of chip carrier 106 is preferably mounted on and electrically coupled to PCB 107 using a plurality of the aforementioned solder balls 95 (preferably of conventional tin-lead composition), the chip carrier 106 in turn having a semiconductor chip 109 positioned thereon and electrically coupled to the upper portion of assembly 105 using a second plurality of solder balls 95 (also preferably of conventional tin-lead composition). In both cases, the outer pads (i.e., pads 65 on the upper surface of substrate 53) may function as solder pads designed for having a solder ball positioned thereon and reflowed once in position. The upper pads of underlying PCB 107 may provide a similar function to accommodate solder balls 95. If PCB 107 is of the same or similar construction as the structure of FIG. 6, the upper conductors 65 of substrate 53 may provide this function. The chip carrier assembly 106 may also include a heat sink 110 thermally coupled to the chip 109, e.g., using a thermally conductive paste 111, and positioned on the upper surface of the carrier by appropriate standoffs 113, as is known in the art. It is also within the abilities of those skilled in the art to utilize an encapsulant material (not shown) to substantially encase the chip and also to possibly eliminate the need for the heat sink if such an encapsulant material is used. Encapsulant material is also possible about the lower pluralities of solder balls 95. It is even further within the scope of the invention to couple chip 109 using conventional wire-bonding in which a plurality of fine wires (not shown) are bonded between chip conductor sites and corresponding conductor pads on the underlying substrate.

(49) In FIG. 8, there is shown an information handling system 121 which is preferably a personal computer, a mainframe computer or a computer server. Other types of information handling systems, including well-known products such as cell-phones, televisions, etc. known in the art may also utilize the teachings of this invention. The circuitized substrate assemblies formed in accordance with the teachings herein may be utilized in the system 121 as a PCB 107 (shown hidden) and/or a chip carrier 106 (also shown hidden). The circuitized substrate assemblies may be utilized as a motherboard in system 121 or as one or more individual PCBs typically utilized in such systems. As is known, computer and the like systems 121 are usually contained within a suitable metal or insulative housing such as shown by the numeral 123, with appropriate venting (if desired) therein, as well as instrumentation externally accessible for system operation by the system's designated operator. The remaining elements of information handling systems of these types are known in the art and further description is not believed necessary.

(50) Thus there has been shown and described a circuitized substrate in which highly effective electrical connections are made possible through the use of a new and unique conductive paste formulation which utilizes a metallic component including nano-particles and possibly other metal micro-particles (as well as possibly conducting polymer materials and an organic material such as epoxy resin) as part thereof. The substrates as taught herein include dielectric materials with melting points substantially similar or greater than the sintering and melting points of the conductive paste, to assure sintering and possibly melting will occur as a result of lamination. Various embodiments of such substrates may be combined together to form a larger, multilayered substrate assembly which can be utilized in such electronic structures as information handling systems. Such systems are thus able to benefit by the unique, advantageous features of this invention. Still further, the formation of sintered paste compositions as well as both sintered and melted compositions has resulted in compositions which reduces the resistance of the electrical paths therein, but also the formation of robust and reliable electrical joints.

(51) While there have been shown and described what are at present considered the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. The invention as defined herein is also capable of transmitting both regular and high speed (frequency) signals, the latter at a rate of from about one Gigabits/sec to about ten Gigabits/second, while substantially preventing impedance disruption. It is also capable of being produced using many conventional PCB processes so as to assure reduced cost and facilitate ease of manufacture. That is, the preferred method for assembling the circuitized substrate of the invention preferably involves the use of conventional lamination equipment and processes as part of the method in which the dielectric layers, having the designated circuitry and/or conductive elements (planes) thereon or within, are stacked up in aligned manner with one another and subjected to relatively high pressures and temperatures for defined time periods.