Organic light emitting display device and manufacturing method thereof

Abstract

A method of manufacturing an organic light emitting display device can include sequentially forming first and second metal films on a substrate, forming a gate electrode, a first storage electrode and a pad in a thin film transistor region, a storage capacitor region and a pad region, respectively, forming a gate insulation film forming a channel layer opposite to the gate electrode, forming an insulation film, forming an etch stopper on the channel layer and first through third contact holes exposing the gate electrode, the first storage electrode and the pad, forming source and drain electrodes, and a second storage electrode on the gate insulation film opposite to the first storage electrode, forming a third storage electrode overlapping the second storage electrode with a passivation film therebetween, forming color filters in respective pixel regions, and forming an organic light emitting diode electrically connected to the third storage electrode.

Claims

1. A method of manufacturing an organic light emitting display device, the method comprising: sequentially forming a first metal film and a second metal film on a substrate and performing a mask procedure for the first and second metal films, to form a gate electrode, a first storage electrode and a pad in a thin film transistor region, a storage capacitor region and a pad region, respectively; forming a gate insulation film on the substrate provided with the gate electrode; forming a channel layer on the gate insulation film opposite to the gate electrode; forming an insulation film on the substrate provided with the channel layer; forming an etch stopper disposed on the channel layer and first through third contact holes configured to exposing the gate electrode, the first storage electrode and the pad using another mask procedure; forming a source electrode and a drain electrode, which are disposed on the substrate provided with the etch stopper, and a second storage electrode disposed on the gate insulation film opposite to the first storage electrode within the storage capacitor region; fanning a third storage electrode which overlaps the second storage electrode with a passivation film therebetween and is connected to the drain electrode; forming red, green and blue color filters in respective pixel regions of the substrate; and forming an organic light emitting diode which is formed on the substrate provided with the color filters and includes a first electrode electrically connected to the third storage electrode, an organic emission layer formed on the first electrode and a second electrode fanned on the organic emission layer.

2. The method of claim 1, wherein the second metal film is formed from a conductive oxide semiconductor.

3. The method of claim 2, wherein the conductive oxide semiconductor is one of indium gallium zinc oxide IGZO, zinc oxide ZnO and titanium oxide TiO.

4. The method of claim 1, wherein the first metal film includes at least two metal layers.

5. The method of claim 1, wherein the first metal film is formed in a single layer which is formed from one of an alloy of molybdenum and titanium MoTi, aluminum Al, an aluminum alloy, tungsten W, copper Cu, nickel Ni, chromium Cr, molybdenum Mo, titanium Ti, platinum Pt and tantalum Ta.

6. The method of claim 1, further comprising performing a heat treatment process after the etch stopper is formed.

7. The method of claim 1, further comprising performing a heat treatment process to the etch stopper before the source and drain electrodes are formed.

8. The method of claim 1, wherein the first metal film is formed in a double layered structure configured with stacked metal layers which are each formed from one of a molybdenum-titanium alloy MoTi, aluminum Al, an aluminum alloy, tungsten W, copper Cu, nickel Ni, chromium Cr, molybdenum Mo, titanium Ti, platinum Pt and tantalum Ta.

9. The method of claim 1, wherein the gate electrode, the first storage electrode and the pad each include an upper surface layer which is formed from a conductive oxide and used as a barrier layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the embodiments and are incorporated herein and constitute a part of this application, illustrate embodiment(s) of the present invention and together with the description serve to explain embodiments of the invention. In the drawings:

(2) FIG. 1A is a cross-sectional view showing an etch stopper and a contact hole formed through the same mask procedure in a related art method of manufacturing of an OLED device;

(3) FIG. 1B is a cross-sectional view illustrating a heat treatment process of the related art OLED device manufacture method being performed after the formation of an etch stopper;

(4) FIGS. 2A through 2K are cross-sectional views illustrating an OLED manufacture method according to an embodiment of the present invention;

(5) FIGS. 3A through 3D are cross-sectional views illustrating in detail a procedure of manufacturing a gate electrode, a storage electrode and pads of an OLED device according to an embodiment of the present invention; and

(6) FIGS. 4A and 4B are data sheets comparatively illustrating characteristics of an element in accordance with performing time points of a heat treatment process for an etch stopper which is included in an OLED device of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(7) Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. These embodiments introduced hereinafter are provided as examples in order to convey their spirits to the ordinary skilled person in the art. Therefore, these embodiments might be embodied in a different manner, so that they are not limited to these embodiments described here. Also, the size and thickness of the device might be exaggerated for the sake of convenience in the drawings. Wherever possible, the same reference numbers will be used throughout this disclosure including the drawings to refer to the same or like parts.

(8) FIGS. 2A through 2K are cross-sectional views illustrating an OLED manufacture method according to an embodiment of the present invention.

(9) Referring to FIGS. 2A through 2K, the OLED device manufacture method according to an embodiment of the invention forms a gate electrode 101 on a substrate 100. The substrate 100 is formed from a transparent insulation material. The gate electrode 101 can be prepared by forming a gate metal film on the substrate 100 and performing a first mask procedure for the gate metal film. At the same time, not only is a first storage electrode 131 formed on the substrate 100 opposite to a storage capacitor region but also a pad 170 is formed on the substrate 100 opposite to a pad region. The pad 170 can be a pad for one of a gate line, a data line and a power supply line.

(10) The gate metal film can include at least two metal films.

(11) For example, the gate metal film can be formed in a triple layered structure including sequentially stacked first through third metal layers. The first metal layer can be formed from a molybdenum alloy such as molybdenum-titanium MoTi. The second metal layer can be formed from an opaque conductive material with a low resistance. For example, the second metal layer can be foamed from one of aluminum Al, an aluminum alloy, tungsten W, copper Cu, nickel Ni, chromium Cr, molybdenum Mo, titanium Ti, platinum Pt, and tantalum Ta. The third metal layer can be formed from a conductive oxide semiconductor or a metal oxide. The conductive oxide semiconductor can be one of indium-gallium-zinc-oxide IGZO, zinc oxide ZnO, and titanium oxide TiO. The metal oxide can be one of indium-tin-oxide ITO and indium-zinc-oxide IZO.

(12) Alternatively, the gate electrode 101, the first storage electrode 131 and the pad 170 can be formed in a double layered structure which includes a first metal layer formed from an opaque conductive material with a low resistance and a second metal layer formed from one of a conductive oxide semiconductor and a metal oxide. The opaque conductive material of the low resistance can be one of a molybdenum-titanium alloy, aluminum Al, an aluminum alloy, tungsten W, copper Cu, nickel Ni, chromium Cr, molybdenum Mo, titanium Ti, platinum Pt, tantalum Ta and alloys thereof. The conductive oxide semiconductor can be one of indium-gallium-zinc-oxide IGZO, zinc oxide ZnO and titanium oxide TiO. The metal oxide can be one of indium-tin-oxide ITO, indium-zinc-oxide IZO and indium-tin-zinc-oxide ITZO.

(13) In this instance, the gate electrode 101 is configured with a gate electrode pattern 101a and a gate barrier layer 101b as shown in FIG. 3B. Similarly, the first storage electrode 131 is configured with a storage electrode pattern 131a and a storage barrier layer 131b, and the pad 170 is configured with a pad electrode pattern 170a and a pad barrier layer 170b.

(14) In other words, the gate electrode 101, the storage electrode 131 and the pad 170 are each covered with a barrier layer which is formed from an oxide semiconductor.

(15) After the gate electrode 101, the first storage electrode 131 and the pad 170 are formed on the substrate 100 as described above, a gate insulation film 102 is formed on the entire surface of the above-mentioned substrate 100 as shown in FIG. 2B. Also, a channel layer 104 is formed on the gate insulation film 102 opposite to the gate electrode 101.

(16) The gate insulation film 102 can be formed from a silicon oxide SiOx and in a single layer structure. Alternatively, the gate insulation film 102 can be formed in a multi-layered structure by alternately depositing a silicon nitride SiNx and a silicon oxide SiOx.

(17) The channel layer 104 can be a semiconductor layer including a crystalline silicon layer and an ohmic contact layer. Alternatively, the channel layer 104 can be formed from an oxide semiconductor layer.

(18) The oxide semiconductor layer can be formed from an amorphous oxide which includes at least one of Indium In, zinc Zn, gallium Ga and hafnium Hf. For example, if the oxide semiconductor layer is formed from the oxide semiconductor of GaInZnO through a sputtering process, three targets formed of In.sub.2O.sub.3, Ga.sub.2O.sub.3 and ZnO or a single target formed from GaInZn oxide can be used in the sputtering process. Alternatively, the oxide semiconductor layer can be formed through the sputtering process which uses either three targets formed from HfO.sub.2, In.sub.2O.sub.3 and ZnO or a single target formed from HfInZn oxide.

(19) When the channel layer 104 is formed on the gate insulation film 102 as described above, an etch stopper 106 is formed on the channel layer 104 as shown in FIG. 2C. The etch stopper 106 can be prepared by depositing an insulation layer on the entire surface of the above-mentioned substrate 100 and then performing a mask procedure for the insulation layer.

(20) At this time, contact holes partially exposing the gate electrode 101, the first storage electrode 131 and the pad 170 are simultaneously formed. As such, the OLED device manufacture method can reduce the number of mask procedures.

(21) Subsequently, a heat treatment process is performed for the etch stopper 106 in order to harden the etch stopper 106. During the formation of the etch stopper 106 in the related art, the gate electrode 101, the storage electrode 131 and the pad 170, which are exposed through the contact holes, are damaged due to an etching process and the heat treatment process. This results from the fact that the gate electrode 101, the storage electrode 131 and the pad are not covered with any barrier layer in the related art.

(22) In contrast, the gate electrode 101, the storage electrode 131 and the pad 170 of the present invention can be covered with barrier layers formed from a conductive oxide semiconductor. As such, the gate electrode 101, the storage electrode 131 and the pad 170 are not damaged during the formation of the etch stopper 106.

(23) When the etch stopper 106 is formed on the substrate 100 as described above, a source electrode 107a and a drain electrode 107b are formed at both ends of the channel layer 104 by forming a source/drain metal film on the entire surface of the above-mentioned substrate 100 and then performing a mask procedure for the source/drain metal film, as shown in FIG. 2D. In accordance therewith, a thin film transistor is completed. The drain electrode 107b is electrically connected to the storage electrode 131 through the respective contact hole. Such a thin film transistor can be one of a switching transistor and a driving transistor formed in a pixel region of the OLED device.

(24) Also, a connective portion 201 is formed into the contact hole exposing a part of the gate electrode 101. A second storage electrode 132 is formed on the gate insulation film 102 opposite to the first storage electrode 131. A first pad contact layer 171 is formed into the respective contact hole exposing a part of the pad 170.

(25) In addition, a data line and a power supply line can be simultaneously formed when the source/drain electrodes 107a and 107b are formed.

(26) The source/drain metal film can be formed from an opaque conductive material with a low resistance. For example, the source/drain metal film can be formed from one of aluminum Al, an aluminum alloy, tungsten W, copper Cu, nickel Ni, chromium Cr, molybdenum Mo, titanium Ti, platinum Pt, tantalum Ta and so on. Alternatively, the source/drain metal film can be formed in a double layered structure which includes a stacked transparent conductive material layer and an opaque conductive material layer. The transparent conductive material layer can be formed from indium-tin-oxide ITO and indium-zinc-oxide IZO.

(27) After the source electrode 107a and the drain electrode 107b are formed on the substrate 100, a passivation film 112 can be formed on the entire surface of the above-mentioned substrate 100 as shown in FIG. 2E. Also, contact holes exposing the first connective portion 201 in contact with the gate electrode 101, the drain electrode in contact with the first storage electrode 131 and the first pad contact layer 171 in contact with the pad 170 are formed in the passivation film by performing a mask procedure for the passivation film 112.

(28) Afterward, a metal film is formed on the substrate provided with the contact holes, and a mask procedure is performed for the metal film. As such, a second connective portion 203 is stacked on the first connective portion 201, a third storage electrode 133 is disposed on the passivation film opposite to the second storage electrode 132, and a second pad contact layer 172 is stacked on the first pad contact layer 171 as shown in FIG. 2F.

(29) The second connective portion 203 can be connected to a gate electrode of a different transistor which is formed in the respective pixel region. The different transistor can be one of another switching transistor and a driving transistor.

(30) The third storage electrode 133 overlaps with the first and second storage electrodes 131 and 132. Also, the third storage electrode 133 is electrically connected to the drain electrode 107b.

(31) Thereafter, a red color filter 238 is formed in a pixel region by coating a red color resin on the above-mentioned substrate and then performing light exposure and development processes for the coated red color resin. Also, a red color filter 239 is formed on the above-mentioned substrate 100 opposite to the thin film transistor occupying a non-display region, as shown in FIG. 2H.

(32) In the same way, a green color filter and a blue color filter are sequentially formed on the above-mentioned substrate 100 opposite to the thin film transistors occupying different non-display regions.

(33) Also, an overcoat layer 212 is formed on the entire surface of the substrate 100 provided with the color filters. The overcoat layer 212 can be used to planarize the upper surface of the substrate 100.

(34) Subsequently, a first electrode 129 and a third pad contact layer 173 are formed by depositing a transparent conductive material on the entire surface of the above-mentioned substrate 100 and then performing a mask procedure for the deposited transparent conductive material, as shown in FIG. 2I. The first electrode 129 is formed on the overcoat layer 212 opposite to the red color filter 238, and the third pad contact layer 173 is formed on the second pad contact layer 172.

(35) If the OLED device is a bottom emission mode OLED device, the first electrode 129 can be used as a cathode electrode.

(36) After the first electrode 129 is formed on the pixel region of the above-mentioned substrate 100 as described above, a bank layer 260 is formed by forming an insulation layer on the entire surface of the above-mentioned substrate 100 and then performing a mask procedure for the insulation layer, as shown in FIG. 2J. The bank layer 260 exposes the respective sub-pixel region. As such, the first electrode 129 corresponding to a sub-pixel region size is exposed through the bank layer 260.

(37) Also, an organic emission layer 221 is formed on the exposed surface of the first electrode 129. Moreover, a second electrode 223 is formed on the entire surface of the substrate 100 provided with the organic emission layer 221, as shown in FIG. 2J. In accordance therewith, an organic light emitting diode OL configured with the first and second electrodes 129 and 223 and the organic emission layer 221 is completed.

(38) The organic emission layer 221 can include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL and an electron injection layer EIL. An electron blocking layer EBL is included in the hole transport layer HTL. The electron transport layer ETL is formed from a low molecular material. For example, the electron transport layer ETL can be formed from one of PBD, TAZ, Alq3, BAlq, TPBI and Bepp2.

(39) The emission layer EML of the organic emission layer 221 can emit color light in accordance with the formation material of the emission layer EML. In order to realize full color, red, green and blue emission layers can be formed in respective sub-pixel regions. Alternatively, the emission layer EML can become a white emission layer which is formed by stacking red, green and blue organic materials.

(40) As the color filters are formed in the sub-pixel regions, the emission layer EML of the present invention can emit white light.

(41) Thereafter, a capping film 350 is attached on the above-mentioned substrate 100 using an adhesive layer 320 as shown in FIG. 2K.

(42) In this way, the OLED device manufacture method of the present invention can allow a barrier layer of a conductive oxide semiconductor to be formed on the gate metal film which is formed on the substrate. As such, damage to the gate electrode, the storage electrode and the pad during the manufacture procedure can be prevented.

(43) Also, the OLED device manufacture method of the present invention can enable the barrier layer of a conductive oxide semiconductor to be formed on the gate electrode, the storage electrode and the pad which are formed on the substrate. In accordance therewith, the number of mask procedures can be reduced and reliability of the elements can be enhanced.

(44) FIGS. 3A through 3D are cross-sectional views illustrating in detail a procedure of manufacturing a gate electrode, a storage electrode 131 and pads of an OLED device according to an embodiment of the present invention.

(45) Referring to FIGS. 3A through 3D, a gate electrode 101, a storage electrode and a pad 170 can be foamed by sequentially forming a first metal film ML1 and a second metal film ML2 on a substrate and then performing a mask procedure for the first and second metal films ML1 and ML2.

(46) The first metal film ML1 can be formed to have a single metal layer or two metal layers. The second metal film ML2 can be formed from an oxide semiconductor with a conductive property. Preferably, the oxide semiconductor is a material with an oxygen partial pressure of 0%.

(47) As shown in FIG. 3B, the gate electrode 101 is configured with a gate electrode pattern 101a and a gate barrier layer 101b. The first storage electrode 131 is configured with a storage electrode pattern 131a and a storage barrier layer 131b. The pad 170 is configured with a pad pattern 170a and a pad barrier layer 170b.

(48) The gate electrode pattern 101a, the storage electrode pattern 131a and the pad pattern 170a can be formed to each have a single metal layer. Alternatively, the gate electrode pattern 101a, the storage electrode pattern 131a and the pad pattern 170a can be formed in a double layered structure which includes stacked two metal layers.

(49) Upper surfaces of the gate electrode pattern 101a, the storage electrode pattern 131a and the pad pattern 170a can be covered with barrier layers which are formed from an oxide semiconductor. In other words, the upper surface layers of the gate electrode 101, the first storage electrode 131 and the pad 170 are formed from an oxide semiconductor and used as barrier layers.

(50) After the gate electrode pattern 101a, the storage electrode pattern 131a and the pad pattern 170a are formed on the substrate 100 as described above, a gate insulation film 102 can be formed on the entire surface of the above-mentioned substrate 100 as shown in FIG. 3C. Also, a channel layer 104 can be formed on the gate insulation film 102 opposite to the gate electrode 101.

(51) Thereafter, an etch stopper 106 can be formed on the channel layer 104 by forming an insulation layer on the entire surface of the substrate 100 provided with the channel layer 104 and then performing a mask procedure for the insulation layer, as shown in FIG. 3D.

(52) At the same time, the present invention can allow first through third contact holes C1, C2 and C3 partially exposing the gate electrode 101, the storage electrode 131 and the pad 170 to be simultaneously formed together with the etch stopper 106. As such, the number of mask procedures used in the OLED device manufacture method of the present invention can be reduced.

(53) Subsequently, a heat treatment process can be performed for the entire surface of the substrate 100 including the etch stopper 106, in order to harden the etch stopper 106. When the etch stopper 106 is hardened, the gate electrode 101, the storage electrode 131 and the pad 170 can be externally exposed by the first through third contact holes C1, C2 and C3.

(54) However, the present invention enables the upper surfaces of the gate electrode 101, the storage electrode 131 and the pad 170 to be covered with the respective barrier layers 101b, 1311b and 170b which are formed from an oxide semiconductor with a conductive property. As such, the gate electrode 101, the storage electrode 131 and the pad 170 are not damaged during an etching process and the heat treatment process.

(55) FIGS. 4A and 4B are data sheets comparatively illustrating characteristics of an element in accordance with performing time points of a heat treatment process for an etch stopper which is included an OLED device of the present invention.

(56) The formation procedure of the etch stopper includes a heat treatment process. In more detail, the etch stopper can be formed by depositing the insulation layer and performing the heat treatment process for the insulation layer before the etching process of the insulation layer, as described in FIGS. 3A through 3D. Alternatively, the etch stopper can be formed by depositing the insulation layer and etching the insulation layer before the heat treatment process of the patterned etch stopper. In other words, the heat treatment process is performed before or after the etching process in the formation of the etch stopper.

(57) FIG. 4A illustrates a threshold voltage property of a transistor when the etch stopper is formed by depositing the insulation layer on the substrate and performing the heat treatment process before the etching process. In this instance, the transistor has a deviation of the threshold voltage Vth corresponding to about 1.0V (42.0V) as shown in FIG. 4A. Due to this, reliability of the transistor cannot satisfy a desired degree.

(58) However, if the etch stopper is formed by depositing the insulation layer and patterning the insulation layer through the etching process before the heat treatment process, the transistor has a threshold voltage property as illustrated in FIG. 4B. Referring to FIG. 4B, the transistor has a deviation of the threshold voltage Vth corresponding to about 0.72V (1.52V). As such, it is evident that the transistor secures superior reliability.

(59) In this way, the present invention can allow the heat treatment process to be performed after the formation of the etch stopper. As such, the etch stopper and the contact holes can be formed through a single (or the same) mask procedure. In accordance therewith, not only reliability of the elements can be enhanced but also the number of mask procedures can be reduced.

(60) Also, the OLED device manufacture method of the present invention can allow a barrier layer of a conductive oxide semiconductor to be formed on the gate metal film which is formed on the substrate. As such, damage to the gate electrode, the storage electrode and the pad during the manufacture procedure can be prevented.

(61) Moreover, the OLED device manufacture method of the present invention can enable the barrier layer of a conductive oxide semiconductor to be formed on the gate electrode, the storage electrode and the pad which are formed on the substrate. In accordance therewith, the number of mask procedures can be reduced and reliability of the elements can be enhanced.

(62) Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the invention, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.