ULTRA-SHORT CHANNEL LENGTHS IN SIC MOS-BASED POWER DEVICES AND METHOD OF MAKING THE SAME

Abstract

A metal oxide semiconductor based power device in 4H-SiC semiconductor includes a semiconductor region, a drain electrode disposed adjacent a drain region and a source electrode disposed adjacent a source region which is disposed over a base region, and a gate electrode separated from the semiconductor region by silicon dioxide as a dielectric material. To avoid punchthrough, when the channel has a length of between i) about 0.5 m and about 0.4 m, ii) about 0.4 m and about 0.3 m, iii) about 0.3 m and about 0.2 m, or iv) about 0.2 m and about 0.1 m, the silicon dioxide has a corresponding thickness range of between i) about 5 nm to about 25 nm, ii) about 5 nm to about 20 nm, iii) about 5 nm to about 15 nm, or iv) about 5 nm to about 10 nm, respectively each base region at a predetermined doping profile.

Claims

1. A metal oxide semiconductor (MOS)-based power device in 4H-SiC semiconductor, comprising: a semiconductor region; a drain electrode disposed adjacent a drain region and a source electrode disposed adjacent a source region, the source region disposed over a base region; a gate electrode separated from the semiconductor region by silicon dioxide as a dielectric material, wherein a load current passing through the drain and source electrodes is controlled by an electric field induced by the gate electrode into the semiconductor region thereby forming a conductive channel; wherein to avoid punchthrough, defined as depletion region of the pn junctions on either side of the base region reaching through the base region and merging thus allowing a substantial current flow through the source electrode when the device is in an off state: when the channel has a length of between about 0.5 m and about 0.4 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 25 nm, and the base region has a first predetermined doping profile, when the channel has a length of between about 0.4 m and about 0.3 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 20 nm, the base region has a second predetermined doping profile, when the channel has a length of between about 0.3 m and about 0.2 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 15 nm, the base region has a third predetermined doping profile, and when the channel has a length of between about 0.2 m and about 0.1 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 10 nm, the base region has a fourth predetermined doping profile, such that the first, second, third and fourth predetermined doping profiles each with its associated channel length provides a near minimum specific on resistance for a prescribed blocking voltage.

2. The MOS-based power device of claim 1, wherein material of the drain, source, and gate electrodes comprises one or more of copper, silver, gold, carbon, graphite, nickel, titanium, aluminum, polysilicon, and graphene.

3. The MOS-based power device of claim 1, wherein the semiconductor region comprises an N-type conductivity type and a P-type conductivity type.

4. The MOS-based power device of claim 1, wherein the semiconductor region comprises a first semiconductor region, a second semiconductor region, and a third semiconductor region.

5. The MOS-based power device of claim 4, wherein the first semiconductor region has a dopant level higher than a dopant level of the second semiconductor region.

6. The MOS-based power device of claim 5, wherein the third semiconductor region has a dopant level higher than a dopant level of the second semiconductor region.

7. The MOS-based power device of claim 1, wherein the electric field induced by the gate electrode is based on application of a gate-to-source voltage (V.sub.GS) established based on thickness of the dielectric material.

8. The MOS-based power device of claim 7, wherein V.sub.GS is expressed as a function of the thickness of the dielectric material based on:
E.sub.ins=(V.sub.GS.sub.GS2.sub.F)/t.sub.ins E.sub.ins is the electric field in the dielectric material induced by the gate electrode, .sub.GS is a work function difference between the gate material and the semiconductor in the channel region in volts, .sub.F is the bulk Fermi potential of the semiconductor material in the channel region (determined by its doping) in volts, and t.sub.ins is the thickness of the dielectric material between the gate and the semiconductor in centimeters.

9. The MOS-based power device of claim 1, wherein the device is a planar MOS field effect transistor (MOSFET), a DMOSFET, a trench MOSFET, a lateral MOSFET, a planar superjunction MOSFET, a trench superjunction MOSFET, a planar insulated-gate bipolar transistor, a trench insulated-gate bipolar transistor, a planar MOS-controlled thyristor, or a trench MOS-controlled thyristor.

10. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.5 m and about 0.4 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 20 nm.

11. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.5 m and about 0.4 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 15 nm.

12. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.5 m and about 0.4 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 10 nm.

13. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.4 m and about 0.3 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 15 nm.

14. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.4 m and about 0.3 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 10 nm.

15. The MOS-based power device of claim 1, wherein when the channel has a length of between about 0.3 m and about 0.2 m, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 10 nm.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0020] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0021] FIG. 1A is a symbolic representation of a power device, e.g., a power metal oxide semiconductor field effect transistor (MOSFET).

[0022] FIG. 1B is a schematic of the MOSFET of FIG. 1A with a load.

[0023] FIG. 2 is a cross sectional view of a MOS power device, and in particular a double-diffused or double-implanted MOS field effect transistor (DMOSFET).

[0024] FIG. 3 is a cross sectional view of a UMOSFET.

[0025] FIG. 4 is simulation results of a planar power MOSFET device depicting various structures, with dimensions provided only as a non-limiting example.

[0026] FIG. 5 is a partial reproduction of FIG. 4 and a graph of base region p-type doping concentration vs. depth in m is shown in FIG. 4 across a section identified as A-A. This figure shows several different doping profile options that were simulated.

[0027] FIGS. 6-8 are simulation results showing electric field profile at punchthrough (FIG. 6), electron current density at punchthrough (FIG. 7), and hole current density at punchthrough (FIG. 8). In each case the channel length was 0.25 m and the long doping profile from FIG. 5 was used.

[0028] FIGS. 9-11 are simulation results showing electric field profile at avalanche breakdown (FIG. 9), electron current density at avalanche breakdown (FIG. 10), and hole current density at avalanche breakdown (FIG. 11) for the doping profile shown in FIG. 5. In each case the channel length was 0.25 m and the short1 doping profile from FIG. 5 was used.

[0029] FIG. 12 provides graphs of breakdown voltages in V vs. channel length in m and specific on-resistance in *m.Math.cm.sup.2 vs. channel length in m, depicting different concentration base doping profiles, labeled long, short1, short2, short3, and short4.

DETAILED DESCRIPTION

[0030] For the purposes of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the drawings, and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of this disclosure is thereby intended.

[0031] In the present disclosure, the term about can allow for a degree of variability in a value or range, for example, within 15%, within 10%, within 5%, or within 1% of a stated value or of a stated limit of a range.

[0032] In the present disclosure, the term substantially can allow for a degree of variability in a value or range, for example, within 85%, within 90%, within 95%, or within 99% of a stated value or of a stated limit of a range.

[0033] A novel power device arrangement is provided herein that improves the on-resistance without sacrificing normal operational parameters such as threshold voltage and blocking voltage and without increasing cell area or overall device area. Specifically the novel arrangement avoids punchthrough for ultra-short channel lengths used for ultra-low on-resistance metal oxide semiconductor (MOS)-based power devices.

[0034] To demonstrate this phenomenon, reference is made to FIG. 4 in which is a simulation result from a power MOSFET device, in particular a DMOSFET, depicting various structures, with dimensions provided only as a non-limiting example. The device provides a MOSFET structure with a polysilicon gate disposed under an interlayer dielectric (ILD) over the source region, the base region, and the JFET region. Various structures, such as the JFET length (L.sub.JFET), channel length (L.sub.CH), gate-to-source length (L.sub.GS), ILD thickness (t.sub.ILD) which also describes a gate to source electrode gap, source length (L.sub.source), base contact length (LBC), polysilicon gate thickness (t.sub.poly), oxide thickness (t.sub.ox), thickness of the JFET region plus an optional current spreading layer (t.sub.JFET), thickness disposed between the drift region and the base region, and thickness of the substrate (t.sub.sub), which are all known to a person having ordinary skill in the art are shown in FIG. 4 along with example values shown in Table 1 for each such parameter.

TABLE-US-00001 TABLE 1 Example values for parameters shown in FIG. 4 Simulation Parameters L.sub.JFET 0.75 m L.sub.CH Varied L.sub.GS 0.5 m L.sub.source 2.0 m L.sub.BC 1.0 m t.sub.ILD 0.5 m t.sub.poly 0.5 m t.sub.ox Varied t.sub.JFET 0.75 m t.sub.drift 5.2 m t.sub.sub (not important to the simulation, but 1.0 m was simulated) N.sub.D, JFET 1 10.sup.17 cm.sup.3 N.sub.D, drift 2.5 10.sup.16 cm.sup.3 N.sub.D, sub 1 10.sup.19 cm.sup.3 N.sub.D, gate 1 10.sup.20 cm.sup.3 t.sub.base 0.6 m t.sub.source 0.3 m
The gate oxide is SiO.sub.2.

[0035] Referring to FIG. 5, an example base region doping profile (i.e., doping concentration in cm.sup.3 vs. depth in m) is provided for some of the regions of the structure depicted in FIG. 4, specifically across a section A-A shown in FIG. 5. This doping profile is an example of the profiles typically used in SiC power MOSFETs, as is known to a person having ordinary skill in the art. Five different configurations are provided in the base doping profile shown in FIG. 5, including long, short1, short2, short3, and short4. The long profile represents a typical current state-of-the-art DMOSET retrograde base doping profile, with a near-surface doping chosen to give a low threshold voltage for the MOSFET, and the higher doping below the surface designed to prevent punchthrough at the bottom of the base in the blocking state. Those labeled short1 through short4 represent options more appropriate for a short channel DMOSFET. These Al implant profiles are the sum of various sequential ion implantation profiles calculated based on the Janson model (M. S. Janson et al., Ion implantation range distributions in silicon carbide, J. Appl. Phys., vol. 93, no. 11, pp. 8903-8909, 2003). The higher doping concentration in the near surface region of the short profiles reduces the penetration of the depletion region from the JFET side of the base region as the drain voltage is increased. When this depletion region significantly overlaps with the depletion region from the source side of the base region, punchthrough occurs. For a sufficiently high near surface base doping concentration, punchthrough will be suppressed, and the off-state drain voltage will be limited by avalanche breakdown rather than punchthrough. Referring to FIG. 12, further discussed below, a graph of blocking voltage in V vs. channel length in m for the doping profiles of FIG. 5 is provided, using the parameter values in Table 1. The blocking voltage represents an important parameter when the device is off. The channel length was varied from about 0.2 m to about 0.5 m. As it is clear from FIG. 12, the blocking voltage degrades quickly when the channel length has reduced to below 0.3 m in this example if the long profile from FIG. 5 is used. Thus, from FIG. 12 it can be deduced for the parameters shown in Table 1 and the long doping profile shown in FIG. 5, the minimum channel length is about 0.3 m before the structure exhibits punchthrough.

[0036] In each case presented in FIG. 12, the oxide thickness t.sub.ox is 12.5 m. As illustrated in FIG. 7, which shows a contour plot of simulated electron current density throughout a device with a 0.25 m channel length, the long doping profile from FIG. 5, and with an applied drain voltage near breakdown, the degradation in blocking voltage for channel lengths below about 0.3 m is due to punchthrough of the drain depletion region through the portion of the p base between the JFET region and the source as the channel length is reduced. This is evidenced in FIG. 7, discussed further below, by the continuous electron current flow from the source, through the base region well below the oxide-semiconductor interface, through the drift region and into the drain contact.

[0037] Channel length can be beneficially shortened by reducing the oxide thickness t.sub.OX and the on-state gate voltage V.sub.GS in such a way as to maintain a specified oxide field E.sub.REL. The value of E.sub.REL is chosen to achieve the desired long-term reliability of the MOSFET at the rated drain voltage and maximum rated junction temperature. The relationship is given by:

V.sub.GS=E.sub.RELt.sub.OX+.sub.GS+2.sub.F(1)

where .sub.GS is the gate-to-semiconductor work function, and
.sub.F is the Fermi potential of the semiconductor base region at the surface. We performed 2-D numerical simulations of the planar MOSFET of FIG. 2 and, as discussed above, we find there is a lower limit to the channel length before punchthrough of the base occurs below the surface. FIGS. 6-8 show the electric field magnitude, electron current density, and hole current density at the onset of punchthrough for a channel length of 0.25 m and an oxide thickness of 12.5 nm with the gate and base grounded and the drain at 490 V.sub.GS. Specifically, FIG. 6 (electric field profile at punchthrough) shows the highest electric field occurs at the interior corner of the grounded base, FIG. 7 (electron current density at punchthrough) shows electron current streaming from the n+ source through the narrowest portion of the base and down to the positive drain terminal, and FIG. 8 (hole current density at punchthrough) shows minimal hole current. It should be understood that if the current had been due to avalanche breakdown instead of punchthrough, we would see electron current flowing only downward from the high-field point and hole current flowing laterally from the high-field point, across the base and into the base contact at the right. A closer look at the electron current path in FIG. 7 reveals that punchthrough is occurring below the surface. Thus the surface channel remains turned off due to improved gate control provided by the thin oxide, but the doping immediately below the surface of the base is insufficient to prevent punchthrough in this region. It occurred to the present inventors that it might be possible to prevent sub-surface punchthrough by increasing the doping of the p-base in the region closer to the surface where punchthrough is taking place.

[0038] When the doping level of the base at the oxide/semiconductor interface is increased, this causes an undesirable increase in the threshold voltage of the MOSFET. In order to adjust the threshold voltage to a desired value while still preventing punchthrough, the inventors propose to include a threshold adjust implant in the upper portion of the base. To reduce the threshold voltage, this implant will be of the opposite doping polarity from the base region below, e.g. an N-type implant if the base is P-type, or a P-type implant if the base is N-type. To increase the threshold voltage, this implant will be of the same doping polarity as the base region below, e.g. an N-type implant if the base is N-type, or a P-type implant if the base is P-type. The implant will be very shallow in depth, extending from the surface only a small fraction of the source region thickness. Typical N-type dopants used in SiC are nitrogen (N) or phosphorus (P). Typical P-type dopants used in SiC are aluminum (Al) or boron (B).

[0039] The structure of simulations of FIGS. 6-8 (i.e., channel length of 0.25 m and an oxide thickness of 12.5 nm) was next simulated using the base doping profile short1, and the results are shown in FIGS. 9-11, which similar to FIGS. 6-8 provide electric field profile at breakdown, electron current at breakdown, and hole current at breakdown. With these higher doping profiles, the maximum drain voltage is now increased from the low value of 490 V in FIGS. 6-8 to a more desirable value of 748 V, and the current flow is now due to avalanche breakdown rather than punchthrough. Specifically, this change can be seen in FIGS. 10 and 11, where the electron current flows from the high-field location only downward to the drain and an equal hole current flows from the high-field location laterally across the base to the base contact. This is the unmistakable signature of avalanche breakdown.

[0040] Referring back to FIG. 5 and further to FIG. 12 which provides graphs of breakdown voltages in V vs. channel length in m and specific on-resistance in *m.Math.cm.sup.2 vs. channel length in m, we have also investigated other base doping profiles with increased near-surface doping concentrations, labeled short1, short2, and short4, discussed above, and these allow us to use successively shorter channels that further reduce the specific on-resistance. Thus, to prevent punchthrough and drain induced barrier lowering (DIBL) from occurring at the surface one can use one or more of i) higher doping in the base regions of the short-channel SiC power MOSFETs, and ii) the use of thin gate oxides and correspondingly reduced drive voltages; and to prevent punchthrough from occurring below the surface one can use higher doping in the base regions of the short-channel SiC power MOSFETs. The benefits are reduced channel length, leading to a reduced resistance-area product that allows manufacturers to place more transistor die on a wafer, thereby reducing cost without compromising performance, ruggedness, or reliability. This approach can be applied to a variety of MOS-based power devices in SiC, including (but not limited to) planar MOSFETs, trench MOSFETs, lateral MOSFETs, planar and trench superjunction MOSFETs, tri-gate MOSFETs, superjunction tri-gate MOSFETs, planar and trench insulated-gate bipolar transistors (IGBTs), and planar and trench MOS-controlled thyristors (MCTs).

[0041] Additionally, disclosed herein is a method of adjusting the threshold voltage to a desired value while still preventing punchthrough, which includes establishing a threshold adjust implant in the upper portion of the base. To reduce the threshold voltage, this implant will be of the opposite doping polarity from the base region below, e.g. an N-type implant if the base is P-type, or a P-type implant if the base is N-type. To increase the threshold voltage, this implant will be of the same doping polarity as the base region below, e.g. an N-type implant if the base is N-type, or a P-type implant if the base is P-type. The implant will be very shallow in depth, extending from the surface only a small fraction of the source region thickness. Typical N-type dopants used in SiC are nitrogen (N) or phosphorus (P). Typical P-type dopants used in SiC are aluminum (Al) or boron (B). Thus, to prevent punchthrough and DIBL from occurring at the surface one or more of the following methods can be used: i) establishing a higher doping in the base regions of the short-channel SiC power MOSFETs, and ii) providing a thin gate oxides and correspondingly reducing drive voltages; and to prevent punchthrough from occurring below the surface the following method can be used: establishing a higher doping in the base regions of the short-channel SiC power MOSFETs.

[0042] Those having ordinary skill in the art will recognize that numerous modifications can be made to the specific implementations described above. The implementations should not be limited to the particular limitations described. Other implementations may be possible. Those with ordinary skill in the art will also recognize that similar implementations can be applied in other wide bandgap semiconductors such as, but not limited to, gallium nitride (GaN) and its alloys and ternary compounds.