Method for manufacturing semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure having different filling layers. The method includes forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second layer, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias. The method further includes recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second. filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, the first etching rate and the second etching rate are different, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias; recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.

2. The method of claim 1, further comprising: forming a third filling layer of the multi-layer stack in the semiconductor substrate beneath the second filling layer, wherein the third filling layer has a third etching rate different from the second etching rate.

3. The method of claim 1, wherein the air void is formed in the location of the second filling layer and surrounded by dielectric filling material.

4. The method of claim 1, further comprising: forming an epitaxial semiconductor layer of the semiconductor substrate over an underlying substrate of the semiconductor substrate, wherein the multi-layer stack is formed in the underlying substrate, and the epitaxial semiconductor layer is thrilled between the multi-layer stack and the switch device.

5. The method of claim 4, further comprising: forming a well portion embedded in the epitaxial semiconductor layer, wherein the well portion is formed under the switch device and over the air void.

6. The method of claim 4, further comprising: forming an etch stop layer between the epitaxial semiconductor layer and the multi-layer stack.

7. The method of claim I, further comprising: forming two deep trench isolation portions in the semiconductor substrate, wherein the multi-layer stack is formed laterally between the deep trench isolation portions; and forming two shallow trench isolation portions in the semiconductor substrate and respectively above the deep trench isolation portions, wherein the switch device is formed laterally between the shallow trench isolation portions.

8. The method of claim 1, further comprising: forming a dielectric layer over the semiconductor substrate and surrounding the switch device.

9. The method of claim 1, further comprising: providing an underlying substrate of the semiconductor substrate before forming a multi-layer stack in the semiconductor substrate, wherein the underlying substrate has the two through vias; and forming two local trenches respectively under the two through vias.

10. The method of claim 9, further comprising: forming a global trench between the two local trenches in the underlying substrate of the semiconductor substrate; and filling the global trench and the two local trenches to firm the multi-layer stack in the underlying substrate of the semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

(2) FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

(3) FIGS. 2 to 7 are schematic views illustrating stages of manufacturing a semiconductor structure by the method of FIG. 1 in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

(4) The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

(5) Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

(6) FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor structure 200 in accordance with some embodiments of the present disclosure. FIGS. 2 to 7 are schematic views illustrating stages of manufacturing the semiconductor structure 200 by the method 100 of FIG. 1 in accordance with some embodiments of the present disclosure, In some embodiments, the method 100 of FIG. 1 for manufacturing the semiconductor structure 200 includes a number of operations (S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125 and S127), and the description and illustration below are not deemed as a limitation as the sequence of the operations.

(7) In operation S101, as shown in FIG. 2, an underlying substrate 212 of a semiconductor substrate 210 is provided. The underlying substrate 212 has two through vias 214. In some embodiments, a masking layer 261 is formed over the underlying substrate 212. The through vias 214 are formed through the masking layer 261 and extend into the underlying substrate 212.

(8) In some embodiments, the masking layer 261 may be deposited by a conventional deposition process, for example, a chemical vapor deposition (CVD) process. In some embodiments, the through vias 214 are formed through an anisotropic etching process to to remove portions below the through vias 214, for example, a wet etching process.

(9) In some embodiments, the masking layer 261 may be a hard mask including nitride material, oxide material or other masking material. In some embodiments, the underlying substrate 212 may be formed from a substrate such as a silicon substrate, an epitaxial substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate or the like. In some embodiments, the through vias 214 may be lined with a nitride, an oxide-based material, or another masking material.

(10) In operation S103, as shown in FIG. 2, an etch stop layer 220 is formed over the underlying substrate 212. In some embodiments, the etch stop layer 220 may be deposited using any conventional deposition method, for example, a chemical vapor deposition (CND) process. In some embodiments, the etch stop layer 220 may include silicon carbide (SiC) or silicon germanium (SiGe).

(11) In operation S105, as shown in FIG. 2, an epitaxial semiconductor layer 216 of the semiconductor substrate 210 is formed over the underlying substrate 212 of the semiconductor substrate 210. In some embodiments, the epitaxial semiconductor layer 216 is formed on the etch stop layer 220.

(12) In some embodiments, the etch stop layer 220 may be formed using any conventional deposition method, for example, a chemical vapor deposition (CVD) process. The epitaxial semiconductor layer 216 is grown on the etch stop layer 220. In this way, the etch stop layer 220 is formed between the underlying substrate 212 and the epitaxial semiconductor layer 216.

(13) In operation S107, as shown in FIG. 2, a well portion 218 is formed and embedded in the epitaxial semiconductor layer 216 after forming the epitaxial semiconductor layer 216 of the semiconductor substrate 210. In some embodiments, the well portion 218 may be formed in the epitaxial semiconductor layer 216 using a conventional ion implantation process, a doping process or other suitable well limning process.

(14) In some embodiments, the well portion 218 may be either a p-doped well portion or an n-doped well portion. Whether the well portion 218 is the p-doped well portion or the n-doped well portion depends on the type of the semiconductor, for example, an NFET or a PFET.

(15) In operation S109, as shown in FIG. 2, two deep trench isolation portions 244 are formed in the semiconductor substrate 210. More specifically, the two deep trench isolation portions 244 are formed in the underlying substrate 212. The two deep trench isolation portions 244 are formed at opposite sides of the well portion 218 to provide isolation from well charges producing harmonic distortion.

(16) In some embodiments, the two deep trench isolation portions 244 can be formed using a conventional etching process for deep trenches, for example, a conventional lithography process, followed by a deposition process for filling the deep trenches with oxide filling material, for example, a chemical vapor deposition or a physical vapor deposition process.

(17) In operation S111, as shown in FIG. 2, two shallow trench isolation portions 242 are formed in the semiconductor substrate 210 and respectively above the deep trench isolation portions 244. In some to embodiments, the two shallow trench isolation portions 242 are formed separate from the epitaxial semiconductor layer 216 and extend into the underlying substrate 212.

(18) In some embodiments, the two shallow trench isolation portions 242 may be formed using conventional lithography, etching and deposition processes. In some embodiments, the shallow trench isolation portions 242 include an oxide material or other suitable insulating material.

(19) In operation S113, as shown in FIG. 2, two local trenches 252 are formed under the two through vias 214, respectively. In some embodiments, the two local trenches 252 are formed separate from the etch stop layer 220 and extend into the underlying substrate 212. In some embodiments, the two local trenches 252 may be thrilled using conventional etching processes, such as wet etching processes or the like.

(20) In operation S115, as shown in FIG. 3, a global trench 254 is formed between the two local trenches 252 in the underlying substrate 212 of the semiconductor substrate 210. In sonic embodiments, the global trench 254 may be formed using conventional etching processes, such as wet etching processes or the like.

(21) In operation S117, as shown in FIG. 4, a multi-layer stack 230 is formed in the semiconductor substrate 210. In some embodiments, the global trench 254 is filled with multiple filling materials with different etching rates to form the multi-layer stack 230. In this way, the multi-layer stack 230 has a first layer 232 and a second filling layer 234 under the first filling layer 232. In some embodiments, a third filling layer 236 of the multi-layer stack 230 is formed in the semiconductor substrate 210 beneath the second filling layer 234.

(22) In some embodiments, as shown in FIG. 4, the multi-layer stack 230 is formed in the underlying substrate 212. The multi-layer stack 230 is formed laterally between the deep trench isolation portions 244. The etch stop layer 220 is formed between the epitaxial semiconductor layer 216 and the multi-layer stack 230. Two top portions of the multi-layer stack 230 are respectively exposed through the two through vias 214.

(23) As shown in FIG. 4, the first filling layer 232 has a first etching rate, the second filling layer 234 has a second etching rate, and the first etching rate and the second etching rate are different. In some embodiments, the third filling layer 236 has a third etching rate different from the second etching rate. In some embodiments, the first etching rate and the third etching rate are the same. In some embodiments, the second etching rate is greater than the first etching rate and the third etching rate. In some embodiments, the first filling layer 232, the second filling layer 234 and the third filling layer 236 have different materials or different densities.

(24) In operation S119, as shown in FIG. 5, the multi-layer stack 230 is recessed from the two through vias 214 to respectively form two blind holes 256 in the first filling layer 232 and the second filling layer 234. In some embodiments, the two blind holes 256 are formed through the first filling layer 232 and the second filling layer 234 into the third filling layer 236. In some embodiments, the multi-layer stack 230 may be formed using conventional etching processes, such as a wet etching processes or other suitable anisotropic etching processes.

(25) In operation S121, as shown in FIG. 6, the second filling layer 234 is selectively etched to form a global cavity 258 between the two blind holes 256 after forming the blind holes 256 in the first filling layer 232, the second filling layer 234 and the third filling layer 236.

(26) In some embodiments, the second etching rate of the second filling layer 234 is greater than the first etching rate of the first filling layer 232 and the third etching rate of the third filling layer 236, and therefore the second filling layer 234 is etched more quickly than other filling layers to form the global cavity 258 first. In some embodiments, the global cavity 258 may be formed using conventional etching processes, such as a wet etching process or other anisotropic etching processes.

(27) In operation S123, as shown in FIG. 7, the global cavity 258 and the two blind holes 256 are filled with dielectric filling material 240 so as to form an air void 238 in the multi-layer stack 230. The air void 238 is formed in the location of the second filling layer 234. In some embodiments, the air void 238 is surrounded by the dielectric filling material 240.

(28) In operation S125, as shown in FIG. 7, a switch device 260 is formed over the semiconductor substrate 210, wherein the air void 238 is formed under the switch device 260. The epitaxial semiconductor layer 216 is formed between the multi-layer stack 230 and the switch device 260. The well portion 218 is formed under the switch device 260 and over the air void 238. The switch device 260 is thrilled laterally between the shallow trench isolation portions 242.

(29) In operation S127, as shown in FIG. 7, a dielectric layer 262 is formed over the semiconductor substrate 210. The switch device 260 is surrounded by the dielectric layer 262.

(30) As shown in FIG. 7, the semiconductor structure 200 is provided. The semiconductor structure includes the semiconductor substrate 210, the multi-layer stack 230, the switch device 260, and the air void 238. The multi-layer stack 230 is buried in the semiconductor substrate 210. The multi-layer stack 230 includes the first filling layer 232 and the second filling layer 234 under the first filling layer 232, the first filling layer 232 has the first etching rate, the second filling layer 234 has the second etching rate, and the first etching rate and the second etching rate are different. The switch device 260 is disposed over the semiconductor substrate 210. The air void 238 is thrilled in the multi-laver stack 230 and under the switch device 260. The air void 238 is surrounded by the dielectric filling material 240. The multi-layer stack 230 further includes the third filling layer 236 disposed beneath the second filling layer 234. The third filling layer 236 has a third etching rate different from the second etching rate. The second etching rate is greater than the first etching rate and the third etching rate. The air void 238 is formed in the location of the second filling layer 234.

(31) As shown in FIG. 7, the second etching rate is greater than the first etching rate. The semiconductor substrate 210 includes the underlying substrate 212 and the epitaxial semiconductor layer 216 disposed over the underlying substrate 212. The multi-layer stack 230 is buried in the underlying substrate 212, and the epitaxial semiconductor layer 216 is disposed between the multi-layer stack 230 and the switch device 260.

(32) As shown in FIG. 7, the well portion 218 is embedded in the epitaxial semiconductor layer 216. The well portion 218 is disposed under the switch device 260 and over the air void 238, The etch stop layer 220 is disposed between the epitaxial semiconductor layer 216 and the multi-layer stack 230.

(33) As shown in FIG. 7, the two shallow trench isolation portions 242 are disposed in the semiconductor substrate 210. The switch device 260 is disposed laterally between the shallow trench isolation portions 242. The two deep trench isolation portions 244 are disposed in the semiconductor substrate 210 and respectively under the shallow trench isolation portions 242. The multi-layer stack 230 is disposed laterally between the deep trench isolation portions 244. The dielectric layer 262 is disposed over the semiconductor substrate 210 and surrounds the switch device 260.

(34) In conclusion, with the design of the semiconductor structure, the semiconductor structure has an air void thrilled in the semiconductor substrate. The air void can provide the switch device with better isolation effect, thereby helping the semiconductor structure reduce capacitance disturbance and raising the switching speed of the switch device over the air void.

(35) In addition, the semiconductor structure has multiple filling layers having different etching rates, which can facilitate the proper formation of the air void in the semiconductor structure.

(36) One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different, The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-laver stack and under the switch device. The air void is surrounded by dielectric filling material.

(37) Another aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes farming a multi-layer stack in the semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, the first etching rate and the second etching rate are different, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias; recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material so as to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.

(38) Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

(39) Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.