Field effect transistor and method for manufacturing semiconductor device

Abstract

A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode (102) including a conductor or a semiconductor and being enclosed by an insulator (104) is formed between a semiconductor layer (101) and a gate (105) so as to cross the semiconductor layer (101) and the floating electrode (102) is charged, whereby carriers are prevented from flowing from a source electrode (103a) or a drain electrode (103b). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer (101) and thus the zero current can be reduced.

Claims

1. A field effect transistor comprising: a semiconductor layer; first and second conductor electrodes in contact with a first surface of the semiconductor layer; a gate over the first surface or a second surface of the semiconductor layer; and a floating electrode between the semiconductor layer and the gate, wherein the floating electrode comprises a conductor or a semiconductor, is enclosed by an insulator, and is charged with a predetermined electric charge, wherein an amount of the predetermined electric charge in the floating electrode is not changed after charging, wherein the floating electrode is provided so as to cross the semiconductor layer, and wherein no PN junction exists in the field effect transistor.

2. A field effect transistor comprising: a semiconductor layer; first and second conductor electrodes in contact with a first surface of the semiconductor layer; a gate over the first surface or a second surface of the semiconductor layer; and a floating electrode between the semiconductor layer and the gate, wherein the floating electrode comprises a conductor or a semiconductor, is enclosed by an insulator, and is charged with a predetermined electric charge, wherein an amount of the predetermined electric charge in the floating electrode is not changed after charging, wherein the floating electrode is provided so as to cross the semiconductor layer, and wherein a conductor-semiconductor junction exists between each of the first and second conductor electrodes and the semiconductor layer.

3. The field effect transistor according to claim 1, wherein the semiconductor layer comprises an oxide in which a proportion of indium and zinc to all metal elements is 25% or higher.

4. The field effect transistor according to claim 2, wherein the semiconductor layer comprises an oxide in which a proportion of indium and zinc to all metal elements is 25% or higher.

5. The field effect transistor according to claim 1, wherein the semiconductor layer comprises an oxide having a bandgap greater than or equal to 3.0 eV and less than or equal to 4.5 eV.

6. The field effect transistor according to claim 2, wherein the semiconductor layer comprises an oxide having a bandgap greater than or equal to 3.0 eV and less than or equal to 4.5 eV.

7. The field effect transistor according to claim 1, wherein the semiconductor layer comprises a first doped region and a second doped region, wherein each of the first doped region and the second doped region includes a carrier at a higher concentration than the other region of the semiconductor layer, wherein the first doped region is in contact with the first conductor electrode, and wherein the second doped region is in contact with the second conductor electrode.

8. The field effect transistor according to claim 2, wherein the semiconductor layer comprises a first doped region and a second doped region, wherein each of the first doped region and the second doped region includes a carrier at a higher concentration than the other region of the semiconductor layer, wherein the first doped region is in contact with the first conductor electrode, and wherein the second doped region is in contact with the second conductor electrode.

9. The field effect transistor according to claim 7, wherein a carrier concentration of each of the first doped region and the second doped region is higher than or equal to 110.sup.18/cm.sup.3 and lower than 110.sup.21/cm.sup.3.

10. The field effect transistor according to claim 8, wherein a carrier concentration of each of the first doped region and the second doped region is higher than or equal to 110.sup.18/cm.sup.3 and lower than 110.sup.21/cm.sup.3.

11. A semiconductor device comprising: a transistor comprising a semiconductor and a gate with a region therebetween; and a cover with a light-blocking property over the transistor, wherein: the region is charged with an electric charge, the cover is provided after charging, and an amount of the electric charge in the region is not changed after charging.

12. A semiconductor device comprising: first and second transistors each comprising a semiconductor and a gate with a region therebetween; and a cover with a light-blocking property over the first and second transistors, wherein: the region of each of the first and second transistors is charged with an electric charge in order that characteristics of the first and second transistors be uniform, and the cover is provided after charging.

13. The semiconductor device according to claim 11, wherein the region comprises a conductor enclosed by an insulator.

14. The semiconductor device according to claim 12, wherein the region comprises a conductor enclosed by an insulator.

15. The semiconductor device according to claim 11, wherein the semiconductor comprises an oxide semiconductor containing indium, gallium and zinc.

16. The semiconductor device according to claim 12, wherein the semiconductor comprises an oxide semiconductor containing indium, gallium and zinc.

17. The semiconductor device according to claim 11, wherein: the semiconductor has a first surface and a second surface opposite to the first surface, a source and a drain of the transistor are in contact with the first surface, and the region is between the second surface and the gate.

18. The semiconductor device according to claim 12, wherein: the semiconductor has a first surface and a second surface opposite to the first surface, a source and a drain of each of the first and second transistors are in contact with the first surface, and the region is between the second surface and the gate.

19. A memory device comprising the semiconductor device according to claim 11.

20. A memory device comprising the semiconductor device according to claim 12.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In the accompanying drawings:

(2) FIGS. 1A to 1C illustrate an example of an FET of one embodiment of the present invention and a principle of operation thereof;

(3) FIGS. 2A to 2C illustrate an example of a conventional FET and operation thereof;

(4) FIGS. 3A to 3C illustrate an example of an FET of one embodiment of the present invention;

(5) FIGS. 4A to 4D illustrate a manufacturing process of an FET according to Embodiment 1;

(6) FIGS. 5A to 5D illustrate a manufacturing process of an FET according to Embodiment 1;

(7) FIGS. 6A to 6C illustrate a manufacturing process of an FET according to Embodiment 1;

(8) FIGS. 7A to 7D illustrate a manufacturing process of a semiconductor device including an FET, according to Embodiment 2;

(9) FIGS. 8A and 8B each illustrate a circuit of a semiconductor device including an FET, according to Embodiment 2; and

(10) FIGS. 9A to 9C illustrate a manufacturing process of a semiconductor device including an FET, according to Embodiment 3.

BEST MODE FOR CARRYING OUT THE INVENTION

(11) Hereinafter, embodiments of the present invention will be described in detail with reference to drawings. Note that the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details can be modified in various ways. Therefore, the present invention is not construed as being limited to the description of the embodiments below.

(12) The structures, the conditions, and the like disclosed in any of the following embodiments can be combined with those disclosed in other embodiments as appropriate. Note that in structures described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and detailed description thereof is not repeated in some cases.

(13) An oxide in this specification is a substance (including a compound) in which the proportion of nitrogen, oxygen, fluorine, sulfur, selenium, chlorine, bromine, tellurium, and iodine (in a molar ratio) is higher than or equal to 25% of the total and the proportion of oxygen to the above elements (in a molar ratio) is higher than or equal to 70%.

(14) A metal element in this specification refers to all elements other than a rare gas element, hydrogen, boron, carbon, nitrogen, a Group 16 element (e.g., oxygen), a Group 17 element (e.g., fluorine), silicon, phosphorus, germanium, arsenic, and antimony.

(15) ( Embodiment 1)

(16) This embodiment will be described with reference to FIGS. 4A to 4D, FIGS. 5A to 5D, and FIGS. 6A to 6C. First, a conductive film, an insulating film, and a conductive film are formed over a substrate 201 and are selectively etched, so that a gate 202, a first gate insulating film 203, and a floating electrode 204 are formed as illustrated in FIG. 4A. A variety of substrates can be given as examples of the substrate 201, but the substrate 201 needs to have such a property as to withstand subsequent treatment. Further, it is preferable that a surface of the substrate 201 has an insulating property. Accordingly, the substrate 201 is preferably a single insulator; an insulator, conductor, or semiconductor whose surface is provided with an insulating layer; or the like.

(17) As the insulator, various kinds of glasses, sapphire, quartz, ceramics, or the like can be used. As the conductor, aluminum, copper, stainless steel, silver, or the like can be used. As the semiconductor, silicon, germanium, silicon carbide, gallium nitride, or the like can be used. In this embodiment, barium borosilicate glass is used as the substrate 201.

(18) As a material for the gate 202, a conductor such as a variety of metal materials or a conductive oxide can be used. The gate 202 may be formed using such a material alone or may have a multilayer structure. In this embodiment, a 250-nm-thick multilayer film having a three-layer structure of titanium/aluminum/titanium formed by a sputtering method is used.

(19) Note that it is conventionally preferable to use a material with a high work function for a gate in terms of a reduction in the zero current. This is because a material with a high work function has a strong force for eliminating electrons in a semiconductor layer. In this embodiment, however, the floating electrode 204 is charged to be used and thus the work function of the gate 202 has little influence.

(20) In many cases, a material with a high work function has a problem of expensiveness, difficulty in deposition, poor conductivity, or the like and such a problem inhibits its practical use. In this embodiment, even with a material which is inexpensive, easily deposited, and excellent in conductivity, sufficiently low zero current can be obtained.

(21) As a material for the first gate insulating film 203, silicon oxide, aluminum oxide, aluminum nitride, hafnium oxide, lanthanum oxide, yttrium oxide, or the like can be used. It is preferable that the first gate insulating film 203 have such a thickness that electric charge does not leak from the floating electrode 204 when an FET is used later. In this embodiment, as a material for the first gate insulating film 203, silicon oxynitride deposited by a CVD method to a thickness of 30 nm to 100 nm is used.

(22) As a material for the floating electrode 204, a variety of conductive materials similar to that for the gate 202 can be used. In general, it is preferable to use, but not limited to, a material with a high work function. Note that some materials with a high work function do not have sufficient conductivity as described above; however, electrons move in a limited region of the floating electrode 204 (specifically, from one surface of the floating electrode to the opposite surface thereof), and thus such conductivity hardly causes a problem. In addition, the thickness of the floating electrode 204 may be 5 nm to 100 nm, preferably 10 nm to 30 nm.

(23) Further, as illustrated in FIG. 4A, a thick insulator 205 is formed to cover the gate 202, the first gate insulating film 203, and the floating electrode 204. The insulator 205 is preferably formed using a method and a material with which excellent step coverage is obtained. For example, silicon oxide, silicon nitride, silicon oxynitride, or the like deposited by a CVD method or a spin coating method may be used as a material for the insulator 205. In addition, the thickness of the insulator 205 needs to be larger than at least the sum of the thicknesses of the gate 202, the first gate insulating film 203, and the floating electrode 204.

(24) FIG. 6A illustrates a state where the FET whose cross section is illustrated in FIG. 4A is observed from the above. In FIGS. 6A to 6C, the insulator 205 is not illustrated. A cross section taken along X-X in FIG. 6A is illustrated in FIG. 4A, and a cross section taken along Y-Y in FIG. 6A is illustrated in FIG. 5A.

(25) Then, a surface is planarized by a chemical mechanical polishing (CMP) method, for example. This polishing is preferably performed until a surface of the floating electrode 204 is exposed. In the case where the insulator 205 is formed by a spin coating method and the surface is already flat enough, for example, the CMP method does not need to be used and the insulator 205 may be etched by a normal dry etching method until the surface of the floating electrode 204 is exposed. Thus, the gate 202, the first gate insulating film 203, and the floating electrode 204 are embedded in an insulator 205a.

(26) After that, as illustrated in FIG. 4B, a second gate insulating film 206, a semiconductor layer 207, and a protective insulating layer 208 are formed. These are formed over a sufficiently flat surface and therefore may be formed by a method with which the step coverage might become insufficient, such as a sputtering method. Further, the second gate insulating film 206, the semiconductor layer 207, and the protective insulating layer 208 need to be successively formed without the substrate 201 being exposed to the air during the formation. This is effective in preventing the semiconductor layer 207 from being exposed to the air, especially in preventing water vapor in the air from being absorbed by the semiconductor layer.

(27) Note that the second gate insulating film 206 and the protective insulating layer 208 may be formed using the material used for the first gate insulating film 203, and each preferably have a sufficiently low hydrogen concentration. Therefore, it is preferable that the concentration of hydrogen and a compound including hydrogen (such as water) in an atmosphere for the film formation be sufficiently low.

(28) The second gate insulating film 206 is preferably thin enough so that electric charge can be accumulated in the floating electrode 204 in a later step and thick enough so that electric charge does not leak from the floating electrode 204 when the FET is used later. In this embodiment, the thickness of the second gate insulating film 206 is 10 nm to 20 nm.

(29) The protective insulating layer 208 is preferably as thick as possible unless a problem with productivity occurs. In addition, it is preferable that excess oxygen exist in the protective insulating layer. In this embodiment, the protective insulating layer 208 has a thickness of 50 nm to 100 nm.

(30) As a material for the semiconductor layer 207, an oxide semiconductor including In or Ga is used. Other than the above oxide semiconductor, a variety of oxide semiconductors can be used. In this embodiment, an InGaZn-based oxide film with a thickness of 5 nm to 20 nm is formed by a sputtering method using an oxide target including In, Ga, and Zn at the same rate. It is preferable that the hydrogen concentration of the semiconductor layer 207 be sufficiently low. Therefore, it is preferable that the concentration of hydrogen and a compound including hydrogen (such as water vapor) in an atmosphere for the film formation be sufficiently low. FIG. 5B illustrates a cross section taken along Y-Y which is a cross section of the FET illustrated in FIG. 4B.

(31) After that, the floating electrode 204, the second gate insulating film 206, the semiconductor layer 207, and the protective insulating layer 208 are selectively etched. As a result of etching, the shape of each of them is changed, so that a floating electrode 204a, a second gate insulating film 206a, a semiconductor layer 207a, and a protective insulating layer 208a are formed. FIG. 6B is a top view of the FET at this time. FIG. 4C illustrates a cross section taken along X-X and FIG. 5C illustrates a cross section taken along Y-Y. Note that the first gate insulating film 203, the insulator 205a, the second gate insulating film 206a, and the protective insulating layer 208a are not illustrated in FIGS. 6A to 6C.

(32) The area and position of the semiconductor layer 207a are determined by this etching, and the etching is preferably performed in stages. A resist mask is formed over a portion serving as the semiconductor layer 207a so as to prevent the portion from being etched. First, the protective insulating layer 208, the semiconductor layer 207, and the second gate insulating film 206 are etched. They may be etched successively. By this etching, the second gate insulating film 206a, the semiconductor layer 207a, and the protective insulating layer 208a are formed, and the second gate insulating film 206a and the protective insulating layer 208a have substantially the same shape as the semiconductor layer 207a. In addition, part of the floating electrode 204 and part of the insulator 205a are exposed.

(33) Next, the floating electrode 204 is etched. This etching is performed under the condition where the floating electrode 204 is preferentially etched. As a result, the insulator 205a is hardly etched. By this etching, the floating electrode 204 is etched and only the floating electrode 204a is left under the semiconductor layer 207a.

(34) As seen in FIG. 6B, the floating electrode 204a is formed to have a shape aligned with the semiconductor layer 207a, that is, formed in a self-aligned manner; thus, the floating electrode 204a has substantially the same length as the semiconductor layer 207a in the channel width direction and overlaps with a region from one end of the semiconductor layer 207a to the other end thereof in the channel width direction. Such a structure is particularly effective in miniaturization.

(35) After the above etching step, or after formation of the semiconductor layer 207 and before the etching step, proper heat treatment is preferably performed once or plural times. This heat treatment is performed to reduce the hydrogen concentration or oxygen deficiency in the semiconductor layer 207 or the semiconductor layer 207a.

(36) After that, an interlayer insulator 209 is formed (see FIG. 4D and FIG. 5D). The interlayer insulator 209 is formed using a single-layer or multilayer insulator, and can be formed using an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride or an organic insulator such as polyimide, which is deposited by a sputtering method, a CVD method, a spin coating method, or the like.

(37) For example, a silicon oxide film with an extremely low hydrogen concentration may be formed to a thickness of 50 nm to 200 nm by a sputtering method first, and then a polyimide film may be formed to a thickness of 500 nm to 1 m by a spin coating method. A spin coating method is preferably used because a flat surface can be obtained.

(38) Next, as illustrated in FIG. 4D and FIG. 6C, contact holes 210a and 210b are formed in the interlayer insulator 209. Note that the interlayer insulator 209 is not illustrated in FIG. 6C. Then, a conductive film of metal or the like is formed and selectively etched, so that a source electrode 211a and a drain electrode 211b are formed.

(39) As a material used for the source electrode 211a and the drain electrode 211b, a variety of metal materials, a conductive oxide, and the like can be given. In the above manner, an FET including the floating electrode 204a is completed.

(40) (Embodiment 2)

(41) In this embodiment, a method for manufacturing a semiconductor circuit where an FET including silicon and an FET which is formed thereover and includes a different semiconductor layer and a floating electrode are provided will be described with reference to FIGS. 7A to 7D. First, with the use of a known technique for manufacturing a silicon MOSFET, an element isolation region 302 is formed in a silicon substrate 301, and a silicon FET including a gate insulating film 303, a gate 304, a source 306a, and a drain 306b is formed. The gate 304 may be provided with a sidewall as illustrated in the drawing. The gate 304 extends over the element isolation region. Further, silicide layers 305a and 305b may be provided on surfaces of the source 306a and the drain 306b in order to increase the conductivity (see FIG. 7A).

(42) After that, an insulator is formed and a surface thereof is polished by a CMP method, so that an insulator 307 with a flat surface is obtained. The CMP is preferably performed until a surface of the gate 304 is exposed. Further, an oxide semiconductor film is formed and etched, so that an oxide semiconductor layer 308 having a desired shape (e.g., an island shape) is formed (see FIG. 7B).

(43) Then, a contact hole reaching the source 306a is formed, a conductive film is formed, a surface of the conductive film is planarized, and then selective etching is performed; thus, a first electrode 309a and a second electrode 309b are formed. Further, an insulating film and a conductive film are formed and etched, so that a first gate insulating layer 310 and a floating electrode 311 are formed (see FIG. 7C). Note that the first gate insulating layer 310 in this embodiment corresponds to the second gate insulating film 206a in Embodiment 1.

(44) After that, a second gate insulating layer 312 is formed. A conductive film is formed and selectively etched, so that a wiring 313a and a wiring 313b are formed. The wiring 313a also serves as a gate of an FET 317 including an oxide semiconductor as a semiconductor layer. The wiring 313b is included in a capacitor 318 in which the second gate insulating layer 312 serves as a dielectric between the wiring 313b and the second electrode 309b (see FIG. 7D).

(45) Further, an interlayer insulator 314 is formed, a contact hole is formed therein, and a contact plug 315 reaching the first electrode 309a is embedded. A wiring connected to the contact plug 315 may be additionally provided. Through the above steps, a semiconductor circuit including a silicon MOSFET 316, the FET 317 including an oxide semiconductor, and the capacitor 318 is formed (see FIG. 7D).

(46) Such a semiconductor circuit can be applied to a memory element illustrated in FIG. 8A. This memory element includes two FETs 316 and 317 and one capacitor 318. The drawing illustrates a memory element in the n-th row and the m-th column.

(47) In writing data into the memory element, when the potential of a writing word line Q.sub.n is set to be high to turn on the FET 317 and data is given to a bit line R.sub.m at this time, electric charge for the data passes through the FET 317 and is accumulated in the capacitor 318.

(48) In reading data from the memory element, the potential of a reading word line P.sub.n is set to be an appropriate level, whereby the FET 316 is turned on or off depending on the amount of electric charge accumulated in the capacitor 318; thus, data can be read by comparison between the potential of the bit line R.sub.m and the potential of a source line S.sub.m.

(49) Thus, data is not lost in reading. Therefore, data can be semipermanently stored when the zero current of the FET 317 is sufficiently low. In order to obtain sufficiently low zero current, the floating electrode 311 is negatively charged. Accordingly, the zero current of the FET 317 can be 110.sup.21 A or lower, preferably 110.sup.24 A or lower, and data can be held for an extremely long time.

(50) In the memory element illustrated in FIG. 8A, data amplified by the FET 316 is read and thus the capacitance of the capacitor 318 can be 110.sup.16 F or lower, preferably 110.sup.17 F or lower; accordingly, the capacitor 318 can have a simple structure and a small area. For these reasons, the size of the memory element can be reduced as well and high integration can be achieved.

(51) On the other hand, in the case of using the capacitor 318 with such low capacitance, data might be instantly lost if the zero current of the FET 317 is high. As described above, given that the zero current of the FET 317 is 110.sup.21 A, data can be held for only 1 day when the capacitance of the capacitor 318 is 110.sup.16 F, and data can be held for only 3 hours when the capacitance is 110.sup.17 F. Given that the zero current is 110.sup.24 A, data can be held for 3 years when the capacitance of the capacitor 318 is 110.sup.16 F, and data can be held a little more than 100 days even when the capacitance is 110.sup.17 F. Moreover, given that the zero current is 110.sup.26 A, data can be held for as long as 31 years even when the capacitance of the capacitor 318 is 110.sup.17 F.

(52) Meanwhile, by applying the manufacturing process illustrated in FIGS. 7A to 7D, a DRAM-type memory element including one FET 317a and one capacitor 318a may be formed as illustrated in FIG. 8B. In this memory element, the capacitor 318a needs to have a capacitance of 110.sup.15 F or higher in terms of prevention of noise; therefore, a stacked capacitor is preferably used.

(53) Data writing is performed in the following manner data is given to the bit line R.sub.m when a high signal is supplied to the word line Q.sub.n to turn on the FET 317a, whereby electric charge is accumulated in the capacitor 318a. Data reading is performed in the following manner when a high signal is supplied to the word line Q.sub.n to turn on the FET 317a, the amount of electric charge released from the capacitor 318a to the bit line R.sub.m is measured. Note that a source line S.sub.n is kept at a constant potential in general, but may be supplied with a signal synchronized with that of the bit line R.sub.m or the word line Q.sub.n.

(54) Naturally, as the zero current of the FET 317a is lower, electric charge can be accumulated in the capacitor 318a for a longer time and thus data can be held for a longer time. For example, in the case where the capacitance of the capacitor 318a is 110.sup.15 F, data can be held for 11 days when the zero current of the FET 317a is 110.sup.24 A, and data can be held for 31 years or longer when the zero current is 110.sup.24 A or lower. In the latter case, substantially semipermanent data holding is possible.

(55) (Embodiment 3)

(56) A method for manufacturing an FET is described in Embodiment 1 or 2. In Embodiment 3, a method for accumulating electric charge in a floating electrode will be described with reference to FIGS. 9A to 9C. In this embodiment, a method for accumulating electric charge in a memory element like the one illustrated in FIG. 8A will be described. Note that RTr.sub.(n,m), WTr.sub.(n,m), and C.sub.(n,m) in the memory element in FIGS. 9A to 9C correspond to the FET 316, the FET 317, and the capacitor 318 in FIG. 8A, respectively.

(57) <FIG. 9A>

(58) After a semiconductor circuit including the memory element is completed, initial characteristics of the memory element are measured first. At this stage, a floating electrode of WTr.sub.(n,m) is not charged. Here, whether the memory element functions as a memory element is judged, and characteristics of the memory element are recorded.

(59) <FIG. 9B>

(60) At this stage, electric charge is accumulated in the floating electrode of WTr.sub.(n,m). The amount of electric charge accumulated in the floating electrode of WTr.sub.(n,m) can be controlled by a potential difference between a gate and a source electrode (or a drain electrode) of WTr.sub.(n,m). Specifically, by controlling a potential difference between the writing word line Q.sub.n and the bit line R.sub.m, electric charge accumulated in the floating electrode of WTr.sub.(n,m) of the memory element can be controlled. On the basis of results of the foregoing measurement, a proper amount of electric charge is accumulated in the floating electrode of WTr.sub.(n,m) of the memory element. Note that a sufficiently long time is ensured for accumulation of electric charge; therefore, an error in the amount of accumulated electric charge can be sufficiently reduced.

(61) <FIG. 9C>

(62) At this stage, characteristics of the memory element are measured again. When sufficient characteristics are obtained in a required number of memory elements, the semiconductor circuit is sealed with a resin or the like and packaged. If sufficient characteristics are not obtained in a required number of memory elements, a step of accumulating a proper amount of electric charge in the floating electrode is performed again on the basis of the measurement data.

(63) By repeating such a cycle, semiconductor circuits and semiconductor devices (memory devices) can be manufactured at a high rate of non-defective products. Electric charge is accumulated using high voltage above, and voltage used for the accumulation may be supplied from an external circuit.

(64) (Embodiment 4)

(65) The semiconductor devices described in Embodiments 1 to 3 can be used in a variety of electronic devices typified by a semiconductor memory. Examples of such an electronic device include televisions, personal computers, communication devices such as mobile phones, electronic notebooks, and portable music players.

EXPLANATION OF REFERENCE

(66) 101: semiconductor layer, 102: floating electrode, 103a: source electrode, 103b: drain electrode, 104: insulator, 105: gate, 111: I.sub.D-V.sub.G curve, 112: I.sub.D-V.sub.G curve, 113: I.sub.D-V.sub.G curve, 114: I.sub.D-V.sub.G curve, 115: I.sub.D-V.sub.G curve, 116: I.sub.D-V.sub.G curve, 201: substrate, 202: gate, 203: first gate insulating film, 204: floating electrode, 204a: floating electrode, 205: insulator, 205a: insulator, 206: second gate insulating film, 206a: second gate insulating film, 207: semiconductor layer, 207a: semiconductor layer, 208: protective insulating layer, 208a: protective insulating layer, 209: interlayer insulator, 210a: contact hole, 210b: contact hole, 211a: source electrode, 211b: drain electrode, 301: substrate, 302: element isolation region, 303: gate insulating film, 304: gate, 305a: silicide layer, 305b: silicide layer, 306a: source, 306b: drain, 307: insulator, 308: semiconductor layer, 309a: first electrode, 309b: second electrode, 310: first gate insulating layer, 311: floating electrode, 312: second gate insulating layer, 313a: wiring, 313b: wiring, 314: interlayer insulator, 315: contact plug, 316: FET, 317: FET, 317a: FET, 318: capacitor, and 318a: capacitor.

(67) This application is based on Japanese Patent Application serial no. 2010-197220 filed with the Japan Patent Office on Sep. 3, 2010, the entire contents of which are hereby incorporated by reference.