Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.

Claims

1. A semiconductor device comprising: a buried gate pattern formed in a substrate at a first level; a source/drain region formed in or over a substrate at a second level higher than the first level; a junction formed in the substrate and coupling the buried gate pattern to the source/drain region; and a semiconductor pattern holding impurities arranged in parallel to the junction and in contact with the junction.

2. The device of claim 1, wherein the semiconductor pattern holding impurities is a silicon pattern doped with n-type or p-type impurities.

3. The device of claim 1, wherein the junction extends between the first and the second levels.

4. The device of claim 1, wherein the junction includes dopants diffused from the semiconductor pattern comprising the impurities.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A to 1E are cross-sectional views illustrating a semiconductor device and a method for forming the same according to an embodiment of the present invention.

(2) FIGS. 2A to 2F are cross-sectional views illustrating a semiconductor device and a method for forming the same according to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

(3) Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

(4) FIGS. 1A to 1E are cross-sectional views illustrating a semiconductor device and a method for forming the same according to an embodiment of the present invention.

(5) Referring to FIG. 1A, a photoresist film is deposited over a semiconductor substrate 100, and an exposure process is carried out using a mask that defines an active region 110. Thereafter, a liner insulation film 105 and a spin on dielectric (SOD) material are buried in a trench formed by etching the exposed semiconductor substrate 100, and a device isolation film 120 defining the active region 110 is formed by performing a planarization etching process such as a chemical mechanical polishing (CMP) method.

(6) After a photoresist film (not shown) is formed over the active region 110 and the device isolation film 120, an exposure process is carried out using a mask defining a buried gate to etch the active region 110, resulting in formation of a recess 130. Preferably, the etching process for forming the recess 130 is an anisotropic etching process.

(7) Thereafter, an oxidation process or an oxide deposition process may be used to form a gate oxidation film 140.

(8) After a gate electrode material 150 is buried in the recess 130 in which the gate oxide film 140 is formed, the gate electrode material 150 and the gate oxide film 140 are etched back, resulting in formation of a buried gate. In this case, the gate electrode material 150 may include aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), and titanium nitride (TiN), or may include a laminated structure of titanium nitride (TiN) and tungsten (W).

(9) After forming the buried gate, N-type impurities are implanted into the active region 110 such that a source/drain junction 155 can be formed. Also, after forming the device isolation film 120, N-type impurities are implanted into the active region 110 such that a source/drain junction 155 can be formed.

(10) Referring to FIG. 1B, an insulation film 160 is formed over the gate electrode material 150 and the gate oxide film 140. In embodiments, the insulation film 160 may be formed by a selective oxidation process or a nitridation process.

(11) Referring to FIG. 1C, impurity-doped polysilicon 170 is formed over the insulation film 160, the device isolation film 120, and the active region 110.

(12) Referring to FIG. 1D, the polysilicon layer 170 doped with impurities is etched so that only portions of polysilicon pattern 175 disposed over sidewalls of the recess 130 remain.

(13) Referring to FIG. 1E, after a sealing insulation film 180 is buried between the polysilicon patterns 175 contained in the recess 130, an annealing process or a rapid thermal annealing (RTA) process is performed to diffuse impurities, so that a junction 190 is formed in the active region 110.

(14) FIGS. 2A to 2F are cross-sectional views illustrating a semiconductor device and a method for forming the same according to another embodiment of the present invention.

(15) Referring to FIG. 2A, a photoresist film is deposited over a semiconductor substrate 200, and an exposure process is carried out using a mask that defines an active region 210. Thereafter, a liner insulation film 105 and a spin on dielectric (SOD) material are buried in a trench formed by etching the exposed semiconductor substrate 200, and a device isolation film 220 defining the active region 210 is formed by performing a planarization etching process such as chemical mechanical polishing (CMP).

(16) After a photoresist film (not shown) is formed over the active region 210 and the device isolation film 220, an exposure process is carried out using a mask defining a buried gate or a recess gate to etch the active region 210, resulting in formation of a recess 230. The etching process for forming the recess 230 may be an anisotropic etching process.

(17) Thereafter, an oxidation film may be deposited over the recess 230, or a gate oxidation film 240 may be formed in the recess 230 using an oxidation process.

(18) A gate electrode material 250 is buried in the recess 230 in which the gate oxide film 240 is formed, and is etched back, so that a buried gate is formed. In an embodiment, the gate electrode material 250 may include aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), and titanium nitride (TiN), or may include a laminated structure of titanium nitride (TiN) and tungsten (W).

(19) After forming the buried gate, N-type impurities are implanted into the active region 210 such that a source/drain junction 255 can be formed. Also, after forming the device isolation film 220, N-type impurities are implanted into the active region 210 such that a source/drain junction 255 can be formed.

(20) Referring to FIG. 2B, an insulation film 260 is formed over the entire surface including the gate electrode material 250, the device isolation film 220, and the active region 210. The insulation film 260 may include an oxide film or a nitride film.

(21) Referring to FIG. 2C, the insulation film 260 formed over sidewalls of the recess 230 is removed, leaving an insulation film pattern 265 over the gate electrode material 250, the device isolation film 220, and the active region 210.

(22) Referring to FIG. 2D, impurity-doped polysilicon 270 is formed over the entire surface including the insulation film pattern 265 and the active region 210.

(23) Referring to FIG. 2E, the polysilicon layer 270 doped with impurities is etched so that a polysilicon pattern 275 is formed only over sidewalls of the recess 230.

(24) Referring to FIG. 2F, after a sealing insulation film 280 is buried between the polysilicon patterns 275 contained in the recess 230, an annealing process or a rapid thermal annealing (RTA) process is performed to diffuse impurities, so that a junction 290 is formed in the active region 210. The junction 290 is included in the active region 210 contained in a region contacting the polysilicon pattern 275.

(25) As is apparent from the above description, the semiconductor device and methods for manufacturing the same according to embodiments of the present invention include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities at a sidewall of a recess located over the gate electrode material, and a junction formed by using an annealing or a rapid thermal annealing (RTA) process, thereby adjusting a thickness of a junction 190 or 290 coupling a gate electrode of a buried gate and a source/drain region.

(26) The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.