RFID transponder and method for operating the same

Abstract

An RFID transponder having an analog front end receiver having an attenuator coupled to receive an RF-signal from an antenna and to attenuate the RF-signal, an amplifier having a fixed amplifier gain and being coupled to receive and to amplify the attenuated RF-signal and a control unit coupled to control a gain of the attenuator, wherein the control unit is configured to control the attenuator gain in response to a level of the amplified RF-signal, the control unit is configured to have a plurality of predetermined states causing the attenuator to increase (step-up) or to decrease (step-down), its gain by a predefined step size, wherein the step size of a step-up is equal to or smaller than the step size of a step-down and wherein the control unit is further configured to switch, upon reaching or exceeding a predefined threshold value, from a first to a second state having a smaller step size and causing the attenuator to change the gain such that the slope of the RF signal inverts and to switch, upon reaching the predefined threshold again, to a third state causing the attenuator to change a prefix of the gain.

Claims

1. A circuit, comprising: A first front end including a first controllable attenuator and a first amplifier, wherein the first controllable attenuator is for receiving a first wakeup pattern and in response generating a first attenuated RF wakeup pattern signal, and wherein the first amplifier is for amplifying the attenuated RF wakeup pattern signal to generate an amplified RF wakeup pattern signal; a first wakeup pattern detector comprising a first and a second stage, wherein the first stage is arranged to detect a first part of the wakeup pattern in the amplified RF wakeup pattern signal and, in response to the detection of the first part of the wakeup pattern, to generate a second stage wakeup signal, wherein the second stage is arranged to wakeup in response to the second stage wakeup signal, and wherein the first stage has a lower power consumption compared to the second stage; a control unit coupled to control the gain of the attenuator, wherein the control unit is configured to control the attenuator gain in response to a level of the amplified RF wakeup pattern signal; wherein the control unit includes a plurality of predetermined states for causing the first controllable attenuator to increase or to decrease the first attenuator gain in accordance with a predefined step size.

2. The circuit of claim 1, wherein the first attenuator gain is the overall gain of the first amplifier and the attenuation of the first controllable attenuator.

3. The circuit of claim 2, wherein predetermined states include up-states for causing the attenuator to increase the attenuator gain by a step-up step size, wherein predetermined states include down-states for causing the attenuator to decrease the attenuator gain by a step-down step size, wherein the step-up step size is equal to or smaller than the step-down step size.

4. The circuit of claim 3, wherein the step-up step size is smaller than the step-down step size.

5. The circuit of claim 2, wherein the control unit is configured to switch, upon reaching or exceeding a predetermined threshold value, from a first control state to a second control state having a smaller step size.

6. The circuit of claim 5, wherein the second state is arranged to change the attenuator gain so the slope of the amplified RF wakeup pattern signal inverts.

7. The circuit of claim 6, wherein the control unit is configured to switch, upon reaching the predefined threshold value again, into a third state for changing the prefix of the attenuator gain, wherein the prefix is positive or negative.

8. The circuit of claim 6, wherein the step sizes are binary ratios so that larger step sizes are a power of two larger than a smaller step size.

9. The circuit of claim 8, wherein the control unit is configured to perform a binary search for settling the generation of the amplified RF wakeup pattern signal.

10. The circuit of claim 2, wherein the gain of the amplified RF wakeup pattern signal is set to a minimum RF level required for wakeup.

11. The circuit of claim 2, wherein the attenuation factor of the attenuator is determined in response to the gain of the amplified RF wakeup pattern signal.

12. The circuit of claim 2, wherein the attenuation factor of the attenuator is dynamically adjusted in response to the gain of the amplified RF wakeup pattern signal.

13. The circuit of claim 2 comprising; A second front end for receiving a second wakeup pattern having a first and a second part concatenated to each other; and a second wakeup pattern detector comprising a first and a second stage, wherein the first stage is arranged to detect a first part of the second wakeup pattern and, in response to the detection of the first part of the second wakeup pattern, to generate a second stage wakeup signal, wherein the second stage is arranged to wakeup in response to the second stage wakeup signal, and wherein the first stage has a lower power consumption compared to the second stage, wherein the first front end and the first wakeup pattern detector are included by a first receiver channel of a first spatial direction of each spatial direction, wherein the second front end and the second wakeup pattern detector are included by a second receiver channel of a second spatial direction of each spatial direction, and wherein the second wakeup pattern detector is arranged to generate a wakeup signal for waking up circuitry in a transponder including the first receiver channel.

14. The circuit of claim 13, comprising: A third front end for receiving a third wakeup pattern having a first and a second part concatenated to each other; and a third wakeup pattern detector comprising a first and a second stage, wherein the first stage is arranged to detect a first part of the second wakeup pattern and, in response to the detection of the first part of the second wakeup pattern, to generate a second stage wakeup signal, wherein the second stage is arranged to wakeup in response to the second stage wakeup signal, wherein the first stage has a lower power consumption compared to the second stage, wherein the third wakeup pattern detector is arranged to generate a wakeup signal for waking up circuitry in a transponder including the first receiver channel, and wherein the third front end and the third wakeup pattern detector are included by a third receiver channel of a third spatial direction of each spatial direction.

15. The circuit of claim 14, wherein each of the first, second, and third receiver channels includes a demodulator, wherein each demodulators form a part of an automatic gain control loop of each respective receiver channel.

16. The circuit of claim 15, wherein each of the first, second, and third wakeup pattern detectors are arranged to each independently generate a wakeup signal for waking up circuitry in a transponder including the first, second, and third receiver channels.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic receiver channel;

(2) FIG. 2 is a simplified circuit diagram for a receiver channel that is controlled by a finite state machine;

(3) FIG. 3 is a state diagram for a control unit according to an embodiment of the invention;

(4) FIG. 4 is a table of the states known from the state diagram of FIG. 3;

(5) FIG. 5 is a schematic diagram illustrating the operation of an attenuator controller;

(6) FIG. 6 is a simplified circuit diagram of three receiver channels having a two stage wake-up pattern detector; and

(7) FIG. 7 is a simplified circuit diagram for a receiver channel, wherein the second stage wake-up pattern detector is split up.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(8) FIG. 2 is a simplified circuit diagram for an analog front end 2 is a simplified circuit diagram for an analog front end 2 and a digital finite state machine FSM of an RFID transponder. An RF-signal RF that is received by a suitable antenna is coupled to an attenuator ATT. The attenuated signal is subsequently coupled to an amplifier chain AMPC that is working with a fixed amplification gain. The attenuation factor of the attenuator ATT is controlled by an attenuator controller ATTC. The overall amplification gain of the RF-signal is controlled by controlling the attenuation factor of the attenuator ATT. Since the amplification factor of the amplifier chain AMPC is constant, the total gain for the RF-signal solely depends on the attenuation factor that is the reciprocal value of the amplifier gain. In the following, the term attenuator gain will be used for this reciprocal attenuation factor that is further proportional to the overall gain of the RF-signal. Accordingly, the gain of the amplifier chain is set to a fixed level of 4:0. Gain<4:0> means that this is a digital signal of 5 bits, gain<4> being the most significant bit and gain<0> the least significant bit. With these 5 bits the gain can be adjusted in 32 steps.

(9) This gain setting determines the minimum RF level required for wake up and is usually fixed during operation. Specification of the amplifier gain is in logarithmic form. The amplified signal is further coupled to a rectifier and peak detector RPD that detects a maximum amplitude of the amplified RF-signal. The level of the maximum amplitude is communicated to a comparator COMP that decides whether the respective level exceeds one of the threshold values TH1, THS or TH2. The respective information is communicated to the finite state machine FSM. The signals th1, ths and th2 that are communicated to the finite state machine FSM, indicate that the respective level TH1, THS and TH2 is reached or exceeded by the RF signal.

(10) The threshold values TH1, THS and TH2 are arranged to each other in ascending order, wherein TH2 is smaller than THS that is in turn smaller than TH1. Preferably, TH2 is approximately equal to 0.7 times THS and TH1 is approximately equal to 1.6 times THS. Preferably, THS is the target output level of the amplifier, TH2 is the demodulation threshold and TH1 indicates that a strong signal has arrived.

(11) The finite state machine FSM receives the signals th1, ths, th2 indicating the level of the RF-signal. The digital finite state machine FSM outputs a signal fast_amp to the rectifier and peak detector RPD. This signal sets the rectifier and peak detector RPD to a predetermined fast or slow mode. Further, the finite state machine FSM outputs signals: precharge, up, down, small, med, big, en_ATT to the attenuator controller ATTC. The signal precharge causes the attenuator controller ATTC to pre-charge or to set the attenuation gain up or down in case of the signal up or down. The signals: small, med, big indicate whether a small, medium or big step-up or step-down is commanded. The signal en_ATT is the enable signal for the ATTC block. If it is low the attenuator is in power down (no power consumption, but output is undefined). High puts it in operating mode. Precharge should be set high for a short time after en_att goes high to bring the output of ATTC to the optimal voltage for starting the regulation loop. Further, the finite state machine communicates the signals EOB and ASK data to the further parts of the RFID transponder. A run signal that starts a bit detection in the ASK signal by the following bit detection block. The finite state machine FSM as well as the comparator COMP and the attenuator controller ATTC are clocked with a clock signal CLK. This causes the whole system to check the level of the RF-signal in every clock cycle. The gain of the amplifier chain is controlled by the signal gain(4:0). In the following, an example wake up sequence for an RFID transponder according to an embodiment of the invention will be explained by making reference to FIG. 3 that is a state diagram for the finite state machine of FIG. 2 that is further a preferable control unit according to an embodiment of the invention. FIG. 4 is an example table showing the states of the finite state machine FSM. In absence of an RF input signal, the finite state machine FSM remains in state 0a which is the state with the lowest power consumption and the maximum gain (see FIG. 3). When an RF-signal is detected and the signal exceeds the threshold value TH2, the finite state machine FSM changes to state 0b as it is indicated by a respective arrow th2. If TH2 is not exceeded, indicated by the arrow !th2, the finite state machine FSM remains in state 0a.

(12) In state 0b, the attenuator controller ATTC is pre-charged (see FIG. 4). In FIG. 5, the relation between the attenuator gain and a control voltage that is fed to the attenuator controller ATTC is depicted. A pre-charge voltage u0 is necessary to set the attenuator controller ATTC to its linear range.

(13) After pre-chargement of the attenuator controller ATTC, the finite state machine FSM automatically changes to state 1 (see FIG. 3.). The step size of the attenuator controller ATTC is set to big. However, both values for up and down remain at zero which means that neither an increase nor a decrease of the attenuator gain (see FIG. 4) takes place. Consequently, there is no change in the control voltage of the attenuator controller ATTC. The startup sequence is at an end and the finite state machine FSM changes into a settling mode.

(14) In the settling mode, starting at state 1 it is determined first, whether the output voltage of the amplifier chain AMPC is higher or lower than THS. If the output voltage is higher than THS, the machine follows the branch ths and reaches state 2 and 3 (indicated by 2,3 in FIG. 3). In this state, the attenuator gain is reduced using big steps down (see FIG. 4) until the level of the RF signal is below THS. If this is the case, the machine follows the branch !ths to states 4 to 7 (indicated by 4-7 in FIG. 3). The attenuator gain is increased again with big steps up (which may be smaller than big steps down, further, they are half the size of the big steps down) until the level of the RF-signal is higher than THS.

(15) Now, the attenuator gain will be decreased using medium steps in state 8 to 11 (indicated by 8-11). These steps are repeated until the level of the RF-signal falls below THS again. If this happens, the machine follows the branch !ths and reaches state 12 to 15 (12-15 in FIG. 3). Again, at this state, the attenuator gain will be increased with medium steps up (which again will be smaller than medium steps down).

(16) The level of the RF-signal will reach the threshold THS. Then, the machine changes to states 25, 26. In these states, the step size is set to small (see FIG. 4). The gain settling of the RFID transponder is achieved and the rectifier output voltage oscillates around the THS level with a minimum attenuation step size until demodulation starts. In the following, further functionality of the finite state machine FSM will be explained by making reference to FIGS. 3 and 4.

(17) State 2, 3 reduces the attenuator gain with big steps (see FIG. 4). Consequently, the transition to the next state, i.e. the branch !ths, is always reached. Therefore the steps 2, 3 do not need a timeout criterion. The input amplitude of the RF-signal is reduced until the signal level falls below THS.

(18) The states reducing the attenuator gain with medium steps, i.e. the states 8 to 11, will also reach the transition to the branch !ths leading to states 12 to 15, since the attenuator gain is reduced until the signal level falls below THS. However, this can take a long number of cycles when a strong signal arrives, because the down steps in the respective states 8 to 11 are only of medium size (see FIG. 4). Advantageously, the number of cycles the state machine stays in this status, is limited. Preferably, the number of cycles is limited to four cycles. If this limit is reached, the state machine changes to state 2, 3 as indicated by the branch ths&11.

(19) The states increasing the attenuator gain have no built-in end condition. However, even with maximum gain, the input level might not be sufficient for the RF-signal to exceed the threshold THS. This refers to states 4 to 7 and 12 to 15. In this case, the RF-signal is to weak to reach the threshold value THS, the number of cycles the machine stays in the respective states is limited. Again, the states are preferably limited to four cycles. If this limit is reached, the machine changes to state 2, 3. This is not indicated by a branch in FIG. 3 for clarity reasons. In case of an RF-signal drop, i.e. the RF-signal quickly loses intensity, the machine remains in the states 4 to 7 or 12 to 15 until the maximum number of cycles is reached. If this is the case, the machine is set to the initial state 0a or to state 4 to 7 respectively.

(20) Due to internal amplifier noise or external interference signals, the decision in state 1, i.e. whether the RF-signal is above or below the threshold value THS, has a certain probability to be wrong. The state machine has to recover from such a wrong decision in the following states. Consequently, the allowed number of cycles for the finite state machine to remain in one state is determined by the ratio of the step size of the previous state and the current step size, taking a wrong decision into account.

(21) The demodulation of the RF-signal starts when settling is achieved and the signal falls below THS (which indicates a strong burst signal). Now, the state machine is in state 28 and the gain is kept constant since the up and down values are both set to low. The signal run is set to high which starts the following digital circuitry.

(22) When RF is turned on, the level rises above TH2 and the machine changes into states 30 and 31. In this state, the signal EOB (End of Burst) is set to low and depending on the value of the RF-signal (whether it exceeds THS or not) the gain is adjusted to the level of the RF-signal. These states correspond to the states 26 and 27, both having a small step size and changing the amplifier gain up and down. The signal EOB is used for a demodulation in the following digital circuitry.

(23) When RF is turned off, the level falls below TH2 and the machine changes into state 29. In this state, EOB (end of burst) is set to high and the gain remains constant.

(24) Timeouts during modulation are detected by the subsequent bit detector block and in case such a timeout is detected the front end 2 is set to the initial state 0a.

(25) The RFID transponder according to the invention is non-sensitive/robust with respect to interference signals. If interference noise is present, the gain control adapts to the level of the interference signal and the finite state machine FSM remains in the states 25, 26 to 31. If a stronger signal arrives, having a strength that is sufficient to lead to an output signal of the rectifier of more than TH1, the demodulation mode is left and the machine changes to settling mode. In case of such a strong burst, the machine changes to state 29 having a very low amplifier gain. In this case, the following circuitry will detect a symbol exceeding a maximum length and thus reset the finite state machine FSM to a state 0a. This is indicated in FIG. 3 by the timeout arrow leading to the state 0a.

(26) A further embodiment of the invention will be explained in the following by making reference to FIGS. 6 and 7.

(27) In a typical environment for an RFID application, the RF signal comes from different spatial directions. This is indicated in FIG. 6 by signals RFx, RFy and RFz. An interference tolerant frontend of an RFID transponder according to the invention uses three independent channels, one channel for each spatial direction. If a strong interference noise is received from a first direction and a signal is received from an other direction, the signal to noise ratio (S/N) is different for each input channel. In most cases at least one channel has a sufficiently high S/N to correctly detect the signal.

(28) As each channel is able to detect a wake up pattern and to react on this, even if one or two other channel(s) are blocked by an interference signal, the RFID transponder can react correctly when receiving a wake up pattern by selecting the undisturbed channel for further RF communication. If one channel detects a wake up pattern, a respective signal wakeX, wakeY or wakeZ is communicated to the rest of the RFID system and its protocol circuitry is started for further communication.

(29) However, according to this approach, three channels, namely channelX, channelY and channelZ have to be active for bit detection and wake up pattern detection. In comparison to a conventional design using just one channel, this could lead to increased power consumption.

(30) The RFID transponder according to the invention provides a solution for a scenario when an interference source and the RF signal RFx, RFy and RFz are received from different spatial directions. The interference source may be strong enough to jam the RFID receiver. However, by evaluating the input RF signal independently for each spatial direction in three separate amplifiers, one amplifier channel can correctly detect an input signal even if another amplifier is blocked by the interfering signal. In conventional designs, the three parallel amplifier channels will lead to the disadvantage of increased power consumption. Since the invention provides an RFID transponder having very little power consumption, this drawback could be overcome. In other words, the low power design of the RFID transponder according to the invention allows the aforementioned parallel design having a receiver channel for each spatial direction.

(31) Each channel comprises an automatic gain control AGC and a demodulator block 8. The amplification of the RF signal is controlled by a loop, so that the output signal amplitude of the AGC is constant. Preferably, a closed loop control according to the aforementioned embodiment of FIGS. 2 to 5 may be applied.

(32) The demodulation block 8 detects, whether the input level exceeds a certain threshold level and outputs the ASK modulation. The data is preferably coded with a bit length coding, wherein the length of the low time plus high time corresponds to certain values. This may be measured in a bit detect block 10 using a local oscillator as time reference. For each symbol length a lower and an upper limit may be given, detected lengths, outside of the valid limits lead to an invalid symbol being output.

(33) The output of the bit detect block 10 is subsequently coupled to a first stage of the wake up pattern detector WP START. Further, the signal is fed to a second block of the wake up pattern detector WP DETECT. The first stage WP START detects a start sequence of the wake up pattern. This start sequence is preferably concatenated to every wake pattern within the respective RFID system. The second stage WP DETECT detects a remainder of the wake up pattern that is concatenate to the start sequence. The resulting values of the wake up pattern detection are compared with the expected/predetermined wake up pattern.

(34) The specific structure of the wake up pattern and the subsequent two stage wake up pattern detection is for minimizing power consumption of the RFID. To achieve a maximum power saving, the following implementation may be chosen. An example embodiment will be explained in the following:

(35) In an initial state (absence of any signal) only the analog part of the RFID, i.e. the AGC and the demodulator 8 are active.

(36) When an input signal RFx, RFy, RFz of sufficient strength is detected by the demodulation circuit 8, the bit detect circuit 10 and the first stage WP START of the wake up pattern detector is enabled.

(37) If the input signal RFx, RFy, RFz drops below a certain threshold value for longer than a timeout time, the front end 2 returns to its initial state.

(38) If the first stage WP START of the wake up pattern detector detects a valid start sequence, i.e. the first part of the wake up pattern, it enables and resets the second stage WP DETECT of the wake up pattern detector for further comparison of the incoming data with a remaining predetermined wake up pattern.

(39) If the first stage WP START detects an invalid symbol, the second stage WP DETECT of the wake up pattern detector is disabled and the first stage WP START waits again for a valid start sequence, i.e. a valid wake up pattern.

(40) If both the first stage WP START and the second stage WP DETECT of the wake up pattern detector detect a valid wake up pattern, a wake signal wakeX, wakeY or wakeZ is output, which activates the further parts of the RFID, e.g. the protocol circuitry. If the second stage WP DETECT however receives a symbol which does not match the expected value, it disables itself. The first stage WP START remains active and searches for a valid start sequence, i.e. a valid wake up pattern.

(41) The wake up pattern detector, i.e., may be first stage WP START and second stage WP DETECT do not work with the same clock as the bit detect circuit 10, but with the symbol clock, which is generated by the bit detector 10. The frequency of the bit detect clock determines the resolution of the symbol discrimination and is usually much higher compared to the symbol clock, which is output whenever a symbol (including an invalid symbol) is detected. This aspect leads to a reduction in power consumption.

(42) This RFID layout according to the embodiment of FIG. 6 can be extended to support a multiple wake up pattern. This further embodiment will be explained by making reference to FIG. 7.

(43) In some RFID applications, a base station can select the RFID transponder's response by sending different wake up patterns. For example, by sending a first wake up pattern, a fast but less secure authentication protocol for unlocking a car's door may be selected. In contrast, by sending a second wake up pattern a slower but more secure authentication protocol, e.g. for the engine start clearance is selected. The two wake up patterns have the same start sequence but different remainders.

(44) The embodiment of FIG. 7 shows a wake up pattern detector having a single first stage WP START but two second stages, namely WP1 DETECT and WP2 DETECT. The latter ones detect the respective different remainders of the wake up pattern. Upon successful detection, the respective signal wake1 or wake2 are communicated to the rest of the RFID transponder.

(45) Operation of the RFID transponder having a split up second stage is in analogy with the aforementioned sequence. The embodiment may be extended to more than two different remainders of a wake up pattern by solely adding further second stages for each wake pattern.

(46) According to another aspect of the invention, for long wake patterns it is further advantageous to split up the second stage of the wake up pattern detector, e.g. a first stage WPdetect1 and a second stage WPdetect2. For an exemplary length of a wake up pattern remainder of N+M symbols, the first stage WPdetect1 will detect/compare the first N symbols of the wake pattern remainder. Upon successful comparison of the first N symbols, the second stage WPdetect2 is enabled which will detect/compare the last M symbols of the wake pattern remainder. In case of successful detection, a respective output signal wake is generated.

(47) Although the invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.