Method for fabricating CMOS compatible contact layers in semiconductor devices

Abstract

A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350 C. to 500 C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Claims

1. A method for fabricating a contact layer on a p-type gallium nitride (GaN) layer of a GaN based structure, the method comprising: depositing a nickel (Ni) layer on the p-type GaN layer; thermally treating the GaN based structure at a temperature range of 350 C. to 500 C., upon depositing the Ni layer; removing the Ni layer using an etchant, upon thermally treating the GaN based structure; and depositing the contact layer on the p-type GaN layer, upon removing the Ni layer, wherein the contact layer comprises a multi layer structure of titanium aluminum titanium (TiAlTi).

2. The method of claim 1, wherein the p-type GaN layer comprises magnesium (Mg) dopants.

3. The method of claim 1, further comprising: annealing the GaN based structure at about 750 C. in a nitrogen atmosphere, prior to depositing the Ni.

4. The method of claim 1, wherein thermally treating the GaN based structure further comprises: thermally treating the GaN based structure in an oxygen atmosphere for about 60 seconds.

5. The method of claim 1, wherein the Ni layer comprises thickness of 5 nm to 15 nm.

6. The method of claim 1, wherein the etchant comprises a solution of sulfuric acid (H.sub.2SO.sub.4) and hydrogen peroxide (H.sub.2O.sub.2).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various embodiments are described herein with reference to the drawings, wherein:

(2) FIG. 1 illustrates a flow chart of an example method for fabricating a complementary metal oxide semiconductor (CMOS) compatible contact layer on a p-type gallium nitride (GaN) layer of a GaN based structure, according to one embodiment.

(3) FIG. 2 (parts 2a to 2e) are cross-sectional views of an example GaN based structure having the CMOS compatible contact layer fabricated in accordance with the method described in FIG. 1.

(4) FIG. 3 illustrates a comparative chart, showing a comparison of threshold voltages of semiconductor devices having CMOS compatible contact layers fabricated without and with Ni layer.

(5) FIG. 4 illustrates a comparative chart, showing a comparison of threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated using a 2 nm Ni layer, a 10 nm Ni layer and a 50 nm Ni layer, in accordance with the method described in FIG. 1.

(6) FIG. 5 illustrates a comparative chart, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by thermally treating the GaN based structure in different atmospheres and for different time durations.

(7) FIG. 6 illustrates a comparative chart, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by removing the Ni layer using different etchants, in accordance with the method described in FIG. 1.

(8) The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.

DETAILED DESCRIPTION

(9) A method for fabricating complementary metal oxide semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In the following detailed description of the embodiments of the present subject matter, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present subject matter is defined by the appended claims.

(10) In the following detailed description, the term GaN based structure refers to a structure including a substrate and a heterogeneous layer stack of gallium nitride (GaN) based materials deposited on the substrate. The heterogeneous layer stack typically includes a p-type GaN layer and an n-type GaN layer deposited on the substrate. Further, the heterogeneous layer stack includes additional layers depending on the semiconductor device, in which the GaN based structure is used. For example, the GaN based structure used in a light emitting diode (LED) includes a substrate and a heterogeneous layer stack including a nucleation layer, a graded intermediate layer, a n-type GaN layer, a multiple quantum well, an electron blocking layer and a p-type GaN layer.

(11) The present invention relates to fabricating a CMOS compatible contact layer on a p-type GaN layer of a GaN based structure. The method includes deposition of a nickel (Ni) layer on top of the p-type GaN layer, followed by thermal treatment in an oxygen (O.sub.2) atmosphere. Furthermore, the Ni layer is wet stripped in a solution of sulfuric acid (H.sub.2SO.sub.4) and hydrogen peroxide (H.sub.2O.sub.2). Finally, the CMOS compatible contact layer (i.e., aluminum (Al) based) is deposited on the p-type GaN layer.

(12) FIG. 1 illustrates flow chart 100 of an example method for fabricating a CMOS compatible contact layer on a p-type GaN layer of a GaN based structure, according to one embodiment. At step 102, the GaN based structure is annealed at a temperature of about 750 C. in a nitrogen (N.sub.2) atmosphere. In one example embodiment, the GaN based structure is annealed in a rapid thermal annealing (RTA) oven for 10 minutes in the N.sub.2 atmosphere. By annealing the GaN based structure, dopants (e.g., Mg dopants) in the p-type GaN layer are activated, which in turn increases net hole concentration of the p-type GaN layer.

(13) At step 104, a Ni layer is deposited on the p-type GaN layer of the GaN based structure. For example, the Ni layer includes a thickness ranging from 5 nm to 15 nm. The deposition of the Ni layer on the p-type GaN layer provides better electrical characteristics, such as lower threshold voltage, as explained in detail with reference to FIG. 3. Further, the electrical characteristics also depend on the thickness of the Ni layer, as explained in detail with reference to FIG. 4.

(14) At step 106, the GaN based structure is thermally treated at a temperature ranging from 350 C. to 500 C. In this case, deposition of additional layers, such as Au or alloys thereof, on the Ni layer is not required. In an example, the GaN based structure is thermally treated at 450 C. in a 100% O.sub.2 atmosphere. In another example, the thermal treatment of the GaN based structure is performed for a time period of 60 seconds. Further, FIG. 5 illustrates the improved electrical characteristics of semiconductor devices when the GaN based structure is thermally treated at 450 C. in the O.sub.2 atmosphere for 60 seconds.

(15) At step 108, the Ni layer is removed using an etchant. In one embodiment, the Ni layer deposited on the p-type GaN layer is wet stripped using a wet etchant. Examples of wet etchants include, a solution of hydrochloric acid (HCl), nitric acid (HNO.sub.3) and water (H.sub.2O), a solution of H.sub.2SO.sub.4 and H.sub.2O.sub.2 (piranha solution) and the like. For example, the Ni layer can be etched for about 2 minutes using the solution of H.sub.2SO.sub.4+H.sub.2O.sub.2 to provide better electrical characteristics.

(16) At step 110, the CMOS compatible contact layer is deposited on the p-type GaN layer. For example, the CMOS compatible contact layer includes a multi-layer structure of titanium aluminum titanium (TiAlTi) having a thickness of 1/100/10 nm.

(17) Examples of the semiconductor devices fabricated with CMOS compatible contact layers, include light emitting diodes (LEDs), power devices and the like. In LEDs, the GaN based structure includes a silicon (Si) substrate, an aluminum nitride (AlN) nucleation layer, a graded aluminum gallium nitride (AlGaN) intermediate layer, a Si doped n-type GaN layer, a indium gallium nitride (InGaN)/GaN multiple quantum well, a AlGaN electron blocking layer, and the p-type GaN layer. Further, the GaN based structure is annealed at 750 C. for 10 min in the N.sub.2 atmosphere. Then, the Ni layer is deposited on the p-type GaN of the GaN based structure. Furthermore, the GaN based structure is thermally treated in the 100% O.sub.2 atmosphere at 450 C. for 60 seconds. Additionally, the Ni layer is etched using the solution of H.sub.2SO.sub.4+H.sub.2O.sub.2, in the ratio of 4:1. Thereafter, the CMOS compatible contact layer is deposited on the p-type GaN layer. After deposition of the CMOS compatible contact layer on the p-type GaN layer, a diode mesa structure is defined on the GaN based structure, by means of a chlorine based inductively coupled plasma (ICP) dry etch process. In addition, a contact layer is deposited on the Si doped n-type GaN layer of the GaN based structure.

(18) Referring now to FIG. 2 (parts 2a to 2e), which illustrates cross-sectional views of example GaN based structure 220 having CMOS compatible contact layer 216 fabricated in accordance with the method described in FIG. 1. As shown in FIG. 2, GaN based structure 220 includes substrate 202 on which a heterogeneous layer stack of GaN based materials is deposited. In an embodiment, the heterogeneous layer stack is deposited on substrate 202 using a metalorganic vapor phase epitaxy (MOVPE) technique. The MOVPE technique refers to a process of depositing thin layers of atoms of the GaN based materials onto substrate 202. In the MOVPE technique, precursor chemicals (i.e., precursors to the atoms deposited on substrate 202) are vaporized and transported into a reactor together with other gases. In one embodiment, the atoms of the GaN based materials (i.e., atoms of Ga, Al and N) are deposited on a 200 mm Si (111) substrate, using the precursor chemicals trimethylgallium, trimethylaluminum and ammonia, respectively. In this case, trimethylgallium, trimethylaluminum and ammonia are vaporized and transported using hydrogen as a carrier gas, such that the heterogeneous layer stack is deposited on substrate 202.

(19) As shown in FIG. 2, the heterogeneous stack of GaN based materials includes nucleation layer 204, graded intermediate layer 206, n-type GaN layer 208, multiple quantum well 210, electron blocking layer 212 and p-type GaN layer 214. In an embodiment, nucleation layer 204 is composed of AlN and graded intermediate layer 206 is composed of AlGaN. Further, n-type GaN layer 208 is doped with Si dopants and p-type GaN layer 214 is doped with Mg dopants. Furthermore, multiple quantum well 210 has an InGaN/GaN quantum well structure. Additionally, electron blocking layer 212 is composed of Mg doped AlGaN.

(20) Further FIG. 2 (part 2c) shows, GaN based structure 220 having top surface 220A and bottom surface 220B. Top surface 220A is formed by thermally treating a Ni layer 222 (FIG. 2, part 2b) at a temperature range of 350 C. to 500 C. for about 60 seconds and then removing the Ni layer. In one embodiment, the Ni layer has a thickness of 10 nm and is thermally treated at 450 C. for 60 seconds in an O.sub.2 atmosphere. Further, the Ni layer is removed using a solution of H.sub.2SO.sub.4+H.sub.2O.sub.2.

(21) Furthermore, CMOS compatible contact layer 216 is present on p-type GaN layer 214. See FIG. 2 (parts 2d and 2e). In addition, contact layer 218 is present on n-type GaN layer 208. See FIG. 2 (part 2e). In one embodiment, CMOS compatible layer 216 includes a multi-layer structure composed of TiAlTi, having a thickness of 1/100/10 nm. Additionally, GaN based structure 220 has a mesa structure and is used in the fabrication of LEDs.

(22) Referring now to FIG. 3, which illustrates comparative chart 300, showing a comparison of threshold voltages of semiconductor devices having CMOS compatible contact layers fabricated without and with Ni layer, with threshold voltage shown on y-axis.

(23) According to comparative chart 300, graph 302 illustrates the threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated without using of the Ni layer. In contrast, graph 304 of comparative chart 300, illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers that are fabricated by using of the Ni layer having a thickness of 10 nm.

(24) As shown in FIG. 3, the threshold voltages in graph 302 are between 4.25 v to 5 v, whereas, the threshold voltages in graph 304 are between 3 v to 4.25 v. From comparative chart 300, it is observed that there is a significant reduction in the threshold voltages when the Ni layer is used. The reduction in the threshold voltages is attributed to improved hole concentration in the p-type GaN layers (e.g., p-type GaN layer 214 of FIG. 2), of the GaN based structures used in the semiconductor devices. For example, referring FIG. 2, the Mg dopants of p-type GaN layer 214 form MgH complexes with hydrogen. The deposition of the Ni layer enhances hydrogen desorption from the Mg dopants, which results in improved hole concentration. The improved hole concentration in p-type GaN layer 214 results in the reduction of the contact resistance, which in turn results in the reduction of the threshold voltages of the semiconductor devices. Therefore, better electrical characteristics are achieved when the Ni layer is deposited on the p-type GaN layer 214.

(25) Referring now to FIG. 4, which illustrates comparative chart 400, showing a comparison of threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated using a 2 nm Ni layer, a 10 nm Ni layer and a 50 nm Ni layer, in accordance with the method described in FIG. 1.

(26) According to comparative chart 400, graph 402 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 2 nm Ni layer. Further, graph 404 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 10 nm Ni layer. Furthermore, graph 406 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 50 nm Ni layer. Additionally, threshold voltage is shown on y-axis.

(27) As shown in FIG. 4, the threshold voltages in graph 402 range from 3.75 v to 3.85 v. In contrast, the threshold voltages in graph 404 range mainly from 3.65 v to 3.725 v. Further, as observed in graph 406 the threshold voltages range mainly from 4.535 v to 4.575 v. Therefore, lowest threshold voltage range is observed when the 10 nm Ni layers are used to fabricate the CMOS compatible contact layers.

(28) Referring now to FIG. 5, which illustrates comparative chart 500, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by thermally treating the GaN based structure in different atmospheres and for different time durations. As shown in comparative chart 500, graph 502A and graph 502B illustrate the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated in the N.sub.2 atmosphere for 60 seconds and 600 seconds, respectively. Furthermore, graph 504A and graph 504B illustrate the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated in the O.sub.2 atmosphere for 60 seconds and 600 seconds, respectively.

(29) As observed from FIG. 5, threshold voltage range in graph 502A and graph 502B is mainly between 4.25 v to 4.45 v and 4.4 v to 4.6 v, respectively. In contrast threshold voltage range in graph 504A and graph 504B is mainly between 3.625 v to 3.7 v and 3.4 v to 3.45 v, respectively. Therefore, it is observed that there is a significant reduction in the threshold voltages when the CMOS compatible contact layers fabricated in the O.sub.2 atmosphere.

(30) Further from graph 504A and graph 504B, it is observed that lower threshold voltages can be achieved when the thermal treatment step is performed for 600 seconds in the O.sub.2 atmosphere. However, it is also observed that there is only a slight increase in the threshold voltage range when the thermal treatment step is performed for 60 seconds in the O.sub.2 atmosphere. Further, in light of the considerable reduction in the time duration (i.e., from 600 seconds to 60 seconds), the slight increase in the threshold voltage range is considered to have a negligible impact on the electrical characteristics of the semiconductor devices.

(31) Referring now to FIG. 6, which illustrates comparative chart 600, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by removing the Ni layer using different etchants, in accordance with the method described in FIG. 1. As shown in FIG. 6, graph 602 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated without the Ni layer. Furthermore, graph 604 illustrates the threshold voltages of the semiconductor devices, when the Ni layer is etched for 10 minutes using HCl+HNO.sub.3+H.sub.2O having the ratio of 3:1:2. In addition, graph 606 illustrates the threshold voltages of the semiconductor devices, when the Ni layer is etched for 2 minutes using H.sub.2SO.sub.4+H.sub.2O.sub.2.

(32) As shown in graph 602, when the Ni layer is not used to fabricate the CMOS compatible contact layers, threshold voltage range is 3.8 v to 4.4 v. Further with regards to graph 604, it is observed that when the Ni layer is etched using HCl+HNO.sub.3+H.sub.2O the threshold voltages of the semiconductor devices are in the range of 3.2 v to 4.1 v. Furthermore, as shown in graph 606, when the Ni layer is etched using H.sub.2SO.sub.4+H.sub.2O.sub.2 the threshold voltages of the semiconductor devices are in the range of 2.9 v to 3 v. Therefore, it is observed that there is a significant drop in the threshold voltages of the semiconductor devices when the Ni layer is etched using H.sub.2SO.sub.4+H.sub.2O.sub.2.

(33) As apparent from the above description, the semiconductor devices having the CMOS compatible contact layers fabricated in accordance with the method described in FIG. 1, show better electrical characteristics as compared to the approaches used in the prior art. Further, by using the CMOS compatible contact layers there is a reduction in the cost of fabricating the semiconductor devices. In other words, by using the CMOS compatible contact layers, the economy-of-scale of existing CMOS production lines is effectively used during the fabrication of the semiconductor devices.

(34) It should be understood that the embodiments and the accompanying drawings as described above have been described for illustrative purposes and the present invention is limited by the following claims. Further, this patent covers all methods fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.