SWITCH UNIT, ETHERNET NETWORK, AND METHOD FOR ACTIVATING COMPONENTS IN AN ETHERNET NETWORK

Abstract

A switch unit for an Ethernet network having a switch and a microprocessor, the switch including at least three ports, which are connected to inputs and outputs of the switch unit, a signal detector and generator for detecting and initiating a bus activity being arranged in each case between the ports and the inputs and outputs of the switch unit. For each input and output an allocation rule to the other inputs and outputs of the switch unit is stored in a memory , the switch unit being designed such that when a bus activity is detected at a signal detector and generator, the assigned inputs and outputs of this input and output are read out from the memory and the associated signal detectors and generators are woken up so that they generate a bus activity at their inputs and outputs.

Claims

1. A switch unit for an Ethernet network, the switch unit comprising: a switch having at least three ports that are connected to inputs and outputs of the switch unit; a microprocessor; a signal detector and generator that is adapted to detect and initiate a bus activity and that is arranged between the at least three ports and the inputs and outputs of the switch unit; and a memory, wherein, for each input and output, an allocation rule to the other inputs and outputs of the switch unit is stored in the memory, wherein the switch unit is configured such that, when a bus activity is detected at the signal detector and generator, the assigned inputs and outputs of this input and output are read out from the memory and the associated signal detectors and generators are woken up so that they generate a bus activity at their inputs and outputs.

2. The switch unit according to claim 1, wherein the memory is configured by a microprocessor.

3. The switch unit according to claim 1, wherein the signal detectors and generators and a memory are continuously supplied with voltage.

4. The switch unit according to claim 1, wherein a second switch is assigned to the switch and a microprocessor, which is adapted such that it is switched at least as a function of the signals at the signal detectors and generators.

5. An Ethernet network comprising at least one switch unit that is connected to control units and/or additional switch units, the at least one switch unit comprising: a switch having a microprocessor, the switch having at least three ports that are connected to inputs and outputs of the switch unit; a signal detector and generator adapted to detect and initiate a bus activity, the signal detector and generator being arranged between the ports and the inputs and outputs of the switch unit; and a memory, wherein, for each input and output, an allocation rule to the other inputs and outputs of the switch unit is stored in the memory, wherein the switch unit is configured such that, when a bus activity is detected at a signal detector and generator, the assigned inputs and outputs of this input and output are read out from the memory and the associated signal detectors and generators are woken up so that they generate a bus activity at their inputs and outputs.

6. The Ethernet network according to claim 5, wherein all switch units of the Ethernet network comprise at least one memory in which the allocation rule is stored.

7. The Ethernet network according to claim 5, wherein at least one switch unit is configured such that all control units and/or switch units connected to the switch unit are woken up in one operating mode.

8. The Ethernet network according to claim 5, wherein the switch units are configured such that a step-by-step wakeup operation is carried out in another operating mode.

9. A method for activating a component in an Ethernet network according to claim 5, the method comprising: detecting a bus activity of a control unit setting up a data connection in at least one switch unit, the bus activity being detected in the switch unit via the signal detector and generator; and generating a bus activity at assigned inputs and outputs so that the control units and/or switch units connected thereto are woken up.

10. The method according to claim 9, wherein the microprocessor is started up in parallel to the wakeup operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0021] FIG. 1 shows a schematic block diagram of a part of an Ethernet network having a step-by-step wakeup operation; and

[0022] FIG. 2 shows a schematic block diagram of a part of an Ethernet network including a switch unit according to the invention.

DETAILED DESCRIPTION

[0023] Part of an Ethernet network 1 is illustrated in FIG. 1, which includes a first control unit A and a second control unit B, which are connected to each other via three switch units 10, the dashed line on switch units 10 being intended to show that the latter may be connected to additional control units and/or switch units. A switch or sensor 2 is assigned to control unit A, wherein an actuator 3 is to be activated by control unit B upon the detection of a sensor signal or the actuation of the switch.

[0024] Assuming that all control units A, B and all switch units 10 are asleep, control unit A is first woken up by sensor 2 or the switch. After control unit A is woken up, the latter transmits a communication signal to connected switch unit 10 in a first step S1 with the request to set up a data connection with control unit B. At the address of control unit B, switch unit 10 now detects that superordinate switch unit 10 is required for the data connection and, in a second step S2, transmits another communication signal to this switch unit 10, which then transmits a communication signal to additional switch unit 10 in a third step S3, until the switch unit finally wakes up control unit B via a communication signal in another step S4. Control unit B may then activate actuator 3. Assuming that each step S1 through S4 takes approximately 200 ms, the data connection from A to B requires approximately 800 ms. This wakeup operation is also referred to as step-by-step wakeup.

[0025] FIG. 2 again shows part of an Ethernet network 1, including control unit A and a switch unit 10, illustrated switch unit 10 being connected to additional components B, C and D, B, C and D being able to be control units or switch units 10.

[0026] Switch unit 10 has a part 11, which is continuously supplied with voltage, and a part 12, whose voltage may be switched on and off via a switch 13. Second part 12 comprises a switch 14 having four ports PA through PD as well as a microprocessor 15. First part 11 includes four signal detectors and generators 16 for detecting and initiating a bus activity. Signal detector and generator 16 is made up of, for example, a transceiver, which reacts to a state change on the connected bus line and is itself able to generate valid signals. First part 11 furthermore includes a memory unit 17, which is designed as a non-volatile RAM, as well as an OR logic 18. Units 16 are situated between ports PA through PD and inputs and outputs EA/A through EA/D of switch unit 10. The designation inputs and outputs is intended to clarify that the connection is bidirectional, i.e., it is able to transmit and receive via the input and output. An allocation rule is stored in memory unit 17 which identifies the network participants to which an individual network participant would like to set up a data connection or via which a data connection must pass. For example, it shows that control unit A requires components B and D for a data connection. Accordingly, component B requires component C, etc.

[0027] Control unit A comprises a microprocessor 20, an Ethernet physical layer circuit 21 and a signal detector and generator 22, which is designed similarly to signal detectors and generators 16 in switch unit 10. Control unit A furthermore includes a switchable voltage controller 23. Ethernet physical layer circuit 21 is used to encode and decode the digital signals of microprocessor 20 into Ethernet bus signals.

[0028] It is now assumed that control unit A, switch unit 10 and components B through D are deactivated. Sensor 2 then detects a signal, i.e., it generates a signal for the purpose of activating voltage controller 23. At the same time, signal detector and generator 22 is activated, which changes its state and transmits a detectable signal. Microprocessor 20 is started up in parallel to the activation of signal detector and generator 22. Even before microprocessor 20 is started up, signal detector and generator 16 assigned to input and output EA/A detects the state change of signal detector and generator 22 and reads out the associated column for A from memory unit 17. Correspondingly, signal detectors and generators 16 assigned to inputs and outputs EA/B and EA/D are addressed by the read operation and subsequently change their state, which is detected by components B and D via their signal detectors and generators. In parallel to reading memory unit 17, switch 13 is activated via OR logic 18, and microprocessor 15 and switch 14 are started up. If control unit A now begins its communication, switch unit 10 and components B and D are already activated, so that the data connection between control unit A and the target component (B and D or another component connected to B or D) may be set up more rapidly.

[0029] The allocation rule in memory unit 17 may be static or configurable by microprocessor 15, which is indicated by the arrow. The system may also be designed to be self-learning, so that, for example, control units which are woken up but are not actually needed may report this and be removed from the matrix accordingly.

[0030] If a component to be woken up is erroneously not in the matrix, the data connection is set up using a step-by-step wakeup operation, it then being possible to enter the missing component into the matrix.

[0031] If control unit A is to be woken up, associated signal detector and generator 16 is correspondingly activated in switch unit 10. This state change is then detected by signal detector and generator 22, which is indicated by the dashed line in FIG. 2. Signal detector and generator 22 then activates voltage controller 23.

[0032] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.