Insulating paste, electronic device and method for forming insulator

Abstract

An insulating paste includes insulating particles 311, Si particles 312 and an organic Si compound 320. The organic Si compound 320 reacts with the Si particles 312 to form a SiO bond filling up the space around the insulating particles 311.

Claims

1. A method for forming an electrical insulator in a space of an electronic device, comprising the steps of: pouring a paste containing electrically insulating particles, Si particles having a particle size equal to or less than 1 m, and an organic Si compound selected from the group consisting of alkylalkoxysilane and organopolysiloxane into the space; and then, reacting the organic Si compound with the Si particles by heat treatment at a temperature of 130 C. to 150 C. under vacuum to form an amorphous silica that completely fills up a space around the electrically insulating particles in the space of the electronic device.

2. A method for forming an electrical insulator in a space of an electronic device, comprising the steps of: pouring a silicon oil into the space and forming Si particles by heat treatment; pouring a paste containing electrically insulating particles and an organic Si compound selected from the group consisting of alkylalkoxysilane and organopolysiloxane into the space; and then, reacting the organic Si compound with the Si particles by a first heat treatment at a temperature of 150 C. to 300 C. in an inert gas atmosphere, followed by a second heat treatment at a temperature of 450 C. to 500 C. under vacuum, followed by a third heat treatment at a temperature of 450 C. to 500 C. in an atmosphere, thereby forming an amorphous silica that completely fills up a space around the electrically insulating particles in the space of the electronic device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a drawing schematically showing the composition of an insulating paste according to the present invention.

(2) FIG. 2 is a drawing showing a method for forming an insulator in a minute space according to the present invention.

(3) FIG. 3 is a drawing schematically showing the structure of an insulator that is formed with an insulating paste according to the present invention.

(4) FIG. 4 is a drawing showing another example of a method for forming an insulator in a minute space according to the present invention.

(5) FIG. 5 is a plan view showing a part of an electronic device according to the present invention.

(6) FIG. 6 is a sectional view of the electronic device shown in FIG. 5.

(7) FIG. 7 is a plan view showing another embodiment of an electronic device according to the present invention.

(8) FIG. 8 is a sectional view of the electronic device shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(9) 1. Insulating Paste

(10) Referring to FIG. 1, an insulating paste 300 according to the present invention contains insulating particles 311, Si particles 312 and a liquid organic Si compound 320. When reacted with the Si particles 312, the organic Si compound 320 forms a SiO bond around the insulating particles 311 (which serve as an aggregate), thus serving to fill up the space around the insulating particles 311.

(11) The insulating particles 311 and the Si particles 312 have a particle size of nanometer order (equal to or less than 1 m). Although the insulating particles 311 and the Si particles 312 are depicted as being spherical in FIG. 1, they may have any shape and should not be construed as limited to the spherical shape. Moreover, the insulating particles 311 and the Si particles 312 are not required to have a uniform particle size but may have various particle sizes within the nanometer range.

(12) 2. Method for Forming Insulator

(13) (1) First Method

(14) In a first method for forming an insulator in a minute space with the insulating paste 300 according to the present invention, at first, members 111, 112 having a minute space 30 are prepared as shown in FIG. 2(A). The members 111, 112 may be different members or may constitute a single member. It is also preferable that at least the surfaces defining the minute space 30 possess electrical conductivity. The minute space 30 may take various forms such as a vertical hole, a transverse hole, a strip-shaped groove or a gap left between different members.

(15) Then, as shown in FIG. 2(B), the insulating paste 300 shown in FIG. 1 is poured into the minute space 30. As described above, the insulating paste 300 contains the insulating particles 311, the Si particles 312 and the organic Si compound 320. It is also possible to pour the liquid organic Si compound 320 after the insulating particles 311 and the Si particles 312 are put in the minute space.

(16) Then, as shown in FIG. 2(C), the organic Si compound 320 is reacted with the Si particles 312 to form the SiO bond network filling up the space around the insulating particles 311. Preferably, the reaction between the organic Si compound 320 and the Si particles 312 is allowed to proceed under vacuum while being heated, for example, within a temperature range of 130 C. to 150 C. Thus, the insulator 3 can be formed as shown in FIG. 2(C). Organic substances resulting from the reaction can be thermally decomposed and discharged as a gas.

(17) The insulator 3 has a structure shown in FIG. 3 in which the space around the insulating particles 311 is completely filled up with the SiO bond network, more specifically, amorphous silica (SiO.sub.2) 330.

(18) More preferably, heating is performed such that the substances in the hole or groove (minute space) are heated under pressure and then cooled under pressure. This process further accelerates the thermal decomposition of the organic substances and also increases the density of the insulating layer, improving the adhesion to the semiconductor substrate.

(19) By performing the above process with the insulating paste 300 according to the present invention, the insulator 3 with excellent physical and chemical strength can be formed in the minute space.

(20) Moreover, the SiO bond filling up the space around the insulating particles 311, more specifically, the amorphous silica (SiO.sub.2) 330 can be formed by reacting the organic Si compound 320 with the Si particles 312. That is, since the formation of the oxide from the Si particles increases the volume, a highly reliable insulator can be formed in the minute space, which is free from defects such as a gap, a void or a crack and has a high adhesion strength to the side wall of the minute space. It should be noted that the volume of the SiO.sub.2 increases by about 30 to 35% from that of the Si particles 312. This corresponds to the shrinkage ratio of the Si particles 312, preventing the formation of a void, a gap or a crack due to the shrinkage.

(21) Furthermore, since the insulating paste 300 according to the present invention contains the insulating particles 311, the insulator can be provided with various electrical properties based on the properties of the insulating particles 311. Basically, the insulating particles 311 are metal oxide particles (ceramic). For instance, when the insulating particles 311 comprise a ferroelectric material such as barium titanate, the insulator can be provided with a large capacitance; when the insulating particles 311 comprise a low dielectric material such as SiO.sub.2 or Al.sub.2O.sub.3, the insulator can be provided with a small capacitance.

(22) A typical example of the organic Si compound 320 to be used in the present invention is alkylalkoxysilane represented by the formula:
CH.sub.3O[Si.sub.nO.sub.n-1(CH.sub.3).sub.n(OCH.sub.3).sub.n]CH.sub.3.

(23) In this case, the reaction formula is as follows.
Si+CH.sub.3O[Si.sub.nO.sub.n-1(CH.sub.3).sub.n(OCH.sub.3).sub.n]CH.sub.3.fwdarw.SiO.sub.2+(C,H,O)(1)

(24) When the substrate having the minute space is a Si substrate, the above reaction also occurs with Si of the Si substrate. Alternatively, it is also possible to use organopolysiloxane (alkoxysilane having a functional side chain). For instance, it is Si or disiloxane having an alkoxy group (RO), where R is an organic group.

(25) (2) Second Method

(26) A second method relates to formation of Si. At first, as shown in FIG. 4(A), a silicon oil 301 is poured into the minute space 30 formed in the members 111, 112 and subjected to heat treatment to form Si particles 302, as shown in FIG. 4(B). Then, the foregoing reaction (1) is carried out as shown in FIGS. 4(C) and 4(D).

(27) As the silicon oil 301, dimethypolylsiloxane (C.sub.2H.sub.6OSi)n may be used. In this case, since heating should be performed first under an inert gas atmosphere and then under vacuum, the heat treatment condition and the reaction formula vary as follows.

(28) (a) When heating is performed under an inert gas atmosphere, the following reaction is allowed to proceed within a temperature range of 150 C. to 300 C.
SiCH.sub.3+O.sub.2.fwdarw.SiCH.sub.2+HO.sub.2
SiCH.sub.3+HO.sub.2.fwdarw.SiCH.sub.2+2HO
2SiCH.sub.3+2HO.fwdarw.2(SiCH.sub.2)+2H.sub.2O
SiCH.sub.2+O.sub.2.fwdarw.SiCH.sub.2O.sub.2.fwdarw.SiO+CH.sub.2O

(29) Since atmospheric heating results in producing SiO.sub.2, heating should be performed under an inert gas atmosphere so as to produce Si. The heating time is five hours or so.
SiCH.sub.2O.sub.2+SiCH.sub.3.fwdarw.SiCH.sub.2O.sub.2H+SiCH.sub.2
SiCH.sub.2O.sub.2H.fwdarw.SiCH.sub.2O+HO
(b) After heating for five hours, the following reaction is allowed to proceed by heating under vacuum within a temperature range of 450 C. to 500 C.
SiCH.sub.2O.fwdarw.Si+CH.sub.2O

(30) Through the above reaction, Si nanoparticles can be produced. When the insulating particles comprise SiO.sub.2 and when the substrate is a Si substrate, the Si nanoparticles can adhere to their surface.

(31) (c) Then, as the organic Si compound, alkylalkoxysilane represented by the formula: CH.sub.3O[Si.sub.nO.sub.n-1(CH.sub.3).sub.n(OCH.sub.3).sub.n]CH.sub.3 is infiltrated into the minute space along with the insulating particles.

(32) (d) Then, the reaction is allowed to proceed by atmospheric heating within a temperature range of 450 C. to 500 C. This reaction occurs as represented by the foregoing reaction formula (1).
Si+CH.sub.3O[Si.sub.nO.sub.n-1(CH.sub.3).sub.n(OCH.sub.3).sub.n]CH.sub.3.fwdarw.SiO.sub.2+(C,H,O)(1)

(33) In the process of the above reaction, when the substrate having the minute space is a Si substrate, the above reaction also occurs with Si of the Si substrate. Alternatively, as described above, it is also possible to use organopolysiloxane (alkoxysilane having a functional side chain). For instance, it is Si or disiloxane having an alkoxy group (RO), where R is an organic group. Thus, a strong bonding layer of SiO.sub.2 (SiO bond network) can be formed between the silica particles and the Si substrate.

(34) 3. Electronic Device

(35) The present invention is applicable to various types of electronic devices in which a small insulator should be formed for a conductor or a conductive substrate of a semiconductor or the like. In various types of electronic devices based on the TSV technology, for example, vertical conductors formed in a semiconductor substrate can be electrically insulated from other vertical conductors and semiconductor circuit elements formed in the semiconductor substrate. Its concrete example will be described hereinbelow.

(36) Referring first to FIGS. 5 and 6, a semiconductor substrate 1 has an insulating layer 3 extending along its thickness direction. The insulating layer 3 is filled in a hole or groove (hereinafter referred to as via) 30 extending along the thickness direction of, for example, a silicon substrate constituting the semiconductor substrate 1. The groove may take any shape such as a straight line shape, a curved line shape or a ring shape. In the case of the hole, its opening may take any shape such as a circular shape, a square shape or an oval shape.

(37) The insulating layer 3 is formed with the insulating paste 300 shown in FIG. 1 and composed of the nm-sized insulating particles 311 and the amorphous silica 330 filling up the space between the insulating particles 311.

(38) While the insulating particles 311 exist in the form of particles, the silica 330 is amorphous and indefinite in shape. Accordingly, even though their elements are almost identical SiO.sub.2, the insulating particles 311 and the silica 330 can be distinguished from each other.

(39) In principle, it is preferred that the insulating particles 311 has a particle size equal to or less than one-tenth of the groove width of the via 30. When the hole diameter or groove width of the via 30 is set equal to or less than 10 m, for example, a few m, the particle size of the insulating particle 311 is equal to or less than 1 m, for example, about a few hundred nm.

(40) In the semiconductor substrate 1 according to the present invention, since the insulating layer 3 is composed of the nm-sized insulating particles 311 and the silica 330 filling up the space between the insulating particles 311, as described above, there can be obtained a highly reliable insulating layer 3 free from defects such as a crack or a void.

(41) More specifically, if the insulating layer 3 is composed only of the insulating particles 311, small voids or hollows may be formed between the insulating particles 311 to cause cracking of the insulating layer 3, and such cracks may extend to the semiconductor substrate 1, e.g., the silicon substrate, damaging the silicon substrate and semiconductor circuit elements formed therein.

(42) In the present invention, on the other hand, the insulating layer 3 is composed of the insulating particles 311 and the silica 330 filling up the space around the silica particles 311, so that small voids or hollows between the insulating particles 311 can be filled up with the silica 330. This prevents cracking of the insulating layer 3, avoiding that the silicon substrate and the semiconductor circuit elements formed therein are damaged by cracking or the like.

(43) When the nanocomposite structure is composed of the nm-sized insulating particles 311 and the silica 330 tightly filling up the space around the insulating particles 311, moreover, stress can be reduced as a specific effect of the nanocomposite structure, so that the distance between the semiconductor circuit elements and the insulating layer 3 can be shortened to improve area efficiency for formation of the semiconductor circuit elements.

(44) The insulating layer 3 is ring-shaped and provided in a ring-shaped groove 30 that is formed in the semiconductor substrate 1 to surround the vertical conductor 2. With the insulating layer 3, accordingly, the semiconductor substrate 1 is divided into an inner ring-shaped portion 11 and an outer portion. Thus, the vertical conductor 2 is electrically insulated from the semiconductor substrate 1 and the other vertical conductors 2.

(45) The ring-shaped groove 30 can be formed by a known technology such as a CVD process or a laser drilling process. The ring-shaped groove 30 extends along the thickness direction of the semiconductor substrate 1 and has an first inner diameter that is larger than a outer diameter of a vertical hole 20 accommodating the vertical conductor 2. Between the inner wall surface of the vertical hole 20 and the inner wall surface of the ring-shaped groove 30, accordingly, the semiconductor substrate 1 is left like an island by a diameter difference, providing the ring-shaped portion 11. The ring-shaped groove 30 has an second inner diameter that is larger than the first inner diameter by a groove width. The groove width of the ring-shaped groove 30 may be, but not limited to, equal to or less than 10 m, for example, a few m.

(46) The insulating layer 3 may further include insulating films 31, 32. The insulating films 31, 32 preferably include an oxide film, more preferably a nitride film. The oxide film and the nitride film may be a single layer, multiple layers or a combination thereof. In addition, the oxide film and the nitride film may be deposited on the wall surface of the ring-shaped groove 30 or obtained by oxidizing or nitriding the surface of the semiconductor substrate 1 which appears on the wall surface of the ring-shaped groove 30. With this insulating structure, a negative effect of the insulating layer 3 on the semiconductor substrate 1 can be blocked by the insulating films 31, 32.

(47) In the illustrated embodiment, the insulating films 31, 32 are obtained by oxidizing or nitriding the inner wall surfaces of the ring-shaped groove 30. That is, the wall surfaces of the ring-shaped groove 30 are covered with the insulating films 31, 32, and the insulating layer 3 is filled in the ring-shaped groove 30 covered with the insulating films 31, 32.

(48) If the semiconductor substrate 1 is a common silicon substrate, for example, the oxide film is a silicon oxide film and the nitride film is a silicon nitride film. The silicon oxide film and the silicon nitride film may be formed by applying a known technology. For example, there have been known a process of oxidizing or nitriding the surface of the silicon substrate and a process of depositing the insulating layer 3 using a chemical vapor deposition process (CVD process), and either process may be employed. The oxidizing or nitriding depth of the insulating films 31, 32, i.e., substantial layer thickness is preferably determined in view of actually required transmission characteristics.

(49) The insulating layer 3 may be a single layer or may have a plurality of coaxially arranged, spaced layers. In addition, its shape is not limited to the illustrated circular shape but may be a polygonal shape such as a rectangular shape. Moreover, the vertical conductor 2 is not limited to the illustrated circular or cylindrical shape, either. It may have a prismatic shape.

(50) The vertical conductor 2 is filled in the vertical hole 20 extending along the thickness direction of the semiconductor substrate 1. Such vertical conductors 2 can be formed by applying a known technology such as a plating process, a molten metal filling process or a conductive paste filling process. The vertical conductors 2 are distributed in rows in a substrate surface. In the illustrated embodiment, the vertical conductor 2 is a through-electrode passing through the semiconductor substrate 1.

(51) The vertical conductors 2 are arranged at a given arrangement pitch as seen in a plane taken along the substrate surface. For example, the dimensions regarding the vertical conductors 2 are such that the arrangement pitch is in the range of 4 to 100 m and the maximum diameter is in the range of 0.5 to 25 m. However, the arrangement pitch is not required to be a certain size, while the diameter is not limited to the above value, either.

(52) FIGS. 7 and 8 illustrate still another embodiment. In this embodiment, the insulating layer 3 fills up a first hole 30 extending along the thickness direction of the semiconductor substrate 1, and the vertical conductor 2 fills up a second hole 20 that is formed in the insulating layer 3. Also in this embodiment, as shown in FIG. 3 under magnification, the insulating layer 3 is composed of the insulating particles 311 and the silica 330 filling up the space around the insulating particles 311, so that the vertical conductor 2 is electrically insulated from the semiconductor substrate 1 and the other vertical conductors 2.

(53) Also in the electronic device shown in FIGS. 7 and 8, since the insulating layer 3 is composed of the insulating particles 311 and the silica 330 filling up the space around the silica particles 311, there can be obtained the effects described with reference to FIGS. 4 and 5.

(54) Since the nanocomposite structure comprising a combination of the nm-sized insulating particles 311 and the silica 330 filling up the space around the silica particles 311 serves to relax the stress occurring in the vicinity of a through-electrode, the distance between the vertical conductor 2 forming the through-electrode and semiconductor circuit elements can be shortened to improve area efficiency for formation of the semiconductor circuit elements.

(55) In addition, since the insulating layer 3 insulates the vertical conductor 2 extending along the thickness direction of the semiconductor substrate 1 from the semiconductor substrate 1, the semiconductor substrate 1 and the vertical conductor 2, e.g., the through-electrode can be electrically insulated with the insulating layer 3 from the other vertical conductors 2 and the semiconductor circuit elements formed in the semiconductor substrate 1.

(56) Moreover, the insulating layer 3 can be formed by filling an insulating material into a ring-shaped groove or a hole extending along the thickness direction of the semiconductor substrate 1. The insulating layer 3 thus formed does not cost much and has a sufficient thickness commensurate with the diameter of the ring-shaped groove or the hole 30.

(57) Typically, such an electronic device can take the form of a three-dimensional system-in-package (3D-SiP). Specifically, it may be a system LSI, a memory LSI, an image sensor, a MEMS or the like. It may also be an electronic device including an analog or digital circuit, a memory circuit such as DRAM, a logic circuit such as CPU or the like or an electronic device that is obtained by preparing different types of circuits such as an analog high frequency circuit and a low frequency, low power consumption circuit in different processes and stacking them.

(58) More specifically, it includes most of electronic devices having an electronic circuit as a functional element, such as a sensor module, an optoelectronic module, a unipolar transistor, a MOS FET, a CMOS FET, a memory cell, integrated circuits (IC) thereof, or various scales of LSIs. In the present invention, integrated circuits called LSI include all types of integrated circuits such as a small-scale integration, a medium-scale integration, a large-scale integration, a very-large-scale integration (VLSI), an ultra-large-scale integration (ULSI), and so on.

(59) Even if the foregoing various types of electronic devices are different from the one disclosed in this specification regarding the stacking structure of substrates, the type of the semiconductor substrate 1, the shape, arrangement and hole diameter of the vertical conductors 2 passing through the semiconductor substrate 1 or the like, they can be included in the present invention as long as satisfying the present invention regarding the structure of the insulating layer 3 and the relationship of the insulating layer 3 to the vertical conductor 2.

(60) The present invention has been described in detail above with reference to preferred embodiments. However, obviously those skilled in the art could easily devise various modifications of the invention based on the technical concepts underlying the invention and teachings disclosed herein.