Device for generating a voltage reference comprising a non-volatile memory cell

Abstract

A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

Claims

1. A device for generating a reference voltage, the device comprising: a first non-volatile memory cell comprising a control-gate transistor and a reading transistor; and a second equivalent memory cell; wherein the control-gate transistor comprises a gate terminal, a body, a first conduction terminal, and a second conduction terminal, the first conduction terminal and the second conduction terminal being connected together to form a control-gate terminal; and wherein the reading transistor comprises a gate terminal connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal; wherein a source terminal of the first non-volatile memory cell and a source terminal of the second equivalent memory cell are connected together; and wherein the device is configured so that the reference voltage is acquired on the floating-gate terminal and is determined by conditions of supply of conduction terminals of the first non-volatile memory cell and the second equivalent memory cell.

2. The device according to claim 1, wherein the second equivalent memory cell includes a reading transistor that has a control-gate terminal connected to floating-gate terminal.

3. The device according to claim 1, wherein the second equivalent memory cell comprises a non-volatile memory cell comprising a control-gate transistor and a reading transistor and defining a second floating-gate terminal.

4. The device according to claim 1, wherein, in the first non-volatile memory cell, an area of the control-gate transistor is larger than an area of the reading transistor.

5. The device according to claim 4, wherein the area of the control-gate transistor and the area of the reading transistor are in a ratio 6:1.

6. The device according to claim 1, wherein, in the first non-volatile memory cell, an area of the control-gate transistor is smaller than an area of the reading transistor.

7. The device according to claim 6, wherein the area of the control-gate transistor and the area of the reading transistor are in a ratio 1:6.

8. The device according to claim 1, wherein the control-gate transistor and reading transistor comprise NMOS transistors.

9. The device according to claim 1, wherein the control-gate transistor and reading transistor comprise PMOS transistors.

10. A system comprising an operational amplifier and the device for generating a reference voltage according to claim 1, wherein the device for generating a reference voltage is inserted as a differential pair in the operational amplifier, wherein the control-gate terminal of the first non-volatile memory cell is connected on an inverting branch of the operational amplifier and a control-gate terminal of the second equivalent memory cell is connected on a non-inverting branch of the operational amplifier.

11. A device comprising: a first control-gate transistor comprising a gate terminal, a body, a first conduction terminal, and a second conduction terminal, the first conduction terminal and the second conduction terminal being connected together to form a first control-gate terminal; a first reading transistor comprising a gate terminal connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal, the gate terminal of the first reading transistor connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal; a second control-gate transistor comprising a gate terminal, a body, a fifth conduction terminal, and a sixth conduction terminal, the fifth conduction terminal and the sixth conduction terminal being connected together to form a second control-gate terminal; and a second reading transistor comprising a gate terminal, a body, a seventh conduction terminal and an eighth conduction terminal, the gate terminal of the second reading transistor connected to the gate terminal of the second control-gate transistor to form a floating-gate terminal, wherein the fourth conduction terminal and the eighth conduction terminal are connected together.

12. The device according to claim 11, wherein the device is configured so that a reference voltage is acquired on the first floating-gate terminal and is determined by conditions of supply of the first control-gate terminal, the second control-gate terminal, the third conduction terminal, the fourth conduction terminal, the seventh conduction terminal, and the eighth conduction terminal.

13. The device according to claim 11, wherein the device comprises a differential pair in an operational amplifier.

14. The device according to claim 13, wherein the first control-gate terminal is connected on an inverting branch of the operational amplifier and the second control-gate terminal is connected on a non-inverting branch of the operational amplifier.

15. The device according to claim 11, wherein the first control-gate transistor has an area that is larger than an area of the first reading transistor.

16. The device according to claim 11, wherein the first control-gate transistor has an area that is smaller than an area of the first reading transistor.

17. A device for generating a reference voltage, the device comprising: a first non-volatile memory cell comprising a first control-gate transistor and a first reading transistor; and a second non-volatile memory cell comprising a second control-gate transistor and a second reading transistor; wherein the first control-gate transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the drain terminal and the source terminal being connected together to form a first control-gate terminal; wherein the first reading transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the gate terminal of the first reading transistor being connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal; wherein the second control-gate transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the drain terminal and the source terminal being connected together to form a second control-gate terminal; wherein the second reading transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the gate terminal of the second reading transistor being connected to the gate terminal of the second control-gate transistor to form a second floating-gate terminal; and wherein the source terminal of the first reading transistor and the source terminal of the second reading transistor are connected together.

18. The device according to claim 17, wherein the device is configured so that a reference voltage is acquired on the first floating-gate terminal and is determined by conditions of supply of conduction terminals of the first non-volatile memory cell and the second non-volatile memory cell.

19. The device according to claim 17, wherein an area of the first control-gate transistor is at least six times larger than an area of the first reading transistor.

20. The device according to claim 17, wherein an area of the first control-gate transistor is at least six times smaller than an area of the first reading transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described purely by way of non-limiting example, with reference to annexed drawings, wherein:

(2) FIG. 1 shows a bandgap-voltage generation circuit;

(3) FIG. 2 shows an analogic non-volatile memory cell, the FGA cell manufactured by the company Xicor;

(4) FIG. 3 shows a voltage-generation device based upon a memory cell;

(5) FIG. 4 shows a floating-gate MOSFET in double-polysilicon technology;

(6) FIG. 5 shows a low-cost EEPROM memory cell in single-polysilicon technology;

(7) FIG. 6 shows a block diagram of a low-dropout (LDO) device;

(8) FIG. 7 shows an implementation of a single-polysilicon non-volatile memory cell;

(9) FIGS. 8A and 8B show embodiments of the solution proposed herein; and

(10) FIGS. 9 and 10 show two implementations of an LDO device.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(11) In the ensuing description, one or more specific details are illustrated, aimed at enabling an in-depth understanding of various embodiments provided by way of example. The embodiments may be obtained without one or more of the above specific details, or else with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not represented or described in detail so that some aspects of the embodiments will not be obscured.

(12) Reference to an embodiment or one embodiment in the framework of the present description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do necessarily refer to one and the same embodiment. In addition, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(13) The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(14) A different implementation of the analogic non-volatile memory (NVM) cell has been developed. The cell has been developed specifically for application in LDO voltage regulators.

(15) Of course, this fact does not limit its application to other types of integrated circuits (ICs).

(16) In addition, the above cell contains great potential as regards provision of voltage references, and in many cases this solution can substitute the conventional bandgap-reference (BGR) solution.

(17) The solution described herein mainly sets itself two primary objectives, namely, integration of the cells within LDO voltage regulators and the use of single-polysilicon-layer technology.

(18) The latter objective implies the use of a low-cost EEPROM solution where, instead of a double-polysilicon technology, as shown in FIG. 4, a single-polysilicon technology, as shown in FIG. 5, is used.

(19) The floating terminal in FIG. 5 is created by the lateral structure containing two adjacent MOSFETs with shorted gate terminals that represent the floating-gate terminal.

(20) The active area of the two MOSFETs present is shared in a non-uniform way. This causes an uneven distribution of the voltage on the two capacitors connected in series. By applying a high voltage across the structure, the capacitor with smaller area is subject to a higher voltage and approaches the breakdown voltage that leads to the Fowler-Nordheim tunnelling effect.

(21) This leads to the passage of charge towards the floating gate. After removal of the programming voltage, the charge remains trapped for a long time. By applying a voltage with opposite polarity, the charge stored can be removed via the same physical effect (Fowler-Nordheim).

(22) The key factor that affects retention of the charge is the thickness of the oxide tunnel, as shown by the example provided in Table 1 below.

(23) TABLE-US-00001 TABLE 1 Examples of time of charge retention as a function of oxide thickness Oxide thickness [nm] Time for 20% loss of charge 4.5 4 min 5 1 day 6 0.5 up to 6 yrs

(24) In addition to the above objectives, there exist also further electrical specifications that must be met for LDO devices.

(25) Consequently, various embodiments envisage integration of a non-volatile memory cell in a differential stage of the LDO error amplifier.

(26) The main diagram appears in FIG. 6. Consequently, the voltage stored behaves as an offset of the differential stage. Two approaches are possible. The offset voltage is incorporated in a single MOSFET or in both MOSFETs of the differential stage.

(27) Various embodiments are consequently possible, some of which are based upon a single-ended implementation and some of which are based upon the differential implementation (see FIGS. 9 and 10).

(28) Each embodiment presents some advantages, but also entails drawbacks. In particular, the single-ended version is easier to manage in terms of programming, but the precision could be worse. On the other hand, the differential version is more difficult to program, but the precision may be higher.

(29) Hence, as has already been the, one or more embodiments may be designed to generate a reference voltage Vref using an innovative integration of an analogic NVM cell as voltage reference with characteristics similar to the voltage references obtained with bandgap circuits.

(30) The new sphere of use imposes different considerations of an electrical nature as compared to the typical use of the cell as digital memory.

(31) Various embodiments propose a solution for providing an electronic device for the generation of reference voltages that are stable and independent of temperature.

(32) More in particular, the ensuing description is based upon the concept of floating gate (FG) that exists in an NVM cell. By floating gate is meant a node or terminal that has an electrical potential defined during programming/erasure and that remains practically unvaried in time (in a way independent of temperature).

(33) In various embodiments, the memory cell becomes the fundamental element of the differential pair of a feedback operational amplifier, generating at output a reference voltage that directly depends upon the potential present on the FG terminal (i.e., proportional to the charge stored in the memory).

(34) Consequently, it is possible to associate to the memory element a new analogic connotation with respect to the customary digital function.

(35) Various embodiments are based on the use of an innovative memory cell of a single-polysilicon FG type that can be implemented using a standard CMOS process and without the need to use of additional masks. Consequently, the above memory cell is obtained in single-polysilicon technology.

(36) The memory cell described and used herein has already formed the subject of a patent filed in the name of the present applicant entitled Memory device with single selection transistor, issued in January 2013 under No. IT0001397228 (and counterpart U.S. Pat. No. 8,693,256).

(37) The above memory cell has found wide use in EEPROM (Electrically Erasable Programmable Read-Only Memory) applications since, like the latter, also this memory cell makes it possible to modify the information contained inside it with very low levels of current consumptions enabling a high parallelism via the Fowler-Nordheim tunnelling phenomenon.

(38) Tunnelling is the mechanism of conduction through an insulating layer and is based upon the phenomenon whereby the wave function of the electron can penetrate through a potential barrier. This mechanism has a marked dependence upon the voltage applied, but basically also depends upon temperature.

(39) As is known, the tunnelling mechanisms may be direct or of a Fowler-Nordheim (FN) type. The Fowler-Nordheim phenomenon consists in tunnelling of electrons from the metal to the conduction band of the semiconductor, through a potential barrier of a triangular shape.

(40) Various embodiments advantageously enable precise voltage references to be obtained (for example, with a precision in the region of 3%, with possibility of even higher levels of precision), compensating the process spread with a considerable saving of area and consumption (1 A).

(41) In various embodiments, the possibility is exploited of creating electrical potentials in a floating terminal made available by the use of non-volatile memory cells as differential pair of an operational-amplifier structure, as shown in FIG. 8.

(42) Two alternative embodiments are proposed for implementation of this new function, as explained more fully hereinafter.

(43) In both embodiments, see FIG. 7, the floating-gate terminal FG is obtained by connecting together two NMOS transistors, i.e., NMOS1 and NMOS2, via their respective gate terminals.

(44) The floating-gate terminal FG is consequently obtained on the common-gate node of the two transistors NMOS1 and NMOS2. In particular, the first transistor NMOS1 is the control-gate transistor MCG, whereas the second transistor NMOS2 is the reading transistor Mread. Consequently, the respective gate are designated by Gcg and Gread.

(45) In particular, in the first transistor MCG the drain terminal Dcg and the source terminal Scg are connected together and define the control-gate terminal CG.

(46) The second transistor Mread has, instead, three conduction terminals, i.e., Dread, Sread, and PWread.

(47) Applied on the transistor MCG are the programming voltages for modifying the voltage on the intermediate floating-gate terminal FG.

(48) In various embodiments, the Fowler-Nordheim phenomenon is used for programming and erasing the analogic non-volatile memory cell NVMCE, according to the voltage applied to the intermediate floating terminal NW, and on the basis of the conditions of the other conduction terminals Dread, Sread, and PWread of the memory cell it is possible to program or erase the memory cell.

(49) As has been the previously, two different embodiments are possible.

(50) In a first embodiment, the cell has a control-gate transistor MCG (which functions as capacitor for driving capacitively the floating-gate terminal FG) of larger size than the reading transistor Mread. This embodiment may be defined as BIG Control Gate, in so far as in this case the area Acg of the control-gate transistor MCG is six times the area Aread of the reading transistor Mread, i.e., Acg=Aread.Math.6.

(51) In a second embodiment, the cell has a control-gate transistor MCG of smaller size than the reading transistor Mread. This embodiment may be defined as SMALL Control Gate, and in this case the area of the control-gate transistor is one sixth of the area Aread of the reading transistor Mread, i.e., Acg=Aread/6.

(52) The memory cells are described in the document U.S. Pat. No. 8,693,256.

(53) This geometrical flexibility of integration renders application even more general, enabling adaptation of the solution to different requirements of sizing of the operational amplifier.

(54) The programming and erasing functions are described hereinafter and summarized in Table 2.

(55) Table 2 highlights the three basic operations to be carried for use of the innovative memory cell.

(56) TABLE-US-00002 TABLE 2 Example of driving potentials of the analogic non-volatile memory cell NVMCE in the various operations; cell obtained in NMOS technology Cell Type Operation FG CGcg NW PWread Sread Dread Big Control Gate Program V Positive Positive High V High V Erase V Positive Positive Positive Positive High V High V High V High V Operating Retention Supply source drain voltage voltage Small Control Program V Positive Positive Positive Positive Gate High V High V High V High V Erase V Positive Positive Positive High V High V High V Operating Retention Positive source drain High V voltage voltage

(57) Both of the embodiments proposed enable biasing of the differential pair with currents of the order of hundreds of nanoamps, enabling creation of reference generators with levels of consumption lower than one milliamp.

(58) Appearing in Table 2 are examples of driving potentials of the analogic non-volatile memory cell NVMCE for the two embodiments, namely, for the BIG Control Gate and for the SMALL Control Gate.

(59) For each operation envisaged, namely, programming, erasure, and operation, indicated in the table are the potentials to be applied to the single control and conduction terminals, namely CGcg, NW, PWread, Sread, and Dread, and also the reaction that is obtained on the floating-gate terminal FG (V: voltage drops; V: voltage rises; Retention: voltage remains unvaried).

(60) In particular, the potential of the floating-gate terminal can be modified as described previously via external access to the terminals CG and NW, or by integrating a high-voltage-generator circuit (charge pump).

(61) As already mentioned previously, the cells shown in FIG. 7 may be integrated and inserted as differential pair of an operational amplifier, as shown in FIG. 8.

(62) FIG. 8A shows the single-ended embodiment, whereas FIG. 8B shows the differential embodiment.

(63) FIG. 8 shows two possible implementations that integrate a non-volatile memory cell.

(64) One or more embodiments may be based on a single-ended configuration (FIG. 8A), which envisages use of one non-volatile memory cell, or on a differential configuration (FIG. 8B), which envisages use of two non-volatile memory cells, as explained more fully hereinafter.

(65) In what follows, the structure of the operational amplifier as regards the biasing and compensation part will not be described in detail since these characteristics are not of interest in a preliminary analysis of the solution proposed herein.

(66) The memory cell proposed is a different physical and architectural integration that affords many advantages.

(67) Unlike the digital cell described in the document U.S. Pat. No. 8,693,256, the memory cell used herein acquires a new analogic connotation.

(68) As compared to the known solution, the selector has been removed, given that it is no longer necessary for this particular application, and the mechanism of injection and extraction of electrons from the floating gate (Fowler-Nordheim phenomenon) is advantageously used, thus drawing advantage from all the considerations of reliability already available in FG technology without any additional masks.

(69) The sizing may be rendered variable so as to maintain a degree of flexibility to be exploited in the design of the differential structure.

(70) In one embodiment, illustrated in FIG. 8A, the solution envisages a single analogic cell NVMCE (single-ended approach).

(71) This configuration reduces the area used and requires accessibility of a single control-gate terminal (CGcg) for enabling programming/erasure of the memory cell.

(72) This solution can be implemented by mirroring the differential pair, hence with the cost-effective analogic cell NVMCE connected on the inverting branch and an equivalent cell EQ connected on the non-inverting branch.

(73) In this case, the equivalent cell EQ has the control-gate terminal CGread connected to the floating gate of the reading transistor Mread of the equivalent cell and consequently cannot store charge (see FIG. 8A).

(74) Consequently, the device for generating a reference voltage Vref comprises an operational amplifier AO, a first non-volatile memory cell NVMCE, which includes a control-gate transistor MCG and a reading transistor Mread.

(75) The control-gate transistor MCG comprises a gate terminal Gcg, a body, and a first conduction terminal Dcg and a second conduction terminal Scg, connected together to form a control-gate terminal CGcg.

(76) Instead, the reading transistor Mread comprises a gate terminal Gread, connected to the gate terminal Gcg of the control-gate transistor to form a floating-gate terminal FG, a body, and a third conduction terminal Dread and a fourth conduction terminal Sread.

(77) The device also comprises a second memory cell.

(78) In various embodiments (FIG. 8A), the second cell is an equivalent memory cell EQ, whereas in alternative embodiments (FIG. 8B) the second cell is also a non-volatile memory cell NVMCE.

(79) In the device described herein the source terminal SreadNVM of the first non-volatile memory cell NVMCE and the source terminal Sreadeq of the second memory cell are connected together.

(80) In addition, the control-gate terminal CGcg of the first non-volatile memory cell NVMCE is connected on the inverting branch of the operational amplifier AO, and the control-gate terminal CGeq of the second, equivalent, memory cell EQ is connected on the non-inverting branch.

(81) Finally, the reference voltage Vref is acquired on the floating-gate terminal FG and is determined by the conditions of supply of the conduction terminals CGcg, Sread, and Dread of the two memory cells NVMCE, EQ.

(82) In an alternative embodiment, shown in FIG. 8B, the solution envisages the use of two cells NVMCE (differential approach).

(83) In this embodiment, there are two operative and accessible control-gate terminals CGcg and CGeq.

(84) This configuration enables a better performance to be achieved in terms of retention of the potential configured or else, given the same retention properties, higher output voltages to be reached.

(85) This embodiment requires, however, accessibility of two terminals (both of the control-gate terminals of the two cells) during programming/erasure. In this embodiment, particular attention is required in formation of the control-gate terminal CG of the cell on the feedback path.

(86) In various embodiments, it is possible to define the output voltage Vref or VOUT by appropriately configuring the potential of the floating-gate terminal FG of the memory cell, rendering the semiconductor used independent of the bandgap voltage.

(87) The embodiments proposed consequently present constructional advantages over normal implementations, which are summarized hereinafter.

(88) As a first advantage, the voltage generated on the floating-gate terminal is independent of the type of semiconductor used.

(89) Furthermore, there is obtained a reduction in the levels of consumption to achieve similar performance.

(90) Thanks to the structure used, a good independence of the output voltage from temperature is obtained.

(91) A further advantage is represented by the reduction of the passive and active components, which hence entail a reduction of the process spread intrinsic in the structure.

(92) By reducing the number of necessary components it is moreover possible to reduce the occupation of area of the structure for similar performance, a characteristic that is very positive in wearable devices.

(93) Furthermore, no particular attention is necessary at the level of layout for eliminating the systematic offset that is to be compensated intrinsically during programming/erasure of the analogic memory cell.

(94) As compared to known solutions, introduction of buffers downstream for driving the currents is consequently not necessary because the operational amplifier can be sized with the due driving capacity for generating the required currents.

(95) With the embodiments described herein, there is the possibility of regulating voltages that are higher than those regulated with the known bandgap solution, without the need for cascaded operational amplifiers and associated resistors for implementing gain structures. There is consequently an intrinsic gain in area and an increase in precision.

(96) Further advantages may be identified in an intrinsic configurability of the structure, which does not require digital calibration but only configuration of the potential of the terminal FG and hence enables output voltages VOUT to be obtained that are not fixed in the design stage, but are defined in-field for each chip according to the need through appropriate programming algorithms.

(97) In addition, two different embodiments are possible according to the design constraints and mission profile or other design choices/requirements.

(98) In order to improve the aspects of retention of the floating analogic potential present on the floating gate, there is proposed a division of the cell into various elements in parallel so as to reduce the effects of loss of electrical charge from the floating gate due to onset of defects in-field. In fact, if this phenomenon is local, with this solution would only have an impact on the element in which the loss of charge has been detected, with a lower incidence on the total charge stored.

(99) The cost-effective analogic cell NVMCE may be implemented also in PMOS version for generating a dual reference with respect to the supply VIN (FIGS. 9 and 10).

(100) Both with the PMOS implementation and with the NMOS implementation voltages of o V (Table 3) may be reached. This solution introduces objective advantages in some particular applications/uses, preserving all the aspects listed above of the NMOS version.

(101) All the foregoing considerations apply also to this implementation.

(102) TABLE-US-00003 TABLE 3 Driving potentials of the analogic non-volatile memory cell NVMCE in the various operations obtained in PMOS technology Cell Type Operation FG CG NW S D PMOS Program V Positive Big High V Control Gate Erase V Positive Positive Positive High V High V High V Operating Retention Supply Supply source drain voltage voltage PMOS Program V Positive Positive Positive Small High V High V High V Control Gate Erase V Positive High V Operating Retention Supply Supply source drain voltage voltage

(103) As has already been the previously, the main application of the voltage-regulator devices described herein is in LDO regulators with ultra-low quiescent current.

(104) The main purpose for development of LDO regulators was to achieve a quiescent current I.sub.Q of 20 nA. It is an ultra-low current that does not enable the use of complex structures.

(105) The architecture must reflect also the requirements of stability of the loop. On the basis of these requirements it has been decided to set the number of stages at two differential stages plus one power MOSFET.

(106) The main diagram of the regulator is illustrated in FIG. 4. The differential pair that incorporates the analogic NVM cell is based upon N-channel MOSFETs with floating gates. The polarity of the transistors has been selected for guaranteeing a common input voltage of the differential stage that can reach the level of the supply voltage (VIN).

(107) Since a current I.sub.Q of 20 nA does not enable use of any resistive divider, the level of voltage Vref stored inside must be equal to the nominal level VOUT. For this reason the operational amplifier AO works in unit-gain configuration.

(108) Two different implementations of the LDO circuit regulator have been developed. In the first, the single-ended configuration of the analogic NVM cell already described previously is used.

(109) The diagram is shown in FIG. 9. The memory cell is represented by the differential pair (M9, M8). In this configuration, just one of the two MOSFETs (the left-hand oneM9) maintains the charge/voltage programmed.

(110) The second (the right-hand oneM8) has the floating gate terminal shorted with the control gate in such a way that it is unable to store any charge/voltage; instead, it functions in active mode, receiving the feedback signal from the output.

(111) Electrically the pair behaves as a standard differential pair, but with a certain programmed offset.

(112) The pair is coupled to a set of current mirrors (M1, M2, M3, M4, M12, M14, M15, M16), which form a fully differential stage. In order to improve some electrical characteristics of the LDO, in particular the dropout voltage (VDROP), it is necessary to maximize the oscillation of the output voltage of the stage. For these reasons, the structure contains four branches that guarantee a rail-to-rail output.

(113) Generation of the tail current (ITail) represents a problem because the level is only of 9 nA.

(114) This problem is solved by the generator VGS/R based upon a self-biasing technique. The self-biasing cycle is incorporated in the left-hand side of the differential stage.

(115) Using the cascode potential of the low-side part (gates of M10, M11) and with the aid of M13 a constant potential is defined on the resistance R3, with consequent constant biasing current.

(116) The value of the resistance R3 is several tens of megaohms. Since the generator ITail is self-biased, it has two stable operating points. The operating point at zero current is avoided by a start-up circuit X1, which injects a small d.c. leakage current and a higher pulsed current during the start-up period.

(117) The start-up circuit is very important because the amplifier contains important charge-storage elements, but the biasing currents are ultra-low. In fact, the compensation network X4 connected between the gate and the drain of the power MOSFET M7 form an active integrator.

(118) In order to guarantee a reasonable start-up time in an interval of a few milliseconds it is necessary to increase the current of the differential stage in the start-up period.

(119) The level of I.sub.Q at 20 nA must be guaranteed only at zero load (zero load current ILOAD). In conditions of increased load it is possible to increase the current consumption.

(120) This entails two main advantages: better dynamic performance and easier frequency compensation.

(121) This is obtained by the adaptive biasing path copying the MOSFET M5 and the current mirror M14, M12.

(122) The copied MOSFET mirrors the current ILOAD. As the current ILOAD increases the total current frail increases. The present current interval ITail ranges from 20 nA to 30 A. The dropout condition represents the specific case where the current ILOAD may be, for example, zero, but the voltage VGS of the power MOSFET M7 may be maximum. From the standpoint of the level of I.sub.Q this is a critical condition because the current in the adaptive biasing path may be extremely high. To keep the current I.sub.Q under control a circuit X2 implemented in the biasing path is used. It enables reduction of the maximum level of the current ICopy1 and consequently of the total current I.sub.Q.

(123) The regulator is protected against overcurrent by the protection circuit X3. The level of the current ILOAD is detected by a copy branch formed by the MOSFET M6 and the resistance R2.

(124) The current ICopy2 is a small replica of the current ILOAD (assuming that there is a small voltage drop on R2). The voltage drop on R2, which corresponds to the level ILOAD, is processed by the overcurrent-protection block X3, where it is compared with an incorporated voltage offset. Once the threshold has been reached, the output of the block X3 starts to limit the voltage VGS of the power MOSFET M7 and hence to limit the maximum level of the current ILOAD.

(125) As mentioned previously, the regulator is built in two gain stages. In addition, it functions in conditions of high capacitive load. For stable operation it must be integrated with an adequate compensation network.

(126) In the diagram, the compensation network is represented by the block X4. It is based upon the principle of Miller adaptive compensation. It works between the gate and the source of the power MOSFET M7. The movement of the output pole is compensated by shifting of the zero guided by the current ILOAD.

(127) On account of the adaptive biasing technique used in the differential pair, also the non-dominant pole on the gate of the power MOSFET is moving. All these facts contribute to creating the well-compensated response system.

(128) For the programming procedure, the input VP is made accessible at package level. Normally, the pin will be connected to ground in use. In post-package programming, the pin will be supplied with high-voltage programming pulses. It must be able to receive high voltage in both of the polarities, enabling the operations of programming/erasure.

(129) The device is designed to work principally in closed-loop (regulation) condition, but it may happen that the supply voltage VIN can drop, forcing the loop into dropout mode. In this case, the quiescent current could increase by several orders of magnitude on account of the adaptive biasing circuit. The increase of the current I.sub.Q in this situation is kept under control by the block Dropout IQ ctrl X2.

(130) The second embodiment (FIG. 10) uses the differential version of the analogic NVM cell. In this case, both of the floating-gate terminals of the differential MOSFETs store a programmed charge of some sort.

(131) To enable programming of the floating-gate MOSFETs M9, M8, their gate terminals are connected outside the device.

(132) The pins must accept high programming voltages in both polarities. In normal operation, the input VP is at ground and the input VP/VFB is used as a feedback node for detection of the voltage VOUT.

(133) The differential pair is coupled with a current mirror M3, M4, which completes the differential stage. In this implementation, the differential stage is simpler than in the previous one. Only two branches are used. The output of the stage is quasi rail-to-rail with a small limitation in the low branch. This behavior is obtained with a specific constellation of the programmed voltages.

(134) The voltages programmed within the MOSFETs M9, M8 are fundamental for proper operation of the device. They not only define the level VOUT but also contribute to generation of the biasing current ITail and to definition of the oscillation of the output voltage. It is evident that the current ITail is defined merely by the resistor R3.

(135) To generate a constant biasing current it is necessary to define a constant voltage on the resistor.

(136) This is obtained by programming a fixed voltage level, around 1.2 V, in the left-hand device M9. This voltage ensures that the voltage on the resistor R3 will be (1.2 VVGS), and a constant current will flow in the differential stage. The MOSFET M8 on the right is programmed, according to the desired level VOUT, as follows:
V_M8=V_M9VOUT

(137) where V_M9=1.2 V

(138) This entails that to obtain a voltage VOUT>1.2 V the transistor M8 must be programmed with a negative voltage.

(139) This approach enables also a high oscillation on the output of the stage to be obtained. Since the voltage in the common source of the differential stage is equal to (1.2VVGS), the gate of the power MOSFET M7 may be brought down to this level.

(140) The start-up circuit X1 is simpler. It is used only for injection of a higher biasing current during the start-up period. In effect, the biasing-generation structure is not self-biased so that no zero operating point is present. In steady-state conditions, the current IStart is zero. All the other parts of the regulator are the same as in the previous case.

(141) There are various advantages in the differential embodiment of the analogic NVM cell. In particular, it is possible to obtain a greater precision because both of the devices of the differential pair are used in the same way.

(142) Thus the common-mode effects could be eliminated. Furthermore, the differential stage containing two branches is simpler.

(143) On the other hand, the structure presents some drawbacks. It is more difficult to manage the structure from the programming standpoint. Both of the gates of the floating-gate MOSFETs must be accessible from outside and must accept a high voltage in both polarities. Also the fact that the feedback signal passes through the floating gate of the MOSFET M8 (capacitive divider) lead to certain complications.

(144) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined in the ensuing claims.