MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT

Abstract

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

Claims

1-22. (canceled)

23. An apparatus comprising a power-converter circuit, said power-converter circuit comprising an interconnection, a first layer, and a second layer, wherein said first and second layers that are constituent layers of a stack of layers, wherein said first layer has a device face and a device-free face, wherein a first set of devices is disposed on said device face thereof, wherein said second layer has a device face and a device-free face, wherein said second layer comprises a second set of devices disposed on said device face thereof, wherein said interconnection is configured to enable said devices disposed on said device face of said first layer to be interconnected with said devices disposed on said device face of said second layer, wherein said interconnection comprises a thru via extending through at least one of said first layer and said second layer, wherein said first layer and said first second layer are wafer bonded to each other.

24. The apparatus of claim 23, wherein said first layer and said second layer are wafer bonded at said device faces thereof.

25. The apparatus of claim 23, wherein said wafer bond is a copper-copper bond.

26. The apparatus of claim 23, wherein said wafer bond is an oxide-oxide bond.

27. The apparatus of claim 23, wherein at least one of said devices comprises a trench capacitor.

28. The apparatus of claim 23, wherein said power-converter circuit implements a buck converter comprising a switched capacitor circuit.

29. The apparatus of claim 23, wherein said power-converter circuit further comprises vias extending through said first layer.

30. An apparatus comprising a power-converter circuit, wherein said power-converter circuit comprises an interconnection and a stack of layers, wherein said stack of layers comprises a first layer having a first layer thickness, wherein said first layer has a device face, a device-free face, and a first set of devices disposed on said device face thereof, wherein said second layer has a second layer thickness, wherein said second layer comprises a device face, a device-free face, and a set of devices disposed on said device face, wherein said interconnection is configured to enable said devices disposed on said device face of said first layer to be interconnected with said devices disposed on said device face of said second layer, wherein said first and second layers are arranged such that said device face of said first layer and said device face of said second layer are separated from each other by a distance that is greater than or equal to the lesser of said active layer thickness and said passive layer thickness.

31. The apparatus of claim 30, wherein said distance is greater than or equal to the sum of said first layer thickness and said second layer thickness.

32. The apparatus of claim 30, wherein said interconnection is disposed between said first layer and said second layer.

33. The apparatus of claim 30, wherein said interconnection is disposed between said device face of said second layer and said device-free face of said first layer.

34. The apparatus of claim 30, wherein said interconnection is disposed between said device face of said first layer and said device-free face of said second layer.

35. The apparatus of claim 30, wherein said interconnection is in contact with solder bumps.

36. The apparatus of claim 30, further comprising a cap layer of said stack, wherein said interconnection is disposed on said cap layer, and wherein one of said first and second layers is constituent of said cap layer.

37. The apparatus of claim 30, wherein said power-converter circuit implements a switched capacitor circuit.

38. The apparatus of claim 30, further comprising one or more additional layers, at least one of which comprises a second layer containing a second set of devices.

39. The apparatus of claim 38, wherein said one or more additional layers comprise a second layer having a face on which a third set of devices is disposed and a third layer having a face on which a fourth set of devices is disposed, and wherein said face on which said fourth set of devices is disposed faces said face on which said third set of devices is disposed.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0042] FIG. 1A is a block diagram of a known power converter architecture;

[0043] FIG. 1B is a particular implementation of the converter architecture shown in FIG. 1;

[0044] FIG. 1C is a side view of the power converter illustrated in FIG. 1B;

[0045] FIG. 1D is a top view of the power converter illustrated in FIG. 1B;

[0046] FIGS. 2A-2C are side views of various power converters with integrated capacitors;

[0047] FIG. 3A is a circuit diagram of a power converter with integrated capacitors;

[0048] FIG. 3B is a top view of one layout of the power converter whose circuit is shown in FIG. 3A;

[0049] FIG. 4 is a circuit diagram of a four-level buck converter with integrated capacitors;

[0050] FIG. 5 is a side view of a power converter with generic device layers;

[0051] FIGS. 6A-6C are three side views of a power converter in which an active device layer is between a passive device layer and an electrical interface;

[0052] FIGS. 6D-6F are three side views of a power converter in which a passive device layer is between an active layer and the electrical interface;

[0053] FIG. 7A is a side view of a power converter with a planar capacitor;

[0054] FIG. 7B is a side view of a power converter with a trench capacitor;

[0055] FIG. 8A is a particular implementation of the power converter shown in FIG. 6B;

[0056] FIG. 8B is a particular implementation of the power converter shown in FIG. 6A;

[0057] FIG. 9A shows a parasitic network between the active and passive layer with one node;

[0058] FIG. 9B shows a parasitic network between the active and passive layer with three nodes;

[0059] FIG. 10A is a block diagram of a partitioned power converter;

[0060] FIG. 10B is a top view of a particular implementation of the partitioned power converter shown in FIG. 10A;

[0061] FIG. 10C is a close up of a switched capacitor unit from the partitioned power converter implementation illustrated in FIG. 10B;

[0062] FIG. 10D is a close up of one switch from the switched capacitor unit illustrated in FIG. 10C;

[0063] FIG. 11 is a top view of an alternative implementation of the partitioned power converter shown in FIG. 10A.

DETAILED DESCRIPTION

[0064] Power converters that use capacitors to transfer energy have certain disadvantages when packaged in the traditional way. Such power converters require a larger number of components and a larger number of pins than conventional topologies. For example, power converter 20 requires two additional capacitors and four additional pins when compared to a buck converter.

[0065] Furthermore, extra energy is lost due to parasitic losses in the interconnection structure between the additional capacitors and the devices in the switch network. The devices and methods described herein address these issues by vertically integrating the passive devices with the active devices within a power converter.

[0066] Embodiments described herein generally include three components: a passive device layer 41A, also referred to a passive layer, an active device layer 42A, also referred to as an active layer, and an interconnect structure 43B. Each layer has devices that will typically be integrated on a single monolithic substrate or on multiple monolithic substrates, both of which may also be incorporated within a reconstituted wafer as in the case of fan-out wafer scale packaging. The passive layer 41A can be fabricated by an IPD process while the active layer 42A can be fabricated by a CMOS process. Each device layer pair is electrically connected together through a high density interconnect structure, which may also include a redistribution layer or micro bumps.

[0067] Additionally, thru vias 47A can be included which allow electrical connections to additional device layers. In the case of a single monolithic substrate, the thru vias may include thru silicon vias, whereas in the case of a reconstituted wafer, the thru vias may include thru mold vias.

[0068] Side views of three different embodiments with thru vias 47A are illustrated in FIGS. 2A-2C. These are only a few of the possible permutations. Each side-view includes at least a passive layer 41A, an active layer 42A, thru vias 47A, and an interconnect structure 43B.

[0069] The passive layer 41A includes passive devices such as capacitors, inductors, and resistors. The active layer 42A includes active devices such as transistors and diodes. The interconnect structure 43B provides electrical connections between the passive layer 41A and the active layer 42A. Meanwhile, thru vias 47A allow for electrical connections to pass thru the passive layer 41A or thru the active layer 42A.

[0070] The interconnect structure 43B can also provide electrical connection between devices on the same layer. For example, separate active devices in different locations on the active layer 42A can be electrically connected using the interconnect structure 43B.

[0071] In the particular embodiment shown in FIG. 2A, the passive layer 41A is between the active layer 42A and the electrical interface 28. An interconnect structure 43B provides interconnections between devices on the active layer 42A and devices on the passive layer 41A. The interconnect structure 43B in some cases can also provide electrical connections between two devices that are on the same passive layer 41A or two devices on the same active layer 42A. Each device layer 41A, 42A has a device face on which the devices are actually formed. The locations of these device faces are indicated by the pair of arrows.

[0072] In the embodiment of FIG. 2A, the device face on the active layer 42A faces, or is opposed to, the device face on the passive layer 41A. Thru vias 41A cut through the passive layer and connect to the interconnect structure 43B. Thus, the path between devices on layers separated by intervening layers generally includes at least a portion through an interconnect structure 34B and a portion through a via 41A. In this way, the interconnect structure 34B provides electrical continuity between devices in different layers, whether the layers are adjacent or otherwise.

[0073] In the alternative embodiment shown in FIG. 2B, the active layer 42A is between the passive layer 41A and the electrical interface 28. Thru vias 42A in this case pass through the active layer 42A. Once again, an interconnect structure 43B_connects the passive devices on the passive layer 41A, the active devices on the active layer 42A, and the thru vias 47A. Once again, as indicated by the arrows, the device face of the passive layer 41A and the device face of the active layer 42A are opposite each other.

[0074] As shown in yet another embodiment in FIG. 2C, it is also possible to use more than two device layers by stacking one or more passive layers and one or more active layers. In the particular embodiment shown in FIG. 2C, such a stack includes_first and second passive layers 41A-41B capped by an active layer 42A. The embodiment further includes a first interconnect structure 43B between the first and second passive layers 41A, 41B and a second interconnect structure 43C between the second passive layer 41B and the active layer 42A. As indicated by the arrows, the device faces of the second passive layer 41B and the active layer 42A face each other, but the device faces of the first and second passive layers 41A, 41B do not.

[0075] The embodiment shown in FIG. 2A-2C can be used to eliminate the pin count penalty in power converter 20 shown in FIG. 1B.

[0076] As illustrated in FIG. 3A, the discrete capacitors C21, C22, CIN1 in the power converter 20 are replaced by integrated capacitors C31, C32, CIN2 respectively that are all placed on a passive layer 41A (not shown). Meanwhile, the active devices S1-S7, SL-SH, and control circuit 23 are all included in a separate active layer 42A that would be stacked relative to the passive layer as suggested by FIGS. 2A-2C. The resulting power converter 30A has three fewer discrete capacitors and four fewer pins than the power converter 20.

[0077] A top view of the power converter 30A in FIG. 3B illustrates the disposition of active and passive devices on separate layers coplanar with an xy plane defined by the x and y axes shown and stacked along a z axis perpendicular to the xy plane. The capacitors C31, C32, CIN2 are disposed on a device face of a passive layer over a device face of an active layer, on which are formed active devices S1-S7.

[0078] Each capacitor is arranged such that it is directly above the particular active device to which it is to be electrically connected. For example, a first capacitor C31 is directly above switches S1-S4. This is consistent with FIG. 3A, which shows that the positive terminal of the first capacitor C31 is to be connected to first and second switches S1, S2 while the negative terminal of the first capacitor C31 is to be connected to third and fourth switches S3, S4. This arrangement shortens the distance current needs to flow between the active devices and the passive devices in comparison to the arrangement illustrated in FIG. 1B-1D, thereby reducing the energy loss.

[0079] FIG. 3B shows another power converter 30B, often referred to as a four-level flying capacitor buck converter. It is a particular implementation of a multi-level buck converter. Other examples include three-level fly capacitor buck converters and five-level capacitor buck converters. Such power converters incorporate a switched-capacitor circuit and can readily be implemented using stacked layers as illustrated in FIGS. 2A-2C.

[0080] If the power converter 30B is implemented using the embodiment illustrated in FIG. 2A, then the device stack 33B includes a top active layer 42A and a bottom passive layer 41A. The active devices S31-S36 are included in the active layer 42A, while the fly capacitors C3A-C3B are included in the passive layer 41A. The fly capacitors C3A-C3B are vertically disposed below the active devices S31-S36 to reduce the energy loss in the electrical interconnection.

[0081] In operation, the input voltage VIN is chopped using the active devices S31-S36 and the two fly capacitors C3A-C3B. This results in a pulsating voltage at an output node LX. This pulsating voltage is presented to an LC filter represented by a filter inductor L31 and a load capacitor CL, thereby producing an output voltage VO, which is the average of the voltage at the LX node.

[0082] In the remaining description of FIG. 4, the power converter 30B is assumed to be connected to a 12 volt source 14 and to provide 4 volts to the load 18A. The power converter 30B is in one of eight different states. Depending upon the state, the voltage at the output node LX is 12 volts, 8 volts, 4 volts or 0 volts, assuming that the first fly capacitor C3A is charged to 8 volts and that the second fly capacitor C3B is charged to 4 volts.

[0083] The power converter 30B alternates between combinations of the states depending upon the desired output voltage VO. Additionally, the duration of time the power converter 30B is in each state enables regulation of the output voltage VO. It is important to note that the power converter 30B always operates such that the fly capacitors C3A-C3B are charged as much as they are discharged. This maintains a constant average voltage across the fly capacitors C3A-C3B.

[0084] A generalization of the embodiments illustrated in FIGS. 2A-2C is illustrated in FIG. 5, which includes four device layers 44A-44D. In general, at least two device layers are required, one of which includes active devices and the other of which includes passive devices. Typically, the pitch of the interconnect structure 43A-43D is finer than the pitch of the bumps 45, such as solder balls, gold studs, and copper pillars, that couple the power converter to the electrical interface 28. The individual capacitors in the layer with passive devices are sized and arranged so as to fit above or below one or more active devices. Furthermore, the switched capacitor elements are also partitioned and laid out in a specific way to reduce parasitic energy loss in the interconnect structures.

[0085] Since semiconductor processing is sequential, it is common to only process one side of a wafer. This adds one more dimension to the number of possible permutations. Assuming there is one active layer 42A, one passive layer 41A, one device face per layer, and thru vias 47A, there are a total of eight different ways of arranging the two layers.

[0086] FIGS. 6A-6C and FIG. 2A illustrate the four possible combinations in which the passive layer 41A is on top and the active layer 42A is on the bottom. As used herein, a bottom layer is the layer closest to the electrical interface and the top layer is the layer furthest from the electrical interface.

[0087] In FIG. 6A, the interconnect structure 43A electrically connects the active devices in layer 42A to thru vias 47A and bumps 45. Similarly, the interconnect structure 43B electrically connects the passive devices in layer 41A to thru vias 47A. As indicated by the arrows, the device faces of the passive and active layers 41A, 42A face away from each other.

[0088] In FIG. 6B, the interconnect structure 43B electrically connects the active devices in layer 42A to thru vias 47A and thru vias 47B. Similarly, the interconnect structure 43C electrically connects the passive devices in layer 41A to thru vias 47B. As indicated by the arrows, the device faces of the passive and active layers 41A, 42A face away from each other.

[0089] Lastly, in FIG. 6C, the interconnect structure 43A electrically connects the active devices in 42A to thru vias 47A and bumps 45. Similarly, the interconnect structure 43C electrically connects the passive devices in layer 41A to thru vias 47B. As indicated by the arrows, the device faces of the passive and active layers 41A, 42A, face away from each other.

[0090] In comparison, FIGS. 6D-6F and FIG. 2B illustrate the four possible combinations in which the active layer 42A is on top and the passive layer 41A is on the bottom.

[0091] In FIGS. 6D-6F, the active layer 42A and the passive layer 41A are electrically connected together as described in connection with FIGS. 6A-6C. The choice of configuration depends upon numerous factors, most of which relate to thru via technology and to the number of pins to the outside world. For example, if there are a larger number of electrical connections between the passive layer 41A and active layer 42A than to the outside world than the configurations illustrated in FIG. 2A & FIG. 2B are more desirable. However, if the opposite is true than the configurations illustrated in FIG. 6A and FIG. 6D are more desirable.

[0092] The passive substrate and active substrate can be in any form when attached, such as singulated dice or full wafers. Two different implementations that are amenable to die-to-die attachment are shown in FIGS. 7A-7B. Each implementation includes a different type of capacitor.

[0093] The capacitors can be of any structure. However, trench capacitors have a capacitance per unit area that is one to two orders of magnitude higher than that of an equivalent planar capacitor, and also have lower equivalent series resistance than equivalent planar capacitors. Both of these capacitor attributes are desirable for use in power converters that use capacitive energy transfer because they favorably affect the efficiency of the power converter.

[0094] In the embodiment shown in FIG. 7A, the passive layer 41A includes a planar capacitor 71A and the active layer 42A includes active devices 75. In contrast, the embodiment shown in FIG. 7B, includes a trench capacitor 71B in its passive layer 41A.

[0095] The interconnect structure 43B electrically connects the devices within the passive layer 41A to the devices within the active layer 42A. The interconnect structure 43B can be implemented in numerous ways, one of which are illustrated in FIGS. 7A and 7B.

[0096] In the case of FIGS. 7A-7B, the interconnect structure 43B is composed of a multilayer interconnect structure 72 on the passive substrate, a single layer of solder bumps 73, and a multilayer interconnect structure 70 on the active substrate.

[0097] The bumps 45 are not visible in FIGS. 7A-7B because their pitch on the electrical interface 28 is typically much larger than the interconnect structure 43B. However, to connect to the outside world, some form of connection, such as bumps 45 along with thru vias 47A, is useful.

[0098] The bumps 45 can either be located above the passive layer 41A or below the active layer 42A. In the case in which the bumps 45 are located above the passive layer 41A, the thru vias cut 47A through the passive layer 41A as illustrated in FIG. 2B. In the case in which the bumps 45 are located below the active layer 42A, the thru vias 47A cut through the active layer 42A as illustrated in FIG. 2A.

[0099] Embodiments of this invention can also be implemented with wafer-to-wafer stacking as shown in FIGS. 8A-8B. The embodiment illustrated in FIG. 8A is a particular implementation of FIG. 6B, whereas, the embodiment illustrated in FIG. 8B is a particular implementation of FIG. 6A.

[0100] The two wafers are electrically connected together using a bonding layer 83 instead of using solder bumps 73 as in the case of FIGS. 7A-7B. There are numerous types of wafer-to-wafer bonding process. Among these are copper-copper bonding, oxide-oxide bonding, and adhesive bonding. Furthermore, FIGS. 8A-8B illustrate the thru vias 47A and their respective bumps 45, which were absent in FIGS. 7A-7B.

[0101] Power converters that rely on capacitors to transfer energy generally have complex networks with many switches and capacitors. The sheer number of these components and the complexity of the resulting network make it difficult to create efficient electrical interconnections between switches and capacitors.

[0102] Typically, metal layers on an integrated circuit or on integrated passive device are quite thin. Because thin metal layers generally offer higher resistance, it is desirable to prevent lateral current flow. This can be accomplished by controlling the electrical paths used for current flow through the power converter. To further reduce energy loss resulting from having to traverse these electrical paths, it is desirable to minimize the distance the current has to travel. If properly done, significant reductions energy loss in the interconnect structure can be realized. This is accomplished using two techniques.

[0103] One way to apply the foregoing techniques to reduce interconnection losses is to partition the switched capacitor element 12A into switched capacitor units operated in parallel, but not electrically connected in parallel. Another way is to choose the shape and location of the switches on the die to fit optimally beneath the capacitors and vice versa.

[0104] Partitioning the SC element 12A is effective because it reduces the horizontal current flow that has always been seen as inevitable when routing physically large switches and capacitors to a single connection point or node as depicted in FIG. 9A.

[0105] As is apparent from FIG. 9A, current in a physically large component will tend to spread out across the component. To the extent it spreads in the lateral direction, its path through the material becomes longer. This is shown in FIG. 9A by noting the difference between the path length between the two nodes through the center switch and the path length between the two nodes through the lateral switches. This additional path length results in loss, represented in the equivalent circuit by RP1.

[0106] By partitioning the component into smaller sections, one can equalize the path length differences between the two nodes, thus reducing associated losses. For example, if the switch and the capacitor in FIG. 9A are partitioned into three sections, the equivalent circuit is approximately that shown in FIG. 9B, in which the lumped resistances associated with the path between nodes is represented by a smaller lumped resistance RP2.

[0107] FIGS. 10A-10D illustrate the application of both of these techniques to the implementation of a power converter.

[0108] As shown in FIG. 10A, the regulating and switching components of a power converter 90 are partitioned to encourage a more direct electrical path between them, and to minimize any lateral current flow. In the particular example of FIG. 10A, the power converter 90 includes a switched capacitor unit 92A connected to a regulating circuit unit 94A at a first node VX1, a switched capacitor unit 92B connected to regulating circuit unit 94B at a second node VX2, and a switched capacitor unit 92C and regulating circuit unit 94C connected at a third node VX3. Furthermore, first inductor L91, second inductor L92, and third inductor L93 are located at the output of each regulating circuit units 94A-94C. These inductors L91-L93 are then shorted together at the load.

[0109] Although FIG. 10A shows both the regulating circuit 16A and the switching capacitor element 12A as both being partitioned, this is not necessary. It is permissible to partition one and not the other. For example, in the embodiment shown in FIG. 11, only the switching capacitor element 12A has been partitioned. A corollary that is apparent from the embodiment shown in FIG. 11 is that the number of partitions of regulating circuit 16A and the number of partitions of the switched capacitor element 12A need not be the same, as is the case in the particular example shown in FIG. 10A.

[0110] A top view of the power converter 90 shown in FIG. 10A is illustrated in FIG. 10B. The switched capacitor units 92A-92C extend along they direction, where the first switched capacitor unit 92A is at the top, the second switched capacitor unit 92B is in the middle, and the third switched capacitor unit 92C is at the bottom. The regulating circuit units 94A-94C extend along they direction as well.

[0111] Like the power converter 30A shown in FIGS. 3A-3B, the device stack 96 includes a top passive layer 41A and a bottom active layer 42A. The capacitors within the switched capacitor units 92A-92C are included in the passive layer 41A, whereas the active devices within the switched capacitor units 92A-92C and regulating circuit units 94A-94C are include in the active layer 42A.

[0112] As shown in the top view of FIG. 10C, switched capacitor unit 92A includes seven power switches S1A-S7A, two pump capacitors C31A-C31B, and a control/driver circuit 23A. The exact size of the active devices need not be the same size as the passive elements for the first loss-reduction technique to be effective. They simply need to be underneath the passive devices. This arrangement allows for more uniform current distribution and reduced wire length in the interconnect structure of the power converter.

[0113] Furthermore, within each switched capacitor unit 92A-92C, the power switches and pump capacitors can be divided up into smaller subunits. This allows for an additional reduction in lateral current flow. An example of the power switch S1A divided up into nine sub units S9A-S9I is illustrated in FIG. 10D.

[0114] Since the single monolithic switched capacitor element 12A is divided up into numerous smaller switched capacitor units 92A-92C and placed so as to encourage current in only one direction as shown in FIG. 10B, the equivalent circuit becomes like that in FIG. 9B, thus reducing overall losses.

[0115] The technique is effective because the total capacitance increases when capacitors are placed in parallel. For example, this technique is far less effective with inductors because total inductance decreases when inductors are placed in parallel.

[0116] Another possible arrangement of the switched capacitor cells is shown in FIG. 11, in which the switched capacitor element is partitioned into small switched capacitor units 92A-92F along both the x and y direction. The exact size and dimensions of the switched capacitor units 92A-92F depend upon many characteristics such as metal thickness, capacitance density, step-down ratio, etc. Both of these techniques reduce the vertical and lateral distance between the switch devices and the passive devices while also providing a uniform current distribution to each individual switch and/or switched capacitor cell. Thus, the parasitic resistance and inductance of the connection between the switches and capacitors is minimized. This is important because the parasitic inductance limits the speed at which the converter can operate and hence its ultimate size while the parasitic resistance limits the efficiency of the power conversion process.

[0117] Among other advantages, the arrangements described above avoids the component and pin count penalty, reduces the energy loss in the parasitic interconnect structures and reduces the total solution footprint of power converters that use capacitors to transfer energy.

[0118] An apparatus as described herein finds numerous applications in the field of consumer electronics, particularly smart phones, tablet computers, and portable computers. In each of these cases, there are displays, including touch screen displays, as well as data processing elements and/or radio transceivers that consume power provided by the apparatus described herein.