Back-end electrically programmable fuse

Abstract

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Claims

1. A method comprising: providing a structure including a hard mask over a first dielectric layer, wherein said hard mask is disposed over a second dielectric layer, said second dielectric layer is directly disposed over a conductive line formed in said first dielectric layer; forming a first opening and a second opening through said hard mask; forming a third opening and a fourth opening in a resist that is formed over said hard mask and in said first opening and in said second opening wherein, said third opening being misaligned with said first opening to expose a sidewall of said first opening and to partially overlap said first opening to define an overlap portion, said overlap portion having a sub-ground rule dimension, said sidewall including an exposed portion of said hard mask, and said fourth opening being fully aligned within said second opening to not expose said hard mask; etching a first portion of said second dielectric layer that is exposed by said overlap portion using said resist and said hard mask including the sidewall as a mask to form a first via cavity in said second dielectric layer, wherein said hard mask is not etched and said first via cavity fully overlies the conductive line and has a dimension specified by said sub-groundrule dimension of said overlap portion; removing said resist to re-expose said first opening; and etching another portion of said second dielectric layer that is exposed by said first opening to form a trench in said second dielectric layer intersecting said first via cavity.

2. The method of claim 1 wherein said trench and said first via cavity are formed by a dual damascene process.

3. The method of claim 2 wherein said conductive line is connected as a cathode and a feature formed by filling said trench is connected as an anode.

4. The method of claim 2 further comprising filling said trench and said first via cavity with copper by CVD or by electroplating.

5. The method of claim 1 wherein said third opening and said fourth opening has a dimension equal to or greater than a groundrule dimension.

6. The method of claim 1 wherein said trench has a dimension equal to or greater than a groundrule dimension.

7. The method of claim 1, further comprising exposing said conductive line at a bottom of said first via cavity.

8. The method of claim 1 wherein said sub-groundrule dimension of said overlap portion is selected according to a target programming current.

9. The method of claim 1 wherein said first opening has a dimension equal to or greater than a groundrule dimension.

10. The method of claim 1 wherein said first opening and said second opening are formed in said hard mask without etching said second dielectric layer.

11. The method of claim 1 wherein etching a first portion of said second dielectric layer further comprises etching a second portion of said second dielectric layer that is exposed by said third opening to form a second via cavity that is fully aligned within said second opening, said second via cavity having at least a ground rule dimension.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features and elements of the present invention are described below in conjunction with the accompanying figures.

(2) FIG. 1A illustrates a conventional back-end e-fuse.

(3) FIG. 1B illustrates pitch and critical dimension for a given lithography.

(4) FIGS. 2A and 2B illustrate a prior art back-end e-fuse.

(5) FIGS. 3A and 3B illustrate side views of an embodiment of the present BEOL e-fuse respectively parallel and perpendicular to the major axis of the upper line.

(6) FIG. 3C is a plan view of an embodiment of the BEOL e-fuse of the present invention.

(7) FIGS. 4A to 4F illustrate a method to form the BEOL e-fuse of the present invention.

(8) FIGS. 5A, 5B, 6, 7, and 8 illustrate different embodiments of a BEOL e-fuse according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(9) The present invention provides a back end of the line (BEOL) fuse structure which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The present e-fuse includes a sub-lithographic via coupled between two BEOL conductive features such as lines, a first of such feature being connected as a cathode and a second of such feature being connected as an anode. The cross section of this sub-lithographic via can be tuned to match the target programming current.

(10) It will be understood that when a first element as a layer, region or substrate is referred to as being on or over a second element, it can be directly on such second element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or directly over a second element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, the two elements can be directly connected or coupled or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present. It is noted that like reference numerals refer to like elements across different embodiments, and that the drawings are not necessarily drawn to scale.

(11) Referring now to FIGS. 3A and 3B, the present e-fuse structure is formed in interconnect metal layers formed on a semiconductor substrate 300. One or more semiconductor devices (not shown) can be formed in or on top surface 301 of the substrate. A so-called middle of the line (MOL) layer 302 which includes structures such as gate contacts formed through a layer of passivation material typically separates surface 301 from a first interconnect layer 310 (M1) which includes conductive line 312 in trench 311 formed within interlayer dielectric (ILD) 315. Lines formed within M1 may conductively connect to the gate contacts which contacts may be tungsten studs. At least a second interconnect layer 320 is disposed over layer 310 and includes conductive line 322 in trench 321 and conductive via 324 in via cavity 323 formed within ILD 325. ILD 325 can be separated from ILD 315 by a cap layer 319.

(12) The interconnect layer directly overlying the M1 layer can be referred to as the M2 layer. As noted, conductive line 322 is formed in at least a second interconnect layer overlying a first interconnect layer 310. A first interconnect layer can be referred to as the M1 layer, and the next overlying interconnect layer as the M2, etc. Within any given Mx layer is formed the Mx lines and the Vx1 vias. A Vx1 via can, for example, connect an Mx line and an Mx1 line.

(13) FIG. 3C depicts the patterns produced by a pair of masks which define the Mx+1 trenches and Vx vias onto a plan view of the Mx features (x=1, 2, 3, etc.). As shown in FIG. 3C, trench 321 overlies trench 311. Cavity 323 extends from trench 321 to trench 311. The width of either or both of trench 321 and trench 311 is greater than or equal to W, the groundrule dimension. At least one edge E of cavity 323 is coplanar or in perfect alignment with an edge T of trench 321. The larger cross sectional dimension G of cavity 323 can be as large as the groundrule dimension and the smaller cross sectional dimension L is less than G, so that the cross sectional area of via 324 can be significantly smaller than the cross sectional area of line 322.

(14) The BEOL e-fuse of the present invention is formed according to a line-first dual damascene scheme illustrated in FIGS. 4A-4F. FIG. 4A illustrates lower conductive lines 412a and 412b formed in a lower layer ILD 415 and covered by cap layer 419. Lower interconnect layer 410 (Mx) is formed on a structure such as a semiconductor wafer (not shown). Over layer 410 is formed a second ILD layer 425, a hard mask 426, and a photoresist 427. A line pattern is created in photoresist 427 by standard photolithography. Line openings P, Q, and R have length and width according to the chip design embodied in an associated line mask (not shown). Line openings P, Q and R can be patterned at the critical dimension (width W), or they can be wider.

(15) In FIG. 4B, openings P, Q, and R are transferred to hardmask 426 and photoresist 427 is removed per known processing. The steps to this point are consistent with the line-first dual damascene scheme disclosed in Low-k Interconnect Stack with a Novel Self-Aligned Via Patterning Process for 32 nm High Volume Manufacturing by R. Brain, et al. (Logic Technology Development, #Quality & Reliability, Intel Corp.)). R. Brain et al propose a line-first scheme to maintain dimensional integrity of a patterned via and avoid the tendency in a via-first scheme for the via pattern to enlarge and thereby short with adjacent features.

(16) According to the present invention, rather than maintaining the patterned via dimension, the process is altered to reliably form a sub-lithographic via. FIG. 4C shows a second resist layer 428 formed over hardmask 426, and patterned according to a second mask defining vias (not shown). The illustrated embodiment depicts two groundrule (width=W) via openings A and B patterned into via resist 428. According to the chip design (embodied by the mask pair for the corresponding Mx+1 line and Mx via), via opening A can be fully aligned within line opening P, while via opening B can be intentionally misaligned with line opening Q to partially overlie the hardmask by distance W. The lower section of FIG. 4C illustrates the relative position of openings P, Q, and R (as Mx+1) and A and B (as Vx) overlying the Mx lines. (Note that the via pattern can be other than a circle; e.g., it can be oblong, rectilinear, square or irregular. This invention does not require any specific via shape, and references to a via diameter herein contemplate the circular equivalent of any via shape embodied in a via mask.)

(17) In FIG. 4D, the intersection of the Mx via and Mx+1 line opening pairs is transferred into ILD 425 such as by selective dielectric reactive ion etching (RIE) process. The via opening A is fully aligned within or encompassed by line opening P, so via A is the same width as via opening A (bounded by the capability of the etch process). As noted, openings A and B were patterned as groundrule dimension openings, so via A will have the same groundrule dimension W and can be referred to as a groundrule via. Via opening B is misaligned with line opening Q, such that a portion of via opening B is blocked by the hardmask 426. That part of via opening B which overlies the hardmask does not get transferred into the dielectric 425. The RIE process is designed to be stopped by the hardmask. The resulting physical opening B in the dielectric has smaller cross section than via opening B in the resist pattern. Via opening B therefore has a sub-lithographic dimension and can be referred to as a sub-groundrule via. Note, however, that the present invention is not limited to via openings that are the minimum lithographic dimension. Sub-lithographic via B could result as the intersection of line opening Q and via opening B, even if via opening B (and/or line opening Q) were larger than the groundrule dimension.

(18) While FIG. 4D shows the via etch reaching to cap 419, the via etch can stop earlier. The via etch might even continue into cap 419. Referring now to FIG. 4E, regardless of the via etch depth, processing can proceed conventionally to remove via resist 428. Further etching can form trenches P, Q and R in ILD 425. The initial via etch can be timed such that the trench etch completes the via etch, which may continue through cap 419 at the bottom of vias A and B. The completed Mx+1 and Vx features shown in FIG. 4F can be formed according to standard dual damascene metallization by depositing a barrier/liner and a seed layer, copper fill and anneal, and chemical-mechanical planarization. In embodiments, the barrier can be PVD Ta(N); the liner can be CVD tungsten (W), titanium (Ti), cobalt (Co), titanium nitride (TiN), ruthenium nitride (RuN), ruthenium (Ru), etc.; and the seed can be PVD copper (Cu), or copper alloyed with a minority component which can be manganese (Mn), aluminum (Al), tin (Sn), indium (In), or others. Copper fill can be done by CVD or electroplating, and may include bottom-up techniques to fill sub-lithographic cavities. In embodiments, the liner CVD process can deposit cobalt from C12H10O6(Co)2 (dicobalt hexacarbonyl tert-butylacetylene), ruthenium from triruthenium dodecacarbonyl (Ru3(CO)12), or tungsten from tungsten hexacarbonyl.

(19) The above-described method can be used to form the BEOL e-fuse illustrated in FIGS. 3A and 3B, where line 322 is connected as the anode and line 312 is connected as the cathode. Via 324 has a sub-groundrule dimension which can be sized according to the programming current. Specifically, referring back to FIG. 4C, if groundrule via pattern B were only slightly misaligned to line opening Q, the cross section of a resulting sub-groundrule via B would be only slightly smaller than that of a groundrule via, such as within the range of 70 to <100% of the groundrule dimension. But via pattern B can overlie the hardmask edge by more, and the designed pattern offset can be adjusted to form an e-fuse link having any sub-lithographic cross sectional area, for example 40% or 50% of the groundrule dimension. According to the present invention, the e-fuse link can be sized to correspond to a target programming current. For example, it may be preferred to blow a particular BEOL e-fuse using a minimal programming current in order to avoid stressing materials comprising or adjacent to the programming current path. The e-fuse link in such case could utilize a groundrule via pattern that only slightly aligns with a line opening.

(20) FIGS. 3A, B, and C illustrate a sub-lithographic via connecting lines in adjacent interconnect layers (i.e., Vx, Mx and Mx+1), but this invention is not so limited. FIG. 5A illustrates that sub-ground rule via 524 can connect overlying line 522 to underlying plate 512. Via 524 can be formed by offsetting via opening 529 relative to a hardmask patterned for line 522. Note that via opening 529 could be somewhat larger than the minimum dimension of the lithography, so long as the intersection of opening 529 and 522 is sub-groundrule. FIG. 5B illustrates another embodiment wherein a sub-ground rule via 534 is formed between layers other than M1, such as between line 532 in M3 and line 522 in M2. As shown in FIG. 6, according to yet another embodiment, a sub-lithographic via 624 can be formed by offsetting a via pattern 629 to overlap the end of line pattern 622. The sub-lithographic via formed by such end overlap may be programmable at lower current than a via formed by an equivalent offset relative to an edge of a line, due to foreshortening of the line pattern at its end. As noted, programming at low current can be advantageous in the immediate vicinity of certain devices. FIG. 7 illustrates yet another embodiment wherein the anode 732 and cathode 712 are in non-adjacent layers and are connected by a stack comprising normal via 734, intermediate line 722, and sub-lithographic via 724. FIG. 8 illustrates yet another embodiment wherein the anode 832 and cathode 812 are connected by a stack comprising sub-lithographic via 834, intermediate line 822, and sub-lithographic via 824.

(21) Yet other embodiments have the anode and cathode in same interconnect layer, such as in M2, with the anode and cathode connected through a third line by a path including a sub-lithographic via. To leverage the presence of a grain boundary between dual damascene Mx and Vx features, when that third line is in a layer above the anode and cathode, the BEOL eFuse can include a sub-lithographic via between the cathode and the third line, and when such third line is in a layer below the anode and cathode, the BEOL eFuse can include a sub-lithographic via between the third line and the anode.

(22) The substrate 300 herein may comprise any semiconductor such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors may be used. In addition to these listed types of semiconducting materials, the present invention also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs). Further, substrate 300 can be single crystalline, polycrystalline, amorphous, or have a combination of at least two of a single crystalline portion, a polycrystalline portion, and an amorphous portion.

(23) Any suitable dielectric material may be used for the dielectric materials of layers x15 and x25 (where x stands for the corresponding Figure number), and the material used for x15 can be the same or different as that for x25. The dielectric material can have dielectric constant less than 3.9, or for so-called low-k dielectric materials between 2.5-3.0, or for so-called ultra low-k materials even lower such as about 2.2. The dielectric material can be any now known or later developed porous or non-porous dielectric material such as silicon oxide (SiO), silicon nitride (Si.sub.3N.sub.4), hydrogenated silicon oxycarbide (SiCOH), silsesquioxanes, carbon-doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), spin-on silicon-carbon contained polymer material available from JSR Corporation, and other low dielectric constant materials or layers thereof.

(24) A dielectric barrier layer or capping layer can be disposed above each of dielectric material layer. The material used for each cap layer x19 or x29 is typically selected to be resistant to the etch and clean processes for the immediately overlying materials. Cap layers can be the same or different materials. Typical materials for the capping layer include any now known or later developed dielectric such a silicon carbide (SiC), silicon nitride (Si.sub.3N.sub.4), silicon dioxide (SiO.sub.2), and nitrogen or hydrogen doped silicon carbide (SiC(N,H)).

(25) Any suitable conductive material may be used for conductors x12, x22 and x24, and each such conductor can be the same or different material from any other. Typical conductive materials include copper (Cu), aluminum (Al), Tungsten (W), silver (Ag), gold (Au) and alloys.

(26) While the present invention has been particularly shown and described with respect to preferred or alternative embodiments, it will be understood by those skilled in the art that further alternatives are possible and may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated.