Manufacturing method of silicon carbide semiconductor device

Abstract

A method of manufacturing a silicon carbide semiconductor device includes grinding a back surface of a semiconductor substrate formed of silicon carbide to reduce thickness thereof and provide an altered layer that is ground; removing by polishing or etching, the altered layer from the back surface; forming a nickel film on the back surface of the semiconductor substrate after removing the altered layer; heat treating the nickel film to forming a nickel silicide layer by silicidation; and forming a metal electrode on a surface of the nickel silicide layer.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, comprising: forming a silicon carbide epitaxial layer on a front surface of a semiconductor substrate formed of silicon carbide: after said forming a silicon carbide epitaxial layer, grinding a back surface of the semiconductor substrate to reduce thickness thereof and provide an altered layer that is ground; removing by polishing or etching, the altered layer from the back surface; forming a nickel film on the back surface of the semiconductor substrate after removing the altered layer; heat treating the nickel film to forming a nickel silicide layer by silicidation; and forming a metal electrode on a surface of the nickel silicide layer.

2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein polishing is accomplished by chemical-mechanical polishing.

3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein etching is accomplished by dry etching or wet etching.

4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein removing includes reducing the thickness of the semiconductor substrate 100 nm or more.

5. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein grinding the back surface of the semiconductor substrate includes growing an epitaxial layer on a front surface of the semiconductor substrate, wherein growing further includes growing a sublimation layer on the back surface of the semiconductor substrate, and wherein grinding includes removing the sublimation layer and removing the surface layer of the back surface of the semiconductor substrate.

6. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal electrode is formed by one of sequential deposition of a titanium film, a nickel film and a silver film, and sequential deposition of a titanium film, a nickel film and a gold film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of one example of a silicon carbide semiconductor device manufactured by a manufacturing method of a silicon carbide semiconductor device according to an embodiment;

(2) FIGS. 2, 3, 4, 5, 6, and 7 are cross-sectional views schematically depicting states during the manufacture of a silicon carbide semiconductor device according to the embodiment; and

(3) FIGS. 8 and 9 are cross sectional views depicting states during the manufacture of a conventional silicon carbide semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) Preferred embodiments of a manufacturing method of a silicon carbide semiconductor device will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or . In the description of the embodiments below and the accompanying drawings, identical constituent elements will be given the same reference numerals and will not repeatedly be described.

EMBODIMENT

(5) Concerning a structure of a silicon carbide semiconductor device produced (manufactured) by the manufacturing method of a silicon carbide semiconductor device according to an embodiment, a vertical insulated gate field effect transistor (MOSFET) will be described as an example. FIG. 1 is a cross-sectional view of one example of a silicon carbide semiconductor device manufactured by the manufacturing method of a silicon carbide semiconductor device according to the embodiment. As depicted in FIG. 1, in a silicon carbide semiconductor device according to the embodiment, on a front surface of an n.sup.+ type semiconductor substrate (hereinafter, n.sup.+-type SiC substrate) 1 formed of silicon carbide (SiC), an n.sup.-type SiC epitaxial layer 2 is formed. On a surface layer of a surface of the n.sup.-type SiC epitaxial layer 2, on the opposite side of the n.sup.-type SiC epitaxial layer 2 with respect to the n.sup.+-type SiC substrate 1 side of the n.sup.-type SiC epitaxial layer 2, a p-type base layer 3 is selectively provided. Inside the p-type base layer 3, an n.sup.+-type source layer 4 and a p.sup.+-type contact layer 5 are selectively provided. The n.sup.+-type source layer 4 and the p.sup.+-type contact layer 5 contact each other.

(6) On a surface of a portion of the p-type base layer 3 between the n.sup.-type SiC epitaxial layer 2 and the n.sup.+-type source layer 4, a gate electrode 7 is provided via a gate insulating film 6. A source electrode 9 is provided to contact the n.sup.+-type source layer 4 and the p.sup.+-type contact layer 5 via a nickel silicide layer 10, and to be electrically insulated from the gate electrode 7 by an interlayer insulating film 8. A contact (electrical contact unit) of a SiC portion (the n.sup.+-type source layer 4 and the p.sup.+-type contact layer 5) and the nickel silicide layer 10 is an ohmic contact. In a back surface of the n.sup.+-type SiC substrate 1, a nickel silicide layer 11 is provided. A contact of the n.sup.+-type SiC substrate 1 and the nickel silicide layer 11 is an ohmic contact. A back surface electrode 12, which is a drain electrode, contacts the nickel silicide layer 11.

(7) The manufacturing method of a silicon carbide semiconductor device according to the embodiment will be described. FIGS. 2, 3, 4, 5, 6, and 7 are cross-sectional views schematically depicting states during the manufacture of a silicon carbide semiconductor device according to the embodiment. As depicted in FIG. 2, on the front surface of the n.sup.+-type SiC substrate (semiconductor wafer) 1, for example, the n.sup.-type SiC epitaxial layer 2 of a 15 m thickness is epitaxially grown. At this time, on the back surface of the n.sup.+-type SiC substrate 1, for example, a n.sup.-type SiC sublimation layer (hereinafter, back surface n.sup.-type SiC sublimation layer) 21 of a 3 m thickness is grown. The back surface n.sup.-type SiC sublimation layer 21 is a layer having a lower impurity concentration than that of the n.sup.+-type SiC substrate 1 and is not necessary in the completed silicon carbide semiconductor device. Therefore, as depicted in FIG. 3, after the back surface n.sup.-type SiC sublimation layer 21 is removed by grinding, the exposed back surface of the n.sup.+-type SiC substrate 1 is polished.

(8) More specifically, for example, using an abrasive wheel having abrading grains of a grit size of about #2000, the back surface n.sup.-type SiC sublimation layer 21 is roughly ground from the back surface side of the n.sup.+-type SiC substrate 1 to reduce the thickness of the n.sup.+-type SiC substrate 1, about 20 m, including the thickness of the back surface n.sup.-type SiC sublimation layer 21, for example. Next, for example, using an abrasive wheel having abrading grains of a grit size of about #7000, finish grinding is performed on the roughly ground back surface of the n.sup.+-type SiC substrate 1 to further reduce the thickness of the n.sup.+-type SiC substrate 1 about 5 m, for example. The reason for such extensive grinding up to the surface layer of n.sup.+-type SiC substrate 1 and exceeding the thickness of the back surface n.sup.-type SiC sublimation layer 21 is that even in cases where the n.sup.+-type SiC substrate 1 is warped or there are differences in grinding thickness, the back surface n.sup.-type SiC sublimation layer 21 can be completely removed. The grit size of the abrading grains, for example, is a size within a range described in a table of grit sizes of abrading materials for abrasive wheels (Bonded Abrasive Grain Sizes) defined under Japanese Industrial Standard (JIS) R6001:1998.

(9) Surface roughness Ra of the finish-ground back surface of the n.sup.+-type SiC substrate 1 is 3 nm, which is large. Further, in the surface layer of the finish-ground back surface of the n.sup.+-type SiC substrate 1, an altered layer (not depicted) in which the crystalline structure is disturbed occurs having a thickness of, for example, about 70 nm from the ground surface. Inside this altered layer, carbon is uniformly distributed. When the altered layer occurs inside the n.sup.+-type SiC substrate 1, consequent to heat treatment thereafter, carbon is prone to be deposited in a layer in a portion where the altered layer occurs. Therefore, after the back surface of the n.sup.+-type SiC substrate 1 is finish-ground, the finish-ground back surface of the n.sup.+-type SiC substrate 1, for example, is chemical mechanical polished (CMP) and the thickness of the n.sup.+-type SiC substrate 1 is further reduced about 100 nm or more, whereby the altered layer that formed in the surface layer of the back surface of the n.sup.+-type SiC substrate 1 is removed. The surface roughness Ra of the back surface of the n.sup.+-type SiC substrate 1 after CMP is preferably, for example, 0.1 nm or less. The total thickness of the n.sup.+-type SiC substrate 1 and the n.sup.-type SiC epitaxial layer 2 before grinding and polishing is determined such that the thickness of the product after grinding and polishing remains.

(10) Next, as depicted in FIG. 4, ion implantation of a p-type impurity for forming the p-type base layer 3, ion implantation of an n-type impurity for forming the n.sup.+-type source layer 4, and ion implantation of a p-type impurity for forming the p.sup.+-type contact layer 5 are sequentially performed; and the p-type base layer 3, n.sup.+-type source layer 4, and the p.sup.+-type contact layer 5 are formed inside the n.sup.-type SiC epitaxial layer 2. The sequence of the ion implantation of an n-type impurity for forming the n.sup.+-type source layer 4 and the ion implantation of a p-type impurity for forming the p.sup.+-type contact layer 5 may be interchanged. Next, for example, heat treatment at 1800 degrees C. is performed, and the impurities implanted to form the p-type base layer 3, the n.sup.+-type source layer 4, and the p.sup.+-type contact layer 5 are activated.

(11) Next, as depicted in FIG. 5, on the entire surface of the n.sup.-type SiC epitaxial layer 2, the gate insulating film 6 is formed. Next, after an impurity-doped polysilicon film is deposited on the gate insulating film 6, the polysilicon film is pattered and the gate electrode 7 is formed. Next, after the interlayer insulating film 8 is formed to cover the gate electrode 7, the interlayer insulating film 8 and the gate insulating film 6 are selectively removed, whereby a contact hole 22 that exposes the n.sup.+-type source layer 4 and the p.sup.+-type contact layer 5 is formed. Next, as depicted in FIG. 6, a nickel film is formed on the entire back surface of the n.sup.+-type SiC substrate 1 after the CMP and on the surface of the silicon portion (the n.sup.+-type source layer 4 and the p.sup.+-type contact layer 5) exposed by the contact hole 22.

(12) Next, for example, the nickel films formed on the substrate front surface side and back surface side are subject to silicidation by rapid heat treatment (RTA), and the nickel silicide layers 10, 11 are formed on the surface of the silicon portion exposed by the contact hole 22 and on the entire polished back surface of the n.sup.+-type SiC substrate 1, respectively. As a result, contact of the silicon portion exposed by the contact hole 22 and the nickel silicide layer 10, and contact of the n.sup.+-type SiC substrate 1 and the nickel silicide layer 11 are ohmic contacts. Next, on the surface of the nickel silicide layer 10 on the front surface side of the n.sup.+-type SiC substrate 1, an aluminum film is deposited and the source electrode 9 is formed. Meanwhile, on the surface of the nickel silicide layer 11 on the back surface side of the n.sup.+-type SiC substrate 1, a titanium (Ti) film, a nickel (Ni) film, and a silver (Ag) film are sequentially deposited and the back surface electrode 12 is formed. In place of the silver (Ag) film, a gold (Au) may be deposited, or an alloy that includes silver, gold, etc. may be deposited. Further, the nickel (Ni) film may also be an alloy of nickel and vanadium (V). Thereafter, the semiconductor wafer (epitaxial wafer formed by stacking of the n.sup.-type SiC epitaxial layer 2 on the n.sup.+-type SiC substrate 1) is cut (diced) into chip-shapes whereby, the vertical MOSFET depicted in FIG. 1 is completed.

(13) As described, an altered layer that occurs in the surface layer of the ground back surface of the n.sup.+-type SiC substrate 1 is removed before the nickel silicide layer 11 is formed on the back surface of the n.sup.+-type SiC substrate 1. Therefore, as depicted in FIG. 7, even when various types of heat treatment (e.g., heat treatment for forming the nickel silicide layer 11, heat treatment for forming the source electrode 9, the back surface electrode 12, etc.) are performed after the altered layer is removed, when the nickel silicide layer 11 is formed, carbon (refer to equation (1)) 11a occurring inside the nickel silicide layer 11 is uniformly distributed inside the nickel silicide layer 11 and does not agglomerate. Thus, inside the nickel silicide layer 11, the carbon does not agglomerate to form brittle deposits having low adhesion and therefore, peeling of the back surface electrode 12 caused by carbon included inside the nickel silicide layer 11 can be prevented.

(14) As described, according to the embodiment, by removing by polishing, an altered layer occurring in the ground surface layer of the n.sup.+-type SiC substrate, the deposition of agglomerated carbon inside the nickel silicide layer consequent to subsequent heat treatment can be prevented. As a result, for example, when the semiconductor wafer is diced into chips, peeling of the back surface electrode caused by the carbon included inside the nickel silicide layer can be prevented. Therefore, peeling of the back surface electrode can be sufficiently suppressed, enabling the yield ratio to be improved.

(15) In the description above, although the present disclosure is described taking a MOSFET as an example, without limitation hereto, application may be to other semiconductor devices that use SiC such as insulated-gate bipolar transistors (IGBT), diodes, and the like. In the described embodiment, although description is given taking a case where an altered layer occurring in the surface layer of the ground back surface of the n.sup.+-type SiC substrate is removed by CMP, without limitation hereto, the altered layer may be removed by dry etching, wet etching, etc. Further, in the described embodiment, although description is given using the epitaxial substrate of the n.sup.-type SiC epitaxial layer stacked on the n.sup.+-type SiC substrate, without limitation hereto, an n.sup.+-type SiC substrate equivalent in thickness to the described epitaxial substrate may be used. The present disclosure is further applicable in cases where the conductivity types (n-type, p-type) of the semiconductor layer or the semiconductor region are reversed in the described embodiment.

(16) As described, by removing by polishing or etching, an altered layer occurring in the ground surface layer of the SiC substrate, the deposition of agglomerated carbon inside the nickel silicide layer consequent to subsequent heat treatment can be prevented. As a result, for example, when the semiconductor wafer is diced into chips, peeling of the back surface electrode caused by carbon included inside the nickel silicide layer can be prevented.

(17) The manufacturing method of a silicon carbide semiconductor device according the present disclosure achieves an effect in that peeling of the back surface electrode can be suppressed.

(18) As described, the manufacturing method of a silicon carbide semiconductor device according to the present disclosure is useful for power semiconductor devices equipped with a metal electrode forming an ohmic contact with a silicon carbide semiconductor.

(19) Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.