Manufacturing method of a pixel structure

Abstract

The present invention provides a pixel structure and a manufacturing method thereof. The pixel structure includes: a transparent substrate (60), a gate line formed on the transparent substrate (60), a thin-film transistor formed on the transparent substrate (60), a data line (68) formed on the transparent substrate (60), a pixel electrode (62) formed on the transparent substrate (60) and the thin-film transistor, a passivation layer (64) formed on the pixel electrode (62), the transparent substrate (60), and the data line (68), and a common electrode (66) formed on the passivation layer (64). The passivation layer (64) includes: a first portion (72) located on the data line (68), a second portion (74) located on the pixel electrode (62), and a third portion (76) located on the transparent substrate (60) and arranged on two opposite sides of the data line (68). The first portion (72) of the passivation layer (64) has a thickness greater than a thickness of the second portion (74).

Claims

1. A manufacturing method of a pixel structure, comprising the following steps: providing a transparent substrate; depositing a data line and a pixel electrode on the transparent substrate; depositing a passivation layer on the transparent substrate, the data line, and the pixel electrode, wherein the passivation layer comprises: a first portion located on the data line, a second portion located on the pixel electrode, and a third portion located on the transparent substrate and arranged on two opposite sides of the data line, a part of the third portion being located between and connecting between the first portion and the second portion; subjecting the passivation layer to etching to reduce a thickness of the second portion of the passivation layer such that a thickness of the first portion of the passivation layer is greater than a thickness of the second portion and also, the thickness of the first portion of the passivation layer is greater than a thickness of the third portion and a top of the second portion of the passivation layer is flush with a top of the part of the third portion connecting between the first portion and the second portion, wherein the top of the second portion and the top of the part of the third portion collectively define a flat surface extending continuously to an edge of the first portion; and depositing a common electrode on the passivation layer such that a portion of the common electrode that corresponds to a portion of the pixel electrode is laid flat directly on the flat surface defined collectively by the top of the second portion and the top of the part of the third portion.

2. The manufacturing method of the pixel structure as claimed in claim 1, wherein the pixel electrode is a transparent conductive layer and the common electrode is a transparent conductive layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The technical solution, as well as beneficial advantages, of the present invention will be apparent from the following detailed description of an embodiment of the present invention, with reference to the attached drawings. In the drawings:

(2) FIG. 1 is a schematic view showing the structure of a conventional pixel;

(3) FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;

(4) FIG. 3 is a flow chart illustrating a manufacturing process of a conventional pixel structure;

(5) FIG. 4 is a schematic view showing a pixel structure according to the present invention;

(6) FIG. 5 is a flow chart illustrating a manufacturing method of a pixel structure according to an embodiment of the present invention;

(7) FIG. 6 schematically shows the structure at various steps of the manufacturing method of FIG. 5;

(8) FIG. 7 is a flow chart illustrating a manufacturing method of a pixel structure according to another embodiment of the present invention; and

(9) FIG. 8 schematically shows the structure at various steps of the manufacturing method of FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(10) To further expound the technical solution adopted in the present invention and the advantages thereof, a detailed description is given to a preferred embodiment of the present invention and the attached drawings.

(11) Referring to FIG. 4, the present invention provides a pixel structure, which comprises:

(12) a transparent substrate 60, a gate line (not shown for the purposes of easy observation) formed on the transparent substrate 60, a thin-film transistor (not shown for the purposes of easy observation) formed on the transparent substrate 60, a data line 68 formed on the transparent substrate 60, a pixel electrode 62 formed on the transparent substrate 60 and the thin-film transistor, a passivation layer 64 formed on the pixel electrode 62, the transparent substrate 60, and the data line 68, and a common electrode 66 formed on the passivation layer 64.

(13) The passivation layer 64 comprises: a first portion 72 located on the data line 68, a second portion 74 located on the pixel electrode 62, and a third portion 76 that is located on the transparent substrate 60 and arranged on two opposite sides of the data line 68. The first portion 72 of the passivation layer 64 has a thickness that is greater than a thickness of the second portion 74. The pixel electrode 62 and the common electrode 66 partly overlap so as to form a storage capacitance C.sub.st. The present invention increases the distance between the data line 68 and the common electrode 66 to reduce parasitic capacitance C.sub.parasitic and at the same time reduces the distance between the pixel electrode 62 and the common electrode 66 to increase the storage capacitance C.sub.st so as to reduce the influence of a feed-through voltage and electrical leakage on the displaying quality of an FFS liquid crystal display that uses the pixel structure.

(14) The transparent substrate is a glass substrate. The pixel structure further comprises a protective layer (not shown) formed between the thin-film transistor and the pixel electrode 62.

(15) The thickness of the first portion 72 of the passivation layer 64 is also greater than a thickness of the third portion 76. Preferably, the second portion 74 of the passivation layer 64 has a top that is substantially flush with a top of the third portion 76.

(16) The thin-film transistor functions to respond to a scanning signal of the gate line to apply a data signal of the data line 68 to the storage capacitance C.sub.st formed by partly overlapping between the pixel electrode 62 and the common electrode 66 and comprises a gate terminal, a drain terminal, and a source terminal. The gate terminal is electrically connected to the gate line. The source terminal is electrically connected to the data line 68. The drain terminal is electrically connected to the pixel electrode 62.

(17) The common electrode 66 comprises a part 82 that is located on the data line 68 and another part 84 located on the pixel electrode 62. In the instant embodiment, the pixel electrode 62 is a transparent conductive layer and the common electrode 66 is also a transparent conductive layer.

(18) Referring to FIGS. 4-6, the present invention also provides a manufacturing method of a pixel structure, which comprises the following steps:

(19) Step 11: providing a transparent substrate 60.

(20) The transparent substrate 60 is a glass substrate.

(21) Step 12: depositing a gate line, a thin-film transistor, a data line 68, and a pixel electrode 62 on the transparent substrate 60.

(22) The processes used to form the gate line, the thin-film transistor, the data line 68, and the pixel electrode 62 can be any known operations.

(23) The step further comprises forming a protective layer on the transparent substrate 60 so that the protective layer is arranged between the thin-film transistor and the pixel electrode 62. The process used to form the protective layer can identical to any known operation.

(24) The thin-film transistor comprises a gate terminal, a drain terminal and a source terminal. The gate terminal is electrically connected to the gate line. The source terminal is electrically connected to the data line 68. The drain terminal of the thin-film transistor is electrically connected to the pixel electrode 62 is order apply a data signal of the data line 68 to the storage capacitance C.sub.st. The pixel electrode 62 is a transparent conductive layer.

(25) Step 13: depositing a passivation layer 64 on the transparent substrate 60, wherein the passivation layer 64 comprises: a first portion 72 located on the data line 68, a second portion 74 located on the pixel electrode 62, and a third portion 76 located on the transparent substrate 60 and arranged on two opposite sides of the data line 68.

(26) Step 14: applying etching to a portion of the passivation layer 64 on a peripheral circuit so as to complete a first time etching and then subjecting the second portion 74 of the passivation layer 64 to etching so as to complete a second time etching to reduce a thickness of the second portion 74 of the passivation layer 64 thereby making a thickness of the first portion 72 of the passivation layer 64 greater than the thickness of the second portion 74.

(27) The second time etching of Step 14 further comprises etching applied to the third portion 76 of the passivation layer 64 so that after the completion of the second time etching, the thickness of the first portion 72 of the passivation layer 64 is greater than the thickness of the third portion 76. Preferably, a top of the second portion 74 of the passivation layer 64 is substantially flush with a top of the third portion 76.

(28) Step 15: depositing a common electrode 66 on the passivation layer 64.

(29) The common electrode 66 is a transparent conductive layer, which comprises a part 82 that is located on the data line 68 and another part 84 located on the pixel electrode 62. In the present invention, the thickness of the first portion 72 of the passivation layer 64 is greater than the thickness of the second portion 74. In other words, while the distance between the data line 68 and the common electrode 66 is enlarged to decrease the parasitic capacitance C.sub.parasitic, the distance between the pixel electrode 62 and the common electrode 66 is reduced to increase the storage capacitance C.sub.st, in order to reduce the influence of a feed-through voltage and electrical leakage on displaying quality of an FFS liquid crystal display using the pixel structure.

(30) Referring to FIGS. 7 and 8, with simultaneous reference to FIG. 4, the present invention further provides a manufacturing method of a pixel structure, which comprises the following steps:

(31) Step 21: providing a transparent substrate 60.

(32) The transparent substrate 60 is a glass substrate.

(33) Step 22: depositing a gate line, a thin-film transistor, a data line 68, and a pixel electrode 62 on the transparent substrate 60.

(34) The processes used to form the gate line, the thin-film transistor, the data line 68, and the pixel electrode 62 can be any known operations.

(35) The step further comprises forming a protective layer on the transparent substrate 60 so that the protective layer is arranged between the thin-film transistor and the pixel electrode 62. The process used to form the protective layer can identical to any known operation.

(36) The thin-film transistor comprises a gate terminal, a drain terminal and a source terminal. The gate terminal is electrically connected to the gate line. The source terminal is electrically connected to the data line 68. The drain terminal of the thin-film transistor is electrically connected to the pixel electrode 62 is order apply a data signal of the data line 68 to the storage capacitance C.sub.st.

(37) The pixel electrode 62 is a transparent conductive layer.

(38) Step 23: depositing a first passivation layer 92 on the transparent substrate 60, the data line 68, and the pixel electrode 62 and subjecting the first passivation layer 92 to etching in such a way that only a portion of the first passivation layer 92 that is located on the data line 68 is preserved, while a remaining portion is removed.

(39) Step 24: depositing a second passivation layer 94 on the transparent substrate 60, the pixel electrode 62, and the first passivation layer 92 and subjecting the second passivation layer 94 to etching in such a way that a portion of the second passivation layer 94 on a peripheral circuit is removed, while a remaining portion is preserved.

(40) In the instant embodiment, the first passivation layer 92 has a thickness greater than a thickness of the second passivation layer 94.

(41) Step 25: depositing a common electrode 66 on the second passivation layer 94.

(42) The common electrode 66 is a transparent conductive layer, which comprises a part 82 that is located on the data line 68 and another part 84 located on the pixel electrode 62.

(43) Arranged between the data line 68 and the common electrode 66 comprises the first and second passivation layers 92, 94, while only the second passivation layer 94 is located between the pixel electrode 62 and the common electrode 66 so that the distance between the data line 68 and the common electrode 66 is greater than the distance between the pixel electrode 62 and the common electrode 66, whereby while the distance between the data line 68 and the common electrode 66 is enlarged to decrease the parasitic capacitance C.sub.parasitic, the distance between the pixel electrode 62 and the common electrode 66 is reduced to increase the storage capacitance C.sub.st, in order to reduce the influence of a feed-through voltage and electrical leakage on displaying quality of an FFS liquid crystal display using the pixel structure.

(44) In summary, the present invention provides a pixel structure and a manufacturing method thereof, wherein a second time etching operation or a two-layered structure of passivation layer is adopted to reduce the distance between a common electrode and a pixel electrode so as to increase storage capacitance of the pixel structure and at the same time, the distance between a data line and the common electrode is increased to reduce harmful parasitic capacitance so as to reduce the influence of a feed-through voltage and electrical leakage on displaying quality of an FFS liquid crystal display that uses the pixel structure. Further, the manufacturing method of the pixel structure is relatively simple.

(45) Based on the description given above, those having ordinary skills of the art may easily contemplate various changes and modifications of the technical solution and technical ideas of the present invention and all these changes and modifications are considered within the protection scope of right for the present invention.