Substrate composite, method and device for bonding of substrates
09682539 ยท 2017-06-20
Inventors
Cpc classification
H01L2224/73204
ELECTRICITY
H01L2224/0401
ELECTRICITY
H01L2224/83193
ELECTRICITY
H01L2224/83203
ELECTRICITY
B32B37/0076
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/14145
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2224/75251
ELECTRICITY
H01L2224/291
ELECTRICITY
H01L2224/29187
ELECTRICITY
H01L2224/73204
ELECTRICITY
H01L2223/54493
ELECTRICITY
H01L2924/01322
ELECTRICITY
H01L2224/831
ELECTRICITY
H01L2224/81143
ELECTRICITY
Y10T428/24942
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L2224/94
ELECTRICITY
H01L2224/16146
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2224/73104
ELECTRICITY
H01L2224/2919
ELECTRICITY
H01L2924/00
ELECTRICITY
H01L24/94
ELECTRICITY
H01L2224/04026
ELECTRICITY
B32B37/18
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/92125
ELECTRICITY
H01L2924/00
ELECTRICITY
H01L23/49827
ELECTRICITY
Y10T156/10
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10T428/24826
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L2221/6834
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L24/75
ELECTRICITY
H01L2224/81191
ELECTRICITY
H01L25/50
ELECTRICITY
H01L2225/06568
ELECTRICITY
H01L23/10
ELECTRICITY
H01L2221/68318
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2224/8385
ELECTRICITY
B32B7/05
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/94
ELECTRICITY
H01L2224/291
ELECTRICITY
H01L24/73
ELECTRICITY
H01L23/544
ELECTRICITY
International classification
H01L21/00
ELECTRICITY
B32B37/18
PERFORMING OPERATIONS; TRANSPORTING
H01L25/00
ELECTRICITY
B32B37/00
PERFORMING OPERATIONS; TRANSPORTING
Abstract
A method for bonding a first substrate to a second substrate including the steps of: making contact of a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, as a result of which a common contact area is formed; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area. The invention also relates to a corresponding device and a substrate composite of a first substrate and a second substrate, in which a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, forms a common contact area, outside the common contact area there being a bond interconnection between the first substrate and the second substrate.
Claims
1. A method for bonding of a first substrate defined as a carrier wafer to a second substrate defined as a product wafer, said method comprising: directly contacting a first contact area of the first substrate with a second contact area of the second substrate to form a common contact area, said second contact area being aligned parallel to the first contact area, and producing a bond interconnection between the first substrate and the second substrate outside the common contact area, wherein the first substrate has a diameter D2 that is less than a diameter D3 of the second substrate.
2. The method as claimed in claim 1, wherein: the bond interconnection on the first substrate is at least partially formed on a first fixing area of the first substrate, which area is angled relative to the common contact area, and the bond interconnection on the second substrate is at least partially formed on a second fixing area of the second substrate, which area is angled relative to the common contact area.
3. The method as claimed in claim 2, wherein the first fixing areas and/or the second fixing areas are arranged rotationally symmetrical to one axis of rotation of the first substrate and/or the second substrate.
4. The method as claimed in claim 2, wherein a first area ratio between the first fixing area and the first contact area is less than 1:5 and/or a second area ratio between the second fixing area and the second contact area is less than 1:5.
5. The method as claimed in claim 2, wherein the bond interconnection is applied to the circumference of the carrier wafer.
6. The method as claimed in claim 5, wherein the bond interconnection is applied to only some portions of the circumference of the carrier wafer.
7. The method as claimed in claim 1, wherein adhesive and/or metallic interconnection elements are used to form the bond interconnection.
8. The method as claimed in claim 7, wherein the bond interconnection is produced at areas of the first and second substrate outside an outer circumference of the first substrate.
9. The method as claimed in claim 8, wherein the common contact area is within the outer circumference of the first substrate.
10. The method as claimed in claim 8, wherein a first interconnection element for the bond interconnection is formed on the outer circumference of the first substrate.
11. A method for bonding of a first substrate defined as a carrier wafer to a second substrate defined as a product wafer, said method comprising: providing an intermediate layer on a top surface of said second substrate to level bumps on the top surface, the intermediate layer being provided on the top surface as a component of said second substrate; directly contacting a first contact area of the first substrate with a second contact area of the intermediate layer of the second substrate to form a common contact area, said second contact area being aligned parallel to the first contact area; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area, wherein the first substrate has a diameter D2 that is less than a diameter D3 of the second substrate.
12. The method as claimed in claim 11, wherein the bond interconnection is produced at areas of the first and second substrate outside an outer circumference of the first substrate.
13. The method as claimed in claim 12, wherein the common contact area is within the outer circumference of the first substrate.
14. The method as claimed in claim 12, wherein a first interconnection element for the bond interconnection is formed on the outer circumference of the first substrate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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(23) In the figures advantages and features of the invention are labeled with the reference numbers which identify them according to embodiments of the invention, components or features with the same function or function with the same effect being labeled with identical reference numbers.
DETAILED DESCRIPTION OF THE INVENTION
(24) For the generic method the first substrate 1 will be a carrier wafer of any material, but preferably of silicon. A second substrate 7 (product wafer), which is to make contact with the first substrate 1, and the carrier wafer is preferably comprised of the same material. Due to identical or at least similar materials mechanical and thermal parameters between the product wafer and carrier wafer are the same or at least similar.
(25) The second substrate 7 on its top 7o has bumps 15 which are used for electrical interconnection of chips. For leveling and pressure equalization, on the top 7o there is an intermediate layer 18 as a component of the second substrate 7 on which contact is made with the first substrate 1. Thus the first substrate 1 has a first contact area 1k and the second substrate 7 has a second contact area 18k. To the extent there are no bumps 15, the second substrate 7 can be brought directly into contact with the first substrate 1 without an intermediate layer 18, then the top 7o becoming the second contact area.
(26) The substrates 1, 7 can either be completely radially symmetrical or can have a notch 2, a flat 3 or any other deviation from the radial symmetry (
(27) For the bond method the carrier wafer (first substrate 1) is worked, especially by grinding and/or etching processes, with an especially commercially conventional diameter D1 (
(28) In the ideal case at the transition of the outer contour 1a to the first contact area 1k a corner edge (with a radius of curvature which is much smaller relative to the opposing one or prior to the reduction of the diameter, especially in a ratio less than 1:5) is provided so that a lower segment of the first substrate 1 has a cylindrical outer contour (aside from possible features according to
(29) One important, especially original aspect of the invention relates to a metal alloy which with on the one hand an interconnection and optionally a sealing of the common contact area between the carrier wafer and product wafer are caused. This can take place by several embodiments of the invention according to the following description.
(30) In a first embodiment (
(31) Preferably the second substrate 7 is also provided with a metallization 11 on the top 7o (or on the side of the intermediate layer 18 pointing toward the first substrate 1) in a ring segment 7r which is located outside a common contact area 22 which is formed between the first and second contact area 1k, 18k when making contact.
(32) The metallizations 11 of the first substrate 1 and the metallizations 11 of the second substrate 7 can be comprised of different materials. Preferably metals are used whose alloys form a eutectic. More preferably at least one of the two metallizations should be comprised of a metal with a melting point as low as possible. The melting point should be less than 500 C., preferably less than 400 C., more preferably less than 300 C., most preferably less than 200 C., most preferably of all less than 100 C. Furthermore the two metallizations 11 and 11 can be comprised of the same metal. This metal should preferably have a melting point as low as possible. Since due to the geometry of the embodiment pressurization of the metallizing regions 11 and 11 is not possible or is only possible to a highly limited degree, production of the metallization 11 takes place predominantly by thermal stress. Generally it is therefore preferably a welding or soldering process.
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(34) The bond interconnection exists toward the first substrate 1 on the outer contour 1a on one fixing area 1f which is roughly orthogonally angled relative to the common contact area 22. Thus the bond interconnection is located outside the common contact area 22. Preferably the fixing surface 1f extends only over one part of the outer contour 1a.
(35) Toward the second substrate 7 the bond interconnection is on the one hand provided on the ring segment 7r and on the other on a second fixing area 18f which is formed by a free space 30 of the intermediate layer 18, which free space is formed especially by the metallization 11. The metallization 11 can be produced especially easily by lithographic processes. The second fixing surface 18f includes a peripheral wall which borders the free space 30. The ring segment 7r borders the free space 30 toward the second substrate 7 and thus forms a part of the second fixing area.
(36) In a second embodiment which, aside from the following details, is made analogously to the first embodiment according to
(37) In a third embodiment (
(38) In a fourth embodiment (
(39) In a fifth embodiment (
(40) Together with the metallization 11 (like
(41) In a sixth embodiment (
(42) Because the diameter D2 of the first substrate is less than/equal to the diameter D3 of the second substrate 7, the carrier wafer (first substrate 1) in subsequent processes, especially sputtering processes and plasma processes, is protected by the ring segment 29. A complex and expensive cleaning of the first substrate, especially caused by metallic contamination, is omitted. The first substrate can thus be re-used immediately for other/further steps.
(43) Advantageously a nonadhesive or only slightly adhesive detachable sealing layer and/or separating layer is applied to the entire area of the first substrate 1 which comes into contact with the product wafer 7. The first substrate 1, 1, 1, 1.sup.IV, 1.sup.V which is provided with this sealing layer has no adhering, permanently cementing contact with the second substrate 7, except for the area of the solder points or adhesive points.
(44) According to this new method of fixing the product wafer 7 to the carrier wafer 1 only at exactly defined points and of separating this fixing again after completion of the processes, any material which ensures fixing which is suitable for the process or processes can be used. In place of metallic solder also chemical or biological materials can be used which entirely or partially lose their fixing properties by adding other materials or energy.
(45) The type of solder metal depends on the temperatures and requirements which are necessary in the other processes and is defined specifically to the process. Since the solder metals depending on the composition have a defined melting point, there is a wide possibility of temperature adaptation. The melting point is higher than the temperature contribution of the production processes which is to be expected at most.
(46) But solder metals can also be used which are also used for the production of bumps on the product wafer. Since during unsoldering heat is supplied only at the sites which are intended for fixing, the bumps of the product wafer are not melted.
(47) It is also possible, instead of the metallization 11, to apply any other material which enables fixing of the wafers. This material can have an adhesive and/or sealing action. The material can be applied radially symmetrically by an apparatus which is known in the semiconductor industry.
(48) In all embodiments the temperature for melting of the interconnection material for bonding and/or debonding can be added in any conceivable manner. In particular introduction over the entire area, preferably by the contact of the carrier wafer and/or of the product wafer with a heating plate, would be conceivable. In one special and preferred embodiment the heat is added by a heating element 32 only at those positions in which the corresponding metallizations or fixings are present. The local heating has the decisive advantage that not the entire wafer is thermally loaded and thus possible structures which are already present on the product wafer are not thermally loaded or are at least loaded very little.
(49) In the apparatus which is used for bonding, at the sites which have these cavities 10, after making contact, temperature is added to melt the solder metal so that soldering takes place at these points. Debonding takes place in the same way, by heating and subsequent mechanical separation of the wafers by the introduction of movement by means of actuating units of a device.
(50) Should one of the metallizations 11, 11, 11 be melted again, preferably melting heat is added only in the immediate vicinity of the metallizations 11, 11, 11.
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(52) In a first embodiment preferably a very narrow heating element 32 is used which makes contact with the top 1o of the first substrate 1. Preferably the heating element 32 is surrounded by two cooling elements 33 which reduce the propagation of the heat over the entire first substrate 1. More preferably opposite (or on the side of the first substrate 1, 1 which faces away therefrom) the region of application of the metallizations 11, 11,11 in the first substrate 1, there is a depression 31 into which a heating element 32, in this case a heating element 32 with a wedge-shaped outline, can be inserted in order to optimize heat transport to the metallization 1.
(53) In another embodiment, a metallization 34 is deposited in the depression 31 for heating, especially in conjunction with the heating element 32. Due to the metallization 34 a high current is routed which produces Joulean heat which in turn heats up the vicinity of the metallization and thus leads to melting of the metallization 34 which is located in the vicinity (function of the heating element 32).
(54) In another embodiment, a metallization 34, especially in conjunction with the heating element 32, is deposited flush on the top 10 of the first substrate 1, 1, therefore without recessing in the first substrate 1, 1.
(55) The three presented methods can also be used to add heat for soldering (producing the interconnection).
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(57) The sample holders 35 and 36 are preferably vacuum sample holders. But they can also be electrostatic or other sample holders which can fix the two wafers.
(58) In another embodiment of the device, instead of a corresponding heating element 32, a dispensing unit 37 can be used. The dispensing unit can be used for lateral metallization, for deposition of adhesives, for application of sealing chemicals or for application of any material. As a result of the possible relative displacements and/or rotations of the sample holders 35, 36 to one another and/or the relative movement of the dispensing unit 37 relative of the sample holders 35, 36, a purely annular application or a blanket application of any material is possible. For example, prior to a bond process or soldering process on the outermost edge of the function wafer 7 or of the carrier wafer 1 a 500 m to 2000 m wide circular layer is applied in order to produce sealing in the edge region, especially for subsequent chemical processes. When using suitable flatness layers this application of an additional sealing layer in the edge region can be omitted. The backfilled flatness layer 18 between the bumps of the function layer must be removed in a cleaning step. Since to differentiate from other methods with adhesive layers this support layer has no adhesive properties or only the slightest such properties, cleaning is simpler and more economical than in adhesive methods.
REFERENCE NUMBER LIST
(59) 1, 1, 1, 1 first substrate (carrier substrate) 1.sup.IV, 1.sup.V 1a first outer contour 1f first fixing area 1k first contact area 1o top 2 notch 3 flat 6 holes 6i inner periphery 7 second substrate (product substrate) 7a second outer contour 7r ring segment 7o top 10 cavities 11, 11, 11 metallizations 18 intermediate layer 18f second fixing area 18k second contact area 20 depressions 21 sealing elements 22 common contact area 28 material superposition 29 ring segment 30 free space 31 depression 32 heating element 33 cooling elements 34, 34 metal deposition 35 lower sample holder 36 upper sample holder 37 dispensing unit D1, D2, D3, D4 diameter R axis of rotation