TOP GATE METAL OXIDE THIN FILM TRANSISTOR SWITCHING DEVICE FOR IMAGING APPLICATIONS

20170170218 ยท 2017-06-15

    Inventors

    Cpc classification

    International classification

    Abstract

    A method of manufacturing an image sensor device includes providing a substrate; forming a buffer layer on the substrate; forming a metal oxide channel on the buffer layer; forming a gate oxide layer on the buffer layer and the metal oxide channel; forming a gate metal layer on the gate oxide layer; forming a photodiode stack on the gate metal layer; patterning the gate oxide layer and the gate metal layer to form a first portion under the photodiode stack, and a second portion comprising a transistor; forming an interlayer dielectric layer over at least the photodiode stack and the transistor; forming a plurality of vias in the interlayer dielectric layer; and metalizing the vias to form contacts to the image sensor device.

    Claims

    1. A method of manufacturing an image sensor device comprising: providing a substrate; forming a buffer layer on the substrate; forming a metal oxide channel on the buffer layer; forming a gate oxide layer on the buffer layer and the metal oxide channel; forming a gate metal layer on the gate oxide layer; forming a photodiode stack on the gate metal layer; patterning the gate oxide layer and the gate metal layer to form a first portion under the photodiode stack, and a second portion comprising a transistor; forming an interlayer dielectric layer over at least the photodiode stack and the transistor; forming a plurality of vias in the interlayer dielectric layer; and metalizing the vias to form contacts to the image sensor device.

    2. The method of claim 1, wherein providing the substrate comprises providing a glass substrate.

    3. The method of claim 1, wherein forming the buffer layer comprises forming a silicon dioxide, silicon nitride, silicon oxynitride, or alumina dielectric film.

    4. The method of claim 1, wherein forming the metal oxide channel comprises forming a patterned Indium oxide layer.

    5. The method of claim 1, wherein forming the gate oxide layer comprises forming a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    6. The method of claim 1, wherein forming the gate metal layer comprises forming an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium layer.

    7. The method of claim 1, wherein forming the photodiode stack comprises forming a Silicon or organic photodiode.

    8. The method of claim 1, wherein forming the photodiode stack comprises forming a transparent metal top contact.

    9. The method of claim 1, wherein forming the interlayer dielectric layer comprises forming a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    10. The method of claim 1, wherein metalizing the vias comprises metalizing the vias with an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium layer.

    11. An image sensor device comprising: a substrate; a buffer layer on the substrate; a metal oxide channel on the buffer layer; a gate oxide layer on the buffer layer and the metal oxide channel; a gate metal layer on the gate oxide layer; a photodiode stack on the gate metal layer; the gate oxide layer and the gate metal layer forming a first portion under the photodiode stack, and a second portion comprising a transistor; an interlayer dielectric layer over at least the photodiode stack and the transistor; and a plurality of metalized vias in the interlayer dielectric layer comprising contacts to the image sensor device.

    12. The image sensor device of claim 11, wherein the substrate comprises a glass substrate.

    13. The image sensor device of claim 11, wherein the buffer layer comprises a silicon dioxide, silicon nitride, silicon oxynitride, or alumina dielectric film.

    14. The image sensor device of claim 11, wherein the metal oxide channel comprises a patterned Indium oxide layer.

    15. The image sensor device of claim 11, wherein the gate oxide layer comprises a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    16. The image sensor device of claim 11, wherein the gate metal layer comprises an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium layer.

    17. The image sensor device of claim 11, wherein the photodiode stack comprises a Silicon, or Organic photodiode.

    18. The image sensor device of claim 11, wherein the photodiode stack comprises a transparent metal top contact.

    19. The image sensor device of claim 11, wherein the interlayer dielectric layer comprises a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    20. The image sensor device of claim 11, wherein the metalized vias comprise an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium metal layer.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0012] FIGS. 1-6 illustrate, in cross-sectional views, a manufacturing method for an image sensor device according to the present invention including a photodiode and a transistor; and

    [0013] FIG. 7 is a pixel circuit that corresponds to the image sensor device shown in FIGS. 1-6.

    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

    [0014] A manufacturing process for an image sensor device performed is illustrated with respect to FIGS. 1-6.

    [0015] Referring to FIG. 1, a buffer dielectric film 104 is deposited on a substrate 102 using PECVD. A metal oxide channel film 106 is deposited by a PVD system and patterned using a photolithography process. Substrate 102 can comprise a glass, plastic, metal foil, or silicon substrate. The buffer layer 104 can comprise a silicon dioxide, silicon nitride, silicon oxynitride, or alumina dielectric film. The metal oxide channel 106 can comprise a patterned Indium oxide (whose composition varies, but major composition components are Indium, Zinc, Gallium, Hafnium, Aluminum, or Indium-Zinc-Gallium-Oxide (IGZO)) layer.

    [0016] Referring to FIG. 2, a gate oxide layer 108, a gate metal layer 110, a photodiode stack film including photodiode layer 112 and top contact layer 114 are deposited using PECVD and PVD. The photodiode layers 112 and 114 are patterned using an etch process. The gate oxide layer 108 can comprise a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer. The gate metal layer 110 can comprise an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium layer. The photodiode 112 of the photodiode stack can comprise a Silicon, or organic photodiode. The top contact 114 of the photodiode stack can comprise a transparent metal such as Indium-Zinc-Oxide (IZO) or Indium-Tin-Oxide (ITO) top contact.

    [0017] Referring to FIG. 3, the gate metal layer 110 and gate oxide layer 108 are patterned and etched to form a photodiode portion 108A and 110A, and a transistor portion 108B and 110B. Either a wet or a dry etch process, or both, can be used. Additional treatments are applied to achieve ohmic contact areas. The semiconductor channel 106 is protected by the gate metal area 110B.

    [0018] Referring to FIG. 4, an interlayer dielectric film 116 is deposited and vias 118A, 118B, and 118C are patterned and etched. The interlayer dielectric layer 116 can comprise a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    [0019] Referring to FIG. 5, a top metal layer 120 is deposited and patterned to form power and bias lines 120A and 120C, and data line 120B. Metalizing the vias 118A, 118B, and 118C comprises metalizing the vias with an Aluminum, Titanium, Molybdenum, Tungsten, or Chromium metal layer.

    [0020] Referring to FIG: 6, a passivation dielectric layer 122 is deposited and vias are opened at the periphery of the sensor array to make contacts between the pixel devices and the peripheral circuitry of the sensor array. The passivation layer 122 can comprise a silicon dioxide, silicon nitride, silicon oxynitride, or alumina layer.

    [0021] Referring to FIG. 7, a passive pixel circuit is shown corresponding to the device shown in FIG. 6. A transistor 122 is coupled between nodes 120C, 110B, and 120B. A photodiode 124 is coupled between nodes 120B and 120A.

    [0022] Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.