InGaAIN-based semiconductor device

Abstract

Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600 C., and a polycrystalline or amorphous In.sub.xGa.sub.yAl.sub.zN layer was obtained. When composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 10.sup.2 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAlN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.

Claims

1. A field effect transistor, comprising: a foundation layer; a nitride semiconductor layer as an n-type channel, the nitride semiconductor layer consisting of a nitride semiconductor having a formula of In.sub.xGa.sub.yAl.sub.zN where x, y, and z satisfy x+y+z=1.0, 0.3x0.99, and 0z<0.4, wherein the nitride semiconductor is polycrystalline or amorphous; an insulating layer provided on a surface of the nitride semiconductor layer; and a gate electrode provided on and directly bonded to a principal surface of the insulating layer and facing the nitride semiconductor layer such that the insulating layer is interposed between the gate electrode and the nitride semiconductor layer, wherein the nitride semiconductor layer is provided on and in direct contact with the foundation layer and has a thickness of from 1 nm to 10 nm, wherein the foundation layer is an insulating substrate, or an insulating amorphous layer provided directly between a substrate and the nitride semiconductor layer, and wherein the field effect transistor is a depletion type field effect transistor.

2. The field effect transistor according to claim 1, wherein x and z satisfy 0z<0.2 and 0.33x<0.7, or 0z<0.1 and 0.7x0.99.

3. The field effect transistor according to claim 2, wherein x and z satisfy 0.5x0.99 and 0z<0.1.

4. The field effect transistor according to claim 1, wherein x satisfies 0.3x0.67.

5. The field effect transistor according to claim 1, wherein the foundation layer is an insulating amorphous layer comprising HfO.sub.2, Al.sub.2O.sub.3, or SiO.sub.2.

6. The field effect transistor according to claim 1, wherein the substrate is a non-single crystalline substrate.

7. The field effect transistor according to claim 1, wherein the foundation layer is an insulating substrate.

8. The field effect transistor according to claim 7, wherein the insulating substrate is a synthetic quartz substrate.

9. The field effect transistor according to claim 1, wherein an ON/OFF ratio of the field effect transistor is 10.sup.2 or higher.

10. The field effect transistor according to claim 1, wherein the nitride semiconductor layer has a thickness of from 1 nm to 5 nm.

11. The field effect transistor according to claim 5, wherein the insulating amorphous layer has a thickness of from 1 nm to 20 nm.

12. The field effect transistor according to claim 1, wherein the nitride semiconductor in the nitride semiconductor layer is polycrystalline.

13. The field effect transistor according to claim 1, wherein the nitride semiconductor in the nitride semiconductor layer is amorphous.

14. A field effect transistor, comprising: a substrate; a first insulating layer; a nitride semiconductor layer; a second insulating layer; a source electrode; a drain electrode; and a gate electrode, wherein the first insulating layer, the nitride semiconductor layer, and the second insulating layer are sequentially provided on a principal surface of the substrate, wherein the nitride semiconductor layer consists of a nitride semiconductor having a formula of In.sub.xGa.sub.yAl.sub.zN where x, y, and z satisfy x+y+z=1.0, 0.3<x<0.99, and 0z<0.4, wherein the nitride semiconductor is polycrystalline or amorphous, wherein the source electrode and the drain electrode are bonded to the nitride semiconductor layer and the second insulating layer, wherein the gate electrode is provided on and directly bonded to a principal surface of the second insulating layer and facing the nitride semiconductor layer such that the second insulating layer is interposed between the gate electrode and the nitride semiconductor layer, wherein the field effect transistor is an InGaAlN-based or InGaN-based semiconductor device and includes the nitride semiconductor layer as an n-type channel, and wherein the field effect transistor is a depletion type field effect transistor.

15. A field effect transistor, comprising: a substrate; a nitride semiconductor layer; an insulating layer; a source electrode; a drain electrode; and a gate electrode, wherein the nitride semiconductor layer and the insulating layer are sequentially provided on a principal surface of the substrate, wherein the nitride semiconductor layer consists of a nitride semiconductor having a formula of In.sub.xGa.sub.yAl.sub.zN where x, y, and z satisfy x+y+z=1.0, 0.3x<0.99, and 0z<0.4, wherein the nitride semiconductor is polycrystalline or amorphous, wherein the source electrode and the drain electrode are bonded to the nitride semiconductor layer and the insulating layer, wherein the gate electrode is provided on and directly bonded to a principal surface of the insulating layer and facing the nitride semiconductor layer such that the insulating layer is interposed between the gate electrode and the nitride semiconductor layer, wherein the field effect transistor is an InGaAlN-based or InGaN-based semiconductor device and includes the nitride semiconductor layer as an n-type channel, and wherein the field effect transistor is a depletion type field effect transistor.

16. A field effect transistor having a bottom gate structure, comprising: a substrate; an insulating layer; a nitride semiconductor layer; a source electrode; a drain electrode; and a gate electrode, wherein the insulating layer is provided between the nitride semiconductor layer and the substrate, wherein the nitride semiconductor layer consists of a nitride semiconductor having a formula of In.sub.xGa.sub.yAl.sub.zN where x, y, and z satisfy x+y+z=1.0, 0.3<x<0.99, and 0z<0.4, wherein the nitride semiconductor is polycrystalline or amorphous, wherein the source electrode and the drain electrode electrically contact the nitride semiconductor layer, wherein the gate electrode is provided between the substrate and the insulating layer, wherein the field effect transistor is an InGaAlN-based or InGaN-based semiconductor device and includes the nitride semiconductor layer as an n-type channel, and wherein the field effect transistor is a depletion type field effect transistor.

17. The field effect transistor according to claim 1, wherein the nitride semiconductor layer consists of a single layer consisting of a single material of the nitride semiconductor having the formula of In.sub.xGa.sub.yAl.sub.zN.

18. The field effect transistor according to claim 14, wherein the nitride semiconductor layer consists of a single layer consisting of a single material of the nitride semiconductor having the formula of In.sub.xGa.sub.yAl.sub.zN.

19. The field effect transistor according to claim 15, wherein the nitride semiconductor layer consists of a single layer consisting of a single material of the nitride semiconductor having the formula of In.sub.xGa.sub.yAl.sub.zN.

20. The field effect transistor according to claim 16, wherein the nitride semiconductor layer consists of a single layer consisting of a single material of the nitride semiconductor having the formula of In.sub.xGa.sub.yAl.sub.zN.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram for explaining a configuration of a transistor (semiconductor device) according to a first embodiment.

(2) FIG. 2 is a diagram illustrating dependency on a film thickness of InN of a ratio between an ON current and an OFF current of a field effect transistor using an InN layer as a channel.

(3) FIG. 3 is a diagram illustrating I.sub.DS-V.sub.DS characteristics of a transistor in the case where the nitride semiconductor layer is a polycrystalline InN layer.

(4) FIG. 4 is a diagram illustrating I.sub.DS-V.sub.GS characteristics of the transistor in the case where the nitride semiconductor layer is a polycrystalline InN layer.

(5) FIG. 5 is a diagram illustrating I.sub.DS-V.sub.DS characteristics of the transistor in the case where the nitride semiconductor layer is an amorphous InN layer.

(6) FIG. 6 is a diagram for explaining one aspect of a configuration of a transistor (semiconductor device) according to a second embodiment.

(7) FIG. 7 is a diagram for explaining one aspect of the configuration of the transistor (semiconductor device) according to the second embodiment.

(8) FIGS. 8(A) and 8(B) are graphs illustrating I.sub.DS-V.sub.DS characteristics and I.sub.DS-V.sub.GS characteristics of the transistor in the case where the nitride semiconductor layer is a single crystalline InN layer having a film thickness of 2 nm, and FIGS. 8(C) and 8(D) are graphs illustrating I.sub.DS-V.sub.DS characteristics and I.sub.DS-V.sub.GS characteristics of the transistor in the case where the nitride semiconductor layer is a single crystalline InN layer having a film thickness of 5 nm.

(9) FIG. 9 is a diagram in which composition of a nitride semiconductor layer of an experimentally manufactured transistor is plotted in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(10) FIG. 10 is a diagram in which composition of a nitride semiconductor layer of a transistor exhibiting an ON/OFF ratio of 10.sup.2 or higher is plotted with .circle-solid. and composition of other nitride semiconductor layers is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(11) FIG. 11 is a diagram in which composition of a nitride semiconductor layer of a transistor exhibiting an on/off ratio of 10.sup.3 or higher is plotted with .circle-solid. and composition of other nitride semiconductor layers is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(12) FIG. 12 is a diagram in which composition of a nitride semiconductor layer having transistor characteristics exhibiting maximum current density exceeding 5 mA/mm is plotted with .circle-solid., and composition of other nitride semiconductor layers is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(13) FIG. 13 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.64, y=0 and z=0.36.

(14) FIG. 14 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.34, y=0.33 and z=0.33.

(15) FIG. 15 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.42, y=0.42 and z=0.16.

(16) FIG. 16 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.3, y=0.7 and z=0.

(17) FIG. 17 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.67, y=0.33 and z=0.

(18) FIG. 18 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer as a channel, the nitride semiconductor layer being expressed as In.sub.xGa.sub.yAl.sub.zN where x=0.5, y=0.5 and z=0.

(19) FIG. 19 is a diagram illustrating a configuration example of a transistor having a laminate structure (heterojunction structure) in which an AlN layer and a second nitride semiconductor layer are bonded on the nitride semiconductor layer of In.sub.xGa.sub.yAl.sub.zN.

(20) FIG. 20 is a diagram illustrating a configuration example of a transistor having a bottom gate structure.

DESCRIPTION OF EMBODIMENTS

(21) Preferred embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. It should be noted that, in the description of the drawings, the same reference numerals will be assigned to the same components, if possible, and overlapped explanation will be omitted.

First Embodiment: InN Layer

(22) FIG. 1 illustrates a configuration of a transistor 1a (semiconductor device) according to a first embodiment. The transistor 1a includes a substrate 2a, a first insulating layer 3a, a nitride semiconductor layer 4a, a second insulating layer 5a, a source electrode 61, a drain electrode 62 and a gate electrode 63.

(23) The first insulating layer 3a, the nitride semiconductor layer 4a and the second insulating layer 5a are sequentially provided on a principal surface S1a of the substrate 2a. The first insulating layer 3a is bonded to the substrate 2a. The nitride semiconductor layer 4a is bonded to the first insulating layer 3a. The second insulating layer 5a is bonded to the nitride semiconductor layer 4a.

(24) In the example illustrated in FIG. 1, the substrate 2a has insulation properties. The substrate 2a is a fused silica substrate. It should be noted that while the substrate 2a does not have to be an insulating substrate, and may be a substrate having conductive properties, when the nitride semiconductor layer 4a is directly formed on the substrate 2a, it is preferable to provide an insulating film on a surface of the substrate 2a.

(25) While the substrate 2a may be a single crystalline substrate, because, typically, the single crystalline substrate is expensive, the substrate 2a may be a non-single crystalline substrate which is less expensive. As will be described later, in the present invention, because the InGaAlN-based nitride semiconductor layer which is the nitride semiconductor layer 4a is a polycrystalline or amorphous film having a film thickness falling within a specific range, a single crystalline substrate does not have to be necessarily used. It should be noted that the substrate 2a does not have to be a so-called crystalline substrate, and only has to be a substrate which allows film formation through a method which will be described later, and may be a plastic substrate, or the like.

(26) The first insulating layer 3a functions as a foundation layer of the nitride semiconductor layer 4a, and, for example, is a layer having a thickness between 1 nm and 20 nm. Examples of the first insulating layer 3a can include an amorphous HfO.sub.2 layer, an Al.sub.2O.sub.3 layer, a SiO.sub.2 layer, or the like. Because the InGaAlN-based nitride semiconductor exhibits characteristics such as high wettability with respect to the surfaces of these insulating layers, by providing the above-described insulating layer, nucleus generation density is increased, so that it becomes possible to form a flat and high-quality polycrystalline or amorphous InGaAlN-based nitride semiconductor layer. It should be noted that when wettability of the InGaAlN-based nitride semiconductor with respect to the surface of the substrate 2a is sufficiently high, even if the InGaAlN-based nitride semiconductor layer is directly formed on a surface of such a substrate, it is possible to obtain a flat and high-quality InGaAlN-based nitride semiconductor layer.

(27) In the present embodiment, the nitride semiconductor layer 4a is an InN layer provided on the substrate 2a, and this InN layer is a polycrystalline or amorphous film having a film thickness between 1 nm and 10 nm. It should be noted that, in the aspect illustrated in FIG. 1, a planar shape of the nitride semiconductor layer 4a is, for example, a rectangle of approximately, 50 m5 m to 50 m10 m.

(28) While amorphous means, in a more limited sense, a material state which does not have long-range order as in a crystal, but has short-range order, in the present specification, amorphous also includes cryptocrystalline which does not have a complete crystal structure, but exhibits weak diffraction in X-ray analysis. Further, the amorphous film includes even an amorphous film which microscopically includes a microcrystal.

(29) The nitride semiconductor layer 4a which is a group III-V compound semiconductor may have either group V polarity (N polarity) or group III polarity. The nitride semiconductor layer 4a can contain impurities (for example, Zn) as a dopant. Further, even a layer containing light element such as oxygen as impurities is the nitride semiconductor layer 4a.

(30) A film thickness of the nitride semiconductor layer 4a is between 1 nm and 10 nm. As described above, it is conventionally considered that if the film thickness of the InN is made thinner, electric characteristics such as mobility becomes poorer, there is no idea of trying to manufacture a transistor using an extremely thin film of several nanometers as a channel layer. However, the present inventors have studied characteristics of the InN layer in the case where the thickness of the InN layer is made extremely thin, and have reached a conclusion that when the thickness of the InN layer falls within the above-described thickness range, even a polycrystalline or amorphous film can exhibit electric characteristics equal to a single crystalline film, and can realize favorable transistor operation, and thus, have made the present invention.

(31) FIG. 2 is a diagram illustrating dependency of a film thickness dependency of InN of a ratio between an ON current and an OFF current of a field effect transistor which uses the InN layer as a channel, the film thickness dependency being obtained through experiments by the present inventors. FIG. 2 indicates a film thickness [nm] on a horizontal axis and indicates the ON current/OFF current ratio on a vertical axis.

(32) A measurement result indicated with P1 in FIG. 2 is a result in the case where the nitride semiconductor layer 4a is polycrystalline InN, a measurement result indicated with P2 in FIG. 2 is a result in the case where the nitride semiconductor layer 4a is amorphous InN, and a measurement result indicated with P3 in FIG. 2 is a result in the case where the nitride semiconductor layer 4a is single crystalline InN.

(33) Referring to FIG. 2, it can be understood that a favorable ON current/OFF current ratio of the nitride semiconductor layer 4a between approximately 10 and 10.sup.8 can be realized in the range where the film thickness of the InN layer which is the nitride semiconductor layer 4a is between 1 nm and 10 nm. Further, when the film thickness of the nitride semiconductor layer 4a is thinner within the range between 1 nm and 10 nm, the ON current/OFF current ratio becomes more favorable. The above-described tendency does not depend on whether the InN layer which is the nitride semiconductor layer 4a is a single crystal, a polycrystal or amorphous. That is, by designing the film thickness of the InN layer which is the nitride semiconductor layer 4a in the range between 1 nm and 10 nm, even when the InN layer is a polycrystal or amorphous, it is possible to obtain electric characteristics equal to those of a single crystal.

(34) It should be noted that such an InN layer is favorably a film deposited through a sputtering method because it is easy to form a film at a relatively low temperature. More preferably, the InN layer is a film deposited through a pulsed sputtering deposition method (PSD method) which has high flexibility in setting of film forming conditions. Further, because when a film is formed at a higher temperature, a size of individual grains becomes larger, which makes it difficult to obtain a flat film, it is preferable to form a film at a temperature less than 600 C.

(35) While, in order to form a film of a single crystalline InN layer, it is necessary to make a diffusion length of an atom on a film formation surface sufficiently long, which inevitably requires to form a film at a relatively high temperature, in the present invention, because the InN layer does not have to be a single crystal if the film thickness falls within a range between 1 nm and 10 nm, it is possible to obtain an advantage that there is no obstacle even when a film formation temperature is set low.

(36) In addition, typically, a light element such as oxygen is likely to be incorporated into a film as impurities under the influence of remaining gas within a chamber when a film is formed through the sputtering method, and, if the InN layer is a single crystal, there is a problem that such oxygen impurities act as a donor. However, if the InN layer is a polycrystal or amorphous, because oxygen impurities are incorporated into the InN layer in a state where the oxygen impurities are electrically inactive by, for example, being trapped in a grain boundary, it is possible to obtain an advantage that the oxygen impurities are less likely to act as a donor as described above.

(37) As with the first insulating layer 3a, examples of the second insulating layer 5a can include an amorphous HfO.sub.2 layer, an Al.sub.2O.sub.3 layer, a SiO.sub.2 layer, or the like. As described above, because InN has high wettability with respect to the surfaces of these insulating layers, InN has an effect of suppressing occurrence of a defect at an interface with the InN layer. It should be noted that the second insulating layer 5a is, for example, a layer having a thickness between approximately 1 nm and 100 nm.

(38) In the example illustrated in FIG. 1, thicknesses of the source electrode 61, the drain electrode 62 and the gate electrode 63 are all approximately 50 nm, and materials of the source electrode 61, the drain electrode 62 and the gate electrode 63 are all, for example, Au. Both the source electrode 61 and the drain electrode 62 are bonded to the nitride semiconductor layer 4a and the second insulating layer 5a. The gate electrode 63 is provided on a surface of the second insulating layer 5a and bonded to the second insulating layer 5a.

(39) A manufacturing method of the transistor 1a will be described next. A wafer corresponding to the substrate 2a is prepared. On a surface of this wafer, the first insulating layer 3a, the nitride semiconductor layer 4a and the second insulating layer 5a are laminated in this order. It should be noted that layers corresponding to the first insulating layer 3a and the second insulating layer 5a may both be layers made of an oxide semiconductor.

(40) If the first insulating layer 3a and the second insulating layer 5a are oxide semiconductors, these layers are both formed through, for example, an atomic layer deposition method (ALD method). An oxygen material when a film is formed through the ALD method is H.sub.2O, a deposition temperature is approximately 200 C., and a deposition period is approximately one and a half hours.

(41) The InN layer corresponding to the nitride semiconductor layer 4a is formed through the pulsed sputtering deposition method (PSD method). A deposition rate of the InN layer is approximately 1 nm/min, and the thickness is set within a range between 1 nm and 10 nm. When the deposition temperature of the InN layer depends on the sputtering method, the temperature is room temperature in the case of an amorphous film, and approximately between 300 C. and 500 C. in the case of a polycrystal. That is, the temperature is lower than a typical crystal growth temperature (600 C. or higher) in the case where a film of a single crystalline InN layer is formed.

(42) While a film of the InN layer corresponding to the nitride semiconductor layer 4a may be formed through the sputtering method other than the PSD method, and may be formed through other evaporation methods or a thin film formation methods such as an MBE method and an MOCVD method, the sputtering method is favorable because it is easy to form a film whose composition is uniform at a relatively low temperature. It should be noted that, as described above, because a size of individual grains become larger when a film of a polycrystalline nitride semiconductor layer 4a is formed at a higher temperature, which makes it difficult to obtain a flat film, it is preferable to form a film at a temperature of less than 600 C.

(43) Contact holes respectively corresponding to the source electrode 61 and the drain electrode 62 are formed on the second insulating layer 5a using lithography technique. Both the source electrode 61 and the drain electrode 62 are formed through lithography after, for example, Au is vacuum evaporated. The gate electrode 63 is formed by patterning Au vacuum evaporated on a surface of the second insulating layer 5a through a lift-off method.

(44) In this manner, the first insulating layer 3a, the nitride semiconductor layer 4a and the second insulating layer 5a are laminated on a surface of the wafer corresponding to the substrate 2a in this order, and separated into chips corresponding to the transistor 1a after the source electrode 61, the drain electrode 62 and the gate electrode 63 are formed. The transistor 1a is manufactured through the above-described manufacturing method.

(45) Transistor characteristics of the transistor 1a which uses the above-described InN layer as a channel will be described next with reference to FIGS. 3 to 5.

(46) FIG. 3 illustrates I.sub.DS-V.sub.DS characteristics of the transistor 1a in the case where the nitride semiconductor layer 4a is a polycrystalline InN layer. Here, I.sub.Ds indicates a current flowing between a drain and a source, V.sub.DS is a voltage between the drain and the source. FIG. 3 indicates V.sub.DS [V] on a horizontal axis and indicates I.sub.DS [A] on a vertical axis.

(47) The result illustrated in FIG. 3 is I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS which is a voltage between the gate and the source is changed in a step of 0.5 [V] within a range between 5 [V] and 8[V]. The ON current/OFF current ratio is approximately 10.sup.5. FIG. 3 illustrates an aspect where I.sub.DS approaches zero as V.sub.GS decreases. Therefore, referring to FIG. 3, it can be understood that it is sufficiently possible to switch the ON current/OFF current ratio of the transistor 1a by controlling V.sub.GS in the case of the polycrystalline InN.

(48) FIG. 4 illustrates I.sub.DS-V.sub.GS characteristics of the transistor 1a in the case where the nitride semiconductor layer 4a is the polycrystalline InN layer. FIG. 4 indicates V.sub.GS [V] on a horizontal axis and indicates I.sub.DS [A] on a vertical axis.

(49) According to the result illustrated in FIG. 4, it can be understood that as V.sub.GS decreases within a range between 4 [V] and 8 [V], I.sub.DS also decreases, and a ratio between a value of I.sub.DS when V.sub.GS is 4 [V] and a value of I.sub.DS when V.sub.GS is 8 [V] is approximately 10.sup.5. Therefore, referring to FIG. 4, it can be understood that it is sufficiently possible to control I.sub.DS of the transistor 1a by controlling V.sub.GS in the case of the polycrystalline InN.

(50) FIG. 5 illustrates I.sub.DS-V.sub.DS characteristics of the transistor 1a in the case where the nitride semiconductor layer 4a is an amorphous InN layer. FIG. 5 indicates V.sub.DS [V] on a horizontal axis and indicates I.sub.DS [A] on a vertical axis.

(51) The result illustrated in FIG. 5 indicates I.sub.DS-V.sub.DS characteristics when V.sub.GS is changed in a step of 2 [V] within a range between 10 [V] and 0 [V]. FIG. 5 illustrates that as V.sub.GS decreases, I.sub.DS also approaches zero. Therefore, referring to FIG. 5, it can be understood that it is sufficiently possible to switch the ON current/OFF current ratio of the transistor 1a by controlling V.sub.GS in the case of the amorphous InN.

Second Embodiment: InN Layer

(52) FIGS. 6 and 7 are diagrams for explaining one aspect of a configuration of a transistor 1b (semiconductor device) according to a second embodiment. It should be noted that, also in the present embodiment, a nitride semiconductor layer 4b is an InN layer provided on a substrate 2b.

(53) FIG. 6(A) is an optical microscope image illustrating a planar shape of the transistor 1b, and FIG. 6(B) is a diagram mainly illustrating a configuration of a cross-section of the transistor 1b along line I-I illustrated in FIG. 6(A).

(54) FIG. 7(A) is a TEM (Transmission Electron Microscope) lattice image illustrating a laminate structure of the transistor 1b, FIG. 7(B) illustrates an electron diffraction pattern (Fourier transformed image of the TEM image) from a region indicated with InN in FIG. 7(A), and FIG. 7(C) is an electron diffraction pattern (Fourier transformed image of the TEM image) from a region indicated with YSZ in FIG. 7(A). It can be confirmed from FIGS. 7(A) to 7(C) that a single crystalline InN as the nitride semiconductor layer is epitaxially grown on a single crystalline YSZ substrate.

(55) The transistor 1b includes the substrate 2b, a nitride semiconductor layer 4b, an insulating layer 5b, a source electrode 61, a drain electrode 62 and a gate electrode 63. The nitride semiconductor layer 4b and the insulating layer 5b are sequentially provided on a principal surface S1b of the substrate 2b.

(56) In the present embodiment, the substrate 2b is an yttria-stabilized zirconia substrate (YSZ substrate). The YSZ substrate has relatively small in-plane lattice mismatch with not only InN but also nitride semiconductors such as InGaN, InAlN and InAlGaN which includes InN as a main component. The principal surface S1b of the substrate 2b is bonded to the nitride semiconductor layer 4b and has plane indices (111). The principal surface S1b is made flat at the atomic level.

(57) The InN layer as the nitride semiconductor layer 4b is provided on the substrate 2b. The nitride semiconductor layer 4b is bonded to the substrate 2b. The nitride semiconductor layer 4b is a single crystal. The nitride semiconductor layer 4b is an epitaxial layer formed through epitaxial growth from the principal surface S1b of the substrate 2b. The nitride semiconductor layer 4b can have any of N-polarity and group III polarity. The nitride semiconductor layer 4b can contain impurity Zn (zinc). The planar shape of the nitride semiconductor layer 4b is, for example, a rectangle of approximately 50 m5 m to 50 m10 m.

(58) The film thickness of the InN layer which is the nitride semiconductor layer 4b falls between 1 nm and 10 nm. As already described with reference to FIG. 2, in the range where the film thickness of the InN layer which is the nitride semiconductor layer falls between 1 nm and 10 nm, the ON current/OFF current ratio of the nitride semiconductor layer is between approximately 10 and 10.sup.8, so that it is possible to realize a favorable ON current/OFF current ratio. Further, as the film thickness of the nitride semiconductor layer is thinner within a range between 1 nm and 10 nm, the ON current/OFF current ratio becomes more favorable. In addition, the above-described tendency does not depend on whether the InN layer which is the nitride semiconductor layer is a single crystal, a polycrystal or amorphous.

(59) Therefore, in the present embodiment, while the InN layer which is the nitride semiconductor layer 4b is a single crystalline InN which is epitaxially grown on the single crystalline YSZ substrate, even when the InN layer is a polycrystalline or amorphous InN layer deposited on a fused silica substrate, or the like, it is possible to obtain electric characteristics equal to those of a single crystal by designing the film thickness in a range between 1 nm and 10 nm.

(60) The insulating layer 5b is bonded to the nitride semiconductor layer 4b. Examples of the insulating layer 5b can include an amorphous HfO.sub.2 layer, an Al.sub.2O.sub.3 layer, a SiO.sub.2 layer, or the like. As already described, because the InN has high wettability with respect to the surfaces of these insulating layers, it is possible to provide an effect of suppressing occurrence of a defect at an interface with the InN layer. It should be noted that the film thickness of the insulating layer 5b is, for example, between 1 nm and 100 nm.

(61) In the example illustrated in FIG. 6, the thicknesses of the source electrode 61, the drain electrode 62 and the gate electrode 63 are all approximately 50 nm, and materials of the source electrode 61, the drain electrode 62 and the gate electrode 63 are all, for example, Au. Both the source electrode 61 and the drain electrode 62 are bonded to the nitride semiconductor layer 4b and the insulating layer 5b. The gate electrode 63 is provided on the surface of the insulating layer 5b and bonded to the insulating layer 5b.

(62) A manufacturing method of the transistor 1b will be described next. A wafer corresponding to the substrate 2b is prepared. While, in the present embodiment, this wafer is a YSZ substrate, if a polycrystalline or amorphous InN layer is formed, this wafer may be a non-single crystalline substrate or an insulating substrate (for example, a fused silica substrate). On the surface of this wafer, the nitride semiconductor layer 4b and the insulating layer 5b are laminated in this order.

(63) The InN layer corresponding to the nitride semiconductor layer 4b is formed through the pulsed sputtering deposition method (PSD method) as in the first embodiment. A deposition rate of the InN layer is approximately 1 nm/min, and the thickness is set in a range between 1 nm and 10 nm. Because, in the present embodiment, a single crystalline InN is formed, an epitaxial temperature is between 600 C. and 700 C. However, if an amorphous InN is deposited through the sputtering method, the deposition temperature is made an ambient temperature, while, if a polycrystalline InN is deposited, the deposition temperature is made between approximately 300 C. and 500 C. That is, the deposition temperature is lower than a typical crystal growth temperature (600 C. or higher) in the case where a film of a single crystalline InN layer is formed.

(64) While a film of the InN layer corresponding to the nitride semiconductor layer 4b may be formed through the sputtering method other than the PSD method, and may be formed through other evaporation methods or a thin film formation method such as an MBE method and an MOCVD method, the sputtering method is favorable because it is easy to form a film whose composition is uniform at a relatively low temperature. It should be noted that, as described above, a size of individual grains becomes larger as the film is formed at a higher temperature, which makes it difficult to obtain a flat film, a film of a polycrystalline nitride semiconductor layer 4a is preferably formed at a temperature of less than 600 C.

(65) When the insulating layer 5b is an oxide semiconductor, for example, a film is formed through an atomic layer deposition method (ALD method). An oxygen material when the film is formed through the ALD method is H.sub.2O, the deposition temperature is 200 C., and a deposition period is approximately one and a half hours.

(66) Contact holes respectively corresponding to the source electrode 61 and the drain electrode 62 are formed in the insulating layer 5b using lithography technique. Both the source electrode 61 and the drain electrode 62 are formed through lithography after, for example, Au is vacuum evaporated. The gate electrode 63 is formed by patterning Au which is vacuum evaporated on a surface of the insulating layer 5b using a lift-off method.

(67) In this manner, on the surface of the wafer corresponding to the substrate 2b, the nitride semiconductor layer 4b and the insulating layer 5b are laminated in this order, and separated into chips corresponding to the transistor 1b after the source electrode 61, the drain electrode 62 and the gate electrode 63 are formed. The transistor 1b is manufactured through the above-described manufacturing method.

(68) Transistor characteristics of the transistor 1b which uses the above-described InN layer as a channel will be described next with reference to FIG. 8.

(69) FIGS. 8(A) and 8(B) illustrate I.sub.DS-V.sub.DS characteristics (FIG. 8(A)) in the case where V.sub.GS of the transistor 1b in the case where the nitride semiconductor layer 4b is a single crystalline InN layer having a film thickness of 2 nm, is changed in a step of 1 [V] within a range between +2 [v] and 2 [V], and I.sub.DS-V.sub.GS characteristics (FIG. 8(B)) under V.sub.DS of 5 [V]. FIG. 8(A) indicates V.sub.DS [V] on a horizontal axis and indicates I.sub.DS [mA/mm] on a vertical axis. Further, FIG. 8(B) indicates V.sub.G [V] on a horizontal axis and indicates I.sub.DS [A] on a vertical axis.

(70) FIGS. 8(C) and 8(D) illustrate I.sub.DS-V.sub.DS characteristics (FIG. 8(C)) in the case where V.sub.GS of the transistor 1b in the case where the nitride semiconductor layer 4b is a single crystalline InN layer having a film thickness of 5 nm, is changed in a step of 2 [V] within a range between +4 [V] and 10 [V], and I.sub.DS-V.sub.GS characteristics (FIG. 8(D)) under V.sub.DS of 5 [V]. FIG. 8(C) indicates V.sub.DS [V] on a horizontal axis, and indicates I.sub.DS [mA/mm] on a vertical axis. FIG. 8(D) indicates V.sub.G [V] on a horizontal axis and indicates I.sub.DS [A] on a vertical axis.

(71) Referring to the results illustrated in FIGS. 8(A) to 8(D), it can be understood that it is sufficiently possible to switch the ON current/OFF current ratio of the transistor 1b by controlling V.sub.GS in the case of a single crystalline InN.

(72) Further, as described above, even when the InN layer is a polycrystal or amorphous, by designing the film thickness within a range between 1 nm and 10 nm, it is possible to obtain electric characteristics equal to those of a single crystal. Therefore, even when the nitride semiconductor layer 4b is a polycrystalline or amorphous InN layer, it is sufficiently possible to switch the ON current/OFF current ratio of the transistor 1b.

(73) While the principle of the present invention has been described in the preferred embodiments, a person skilled in the art would recognize that arrangement and details of the present invention can be modified without departing from such principle.

(74) For example, the semiconductor device according to the present invention can be made a semiconductor device having a configuration including a laminate structure in which the nitride semiconductor layer having composition different from that of InN is bonded on at least one principle surface of the above-described InN layer, that is, a semiconductor device having a heterojunction structure.

(75) The present invention is not limited to a specific configuration disclosed in the present embodiments. Therefore, all modifications and changes that result from the claims and the scope of its spirit are claimed. For example, the nitride semiconductor layers 4a and 4b of the present embodiments can be applied to semiconductor devices other than a transistor. In the case of the nitride semiconductor layer 4a, the first insulating layer 3a is also applied to such a semiconductor device along with the nitride semiconductor layer 4a.

Third Embodiment: InGaAlN Layer

(76) In the above-described first and second embodiments, the nitride semiconductor layer is made an InN layer expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) where x=1. Further, it is clarified that, in the case of the InN layer, by setting the thickness within a specific thickness range, it is possible to obtain a non-single crystalline film exhibiting channel characteristics equal to those of a single crystal.

(77) If desired electric characteristics can be obtained only within a specific thickness range (1 to 10 nm), there is a problem that flexibility of design of the semiconductor device cannot be secured. Therefore, the present inventors have further studied electric characteristics of an InGaAlN-based nitride semiconductor and found that even a non-single crystalline film exhibits channel characteristics equal to those of a single crystal if a composition range of the film falls within a specific composition range.

(78) It has been conventionally considered that it is difficult to change the composition of In in the InGaAlN-based nitride semiconductor in a broad range in thermodynamic terms, because an ion radius of In in the InGaAlN-based nitride semiconductor is larger than those of other elements. However, such conventional knowledge is one that is applied to an InGaAlN-based nitride semiconductor obtained through a CVD method in which a film is formed at a relatively high temperature. The present inventors have pursued study based on idea that the above-described knowledge is one that is merely applied to the InGaAlN-based nitride semiconductor formed under a thermal equilibrium state, and if the InGaAlN-based nitride semiconductor is deposited through a sputtering method in which a film can be formed at a relatively low temperature, the film may be quenched while a state is kept a thermally non-equilibrium state, and film formation may stably proceed, thereby achieving the present invention.

(79) In the following examples, a result of study as to how electric characteristics of the InGaAlN-based nitride semiconductor expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) depends on its composition will be described.

(80) A field effect transistor 1a having a configuration illustrated in FIG. 1 was experimentally manufactured, and electric characteristics were evaluated with ratios between ON currents and OFF currents (ON/OFF ratios) and maximum current density of the transistor 1a while composition (In.sub.xGa.sub.yAl.sub.zN) of the nitride semiconductor layer 4a which becomes a channel is variously changed. The substrate 2a is a fused silica substrate, the first insulating layer 3a is HfO.sub.2 having a thickness of 20 nm, the second insulating layer 5a is HfO.sub.2 which is also used as a gate insulating film and has a thickness of 20 nm. It should be noted that the substrate 2a may be a non-single crystalline substrate or an insulating substrate other than the fused silica substrate, and the first insulating layer 3a and the second insulating layer 5a may be an Al.sub.2O.sub.3 layer or a SiO.sub.2 layer. Further, all transistors 1a have a gate length of 5 m and a channel width of 50 m.

(81) All In.sub.xGa.sub.yAl.sub.zN layers are formed through the sputtering method (in the present embodiment, the PSD method). The deposition rate is approximately 1 nm/min. Further, the deposition temperature is made less than 600 C., and the In.sub.xGa.sub.yAl.sub.zN layers are made polycrystalline or amorphous In.sub.xGa.sub.yAl.sub.zN layers.

(82) FIG. 9 is a diagram in which composition of the nitride semiconductor layer 4a of the transistor 1a which is experimentally manufactured is plotted in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(83) FIG. 10 is a diagram in which composition of the nitride semiconductor layer 4a of the transistor exhibiting an ON/OFF ratio of 10.sup.2 or higher is plotted with .circle-solid. and composition of other nitride semiconductor layer 4a is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN among the composition illustrated in FIG. 9.

(84) According to this result, when the composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting the ON/OFF ratio of 10.sup.2 or higher can be obtained.

(85) Further, FIG. 11 is a diagram in which composition of the nitride semiconductor layer of a transistor exhibiting the ON/OFF ratio of 10.sup.3 or higher is plotted with .circle-solid. and composition of other nitride semiconductor layers is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(86) According to this result, when composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting the ON/OFF ratio of 10.sup.2 or higher can be obtained.

(87) Further, FIG. 12 is a diagram in which composition of a nitride semiconductor layer having transistor characteristics exhibiting maximum current density exceeding 5 mA/mm is plotted with .circle-solid. and composition of other nitride semiconductor layers is plotted with in a ternary phase diagram of In.sub.xGa.sub.yAl.sub.zN.

(88) According to this result, when composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.5x1.0 and 0z<0.1, transistor characteristics exhibiting the maximum current density exceeding 5 mA/mm can be obtained.

(89) As described above, when composition of the nitride semiconductor layer expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, even when the film is a non-single crystalline film, it is possible to provide sufficient channel characteristics (having the ON/OFF ratio of 10.sup.2 or higher) as transistor operation, and, when the composition falls within a range of 0z0.2 when 0.3x<0.7 and 0z<0.1 when 0.7x1.0, the ON/OFF ratio becomes further higher by an order of magnitude (10.sup.3 or higher). Further, when the composition of the nitride semiconductor layer falls within a range of 0.5x1.0 and 0z<0.1, a transistor having excellent transistor characteristics of maximum current density exceeding 5 mA/mm can be obtained.

(90) It should be noted that, as described in the first embodiment, when InN which is a nitride semiconductor having composition of x=1.0 when the nitride semiconductor is expressed with a general expression In.sub.xGa.sub.yAl.sub.zN is used as a channel layer, it is impossible to obtain sufficient transistor characteristics if the film thickness exceeds 10 nm.

(91) Therefore, in order to secure flexibility of design of the semiconductor device, it is preferable to remove InN from the above-described composition range, that is, the In composition ratio x of the nitride semiconductor layer is preferably 0.99 or less (x0.99).

(92) It is known that a film of an InGaAlN-based nitride semiconductor containing 1% or higher of Al or Ga, that is, a nitride semiconductor in which x0.99 when the nitride semiconductor is expressed with a general expression In.sub.xGa.sub.yAl.sub.zN, becomes structurally strong, and a defect is less likely to occur (see, for example, Non Patent Literature 4). This is considered because of a phenomenon that an InGaAlN-based nitride semiconductor containing 1% or higher of Al or Ga is thermodynamically likely to be phase separated, which makes it likely to make concentration of Al or Ga locally non-uniform, resulting in suppressing propagation of dislocation.

(93) FIG. 13 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.zN where x=0.64, y=0 and z=0.36 as a channel, and FIG. 13(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 1 [V] within a range between +5 [V] and 7 [V]. Further, FIG. 13(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 1 [V].

(94) This transistor is obtained by depositing 5 nm of a channel layer having composition of In.sub.0.64Al.sub.0.36N on a fused silica substrate through a sputtering method at an ambient temperature. It should be noted that a gate insulating film is HfO.sub.2, a gate length is 5 m, and a channel width is 50 m.

(95) The above-described composition falls within a range of 0.3x1.0 and 0z<0.4, the ON/OFF ratio is 710.sup.2, and maximum current density is 0.4 mA/mm.

(96) FIG. 14 illustrates electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.zN where x=0.34, y=0.33 and z=0.33 as a channel, and FIG. 14(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 1 [V] within a range between +5 [V] and 7 [V]. Further, FIG. 14(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 1 [V].

(97) This transistor is obtained by depositing 5 nm of a channel layer having composition of In.sub.0.34Ga.sub.0.33Al.sub.0.33N on a fused silica substrate at a substrate temperature of 400 C. through the sputtering method. It should be noted that a gate insulating film is HfO.sub.2, a gate length is 5 m, and a channel width is 50 m.

(98) The above-described composition also falls within a range of 0.3z1.0 and 0z<0.4, and has the ON/OFF ratio of 110.sup.3 and maximum current density of 3.410.sup.4 mA/mm.

(99) FIG. 15 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.z N where x=0.42, y=0.42 and z=0.16 as a channel, and FIG. 15(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 2 [V] within a range between +2 [V] and 6 [V]. Further, FIG. 15(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 1 [V].

(100) This transistor is obtained by depositing 5 nm of a channel layer having composition of In.sub.0.42Ga.sub.0.42Al.sub.0.16N on a fused silica substrate at a substrate temperature of 400 C. through the sputtering method. It should be noted that a gate insulating film is HfO.sub.2, a gate length is 5 m, and a channel width is 50 m.

(101) The above-described composition falls within a range of 0.3x<0.7 and 0z<0.2, and has the ON/OFF ratio of 110.sup.3 and the maximum current density of 110.sup.3 mA/mm.

(102) FIG. 16 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.zN where x=0.3, y=0.7 and z=0 as a channel, and FIG. 16(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 0.5 [V] within a range between +5 [V] and 9 [V]. Further, FIG. 16(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 1 [V].

(103) This transistor is obtained by depositing 30 nm of a channel layer having composition of In.sub.0.3Ga.sub.0.7N on a fused silica substrate at a substrate temperature of 400 C. through the sputtering method. It should be noted that a gate insulating film is HfO.sub.2, a gate length is 5 m, and a channel width is 50 m.

(104) The above-described composition also falls within a range of 0.3x<0.7 and 0z<0.2, and has the ON/OFF ratio of 110.sup.6 and maximum current density of 0.5 mA/mm.

(105) FIG. 17 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.zN where x=0.67, y=0.33 and z=0 as a channel, and FIG. 17(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 1 [V] within a range between +4 [V] and 9 [V]. Further, FIG. 17(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 1 [V].

(106) This transistor is obtained by depositing 6 nm of a channel layer having composition of In.sub.0.67Ga.sub.0.33N on a fused silica substrate at a substrate temperature of 400 C. through the sputtering method. It should be noted that a gate insulating film is HfO.sub.2, a gate length is 5 m and a channel width is 50 m.

(107) The above-described composition falls within a range of 0.5x1.0 and 0z<0.1, and has an ON/OFF ratio of 110.sup.4 and maximum current density of 7.5 mA/mm.

(108) FIG. 18 is a diagram illustrating electric characteristics of a transistor including a nitride semiconductor layer expressed with In.sub.xGa.sub.yAl.sub.zN where x=0.5, y=0.5 and z=0, and FIG. 18(A) illustrates I.sub.DS-V.sub.DS characteristics in the case where V.sub.GS is changed in a step of 1 [V] within a range between 0 [V] and 9 [V]. Further, FIG. 18(B) illustrates I.sub.DS-V.sub.GS characteristics under V.sub.DS of 5 [V].

(109) This transistor is obtained by depositing 45 nm of a channel layer having composition of In.sub.0.5Ga.sub.0.5N on a fused silica substrate at a substrate temperature of 400 C. through the sputtering method. It should be noted that this transistor has a ring gate structure, in which a gate insulating film is HfO.sub.2, a gate ring diameter is 100 m, and a channel length is 10 m.

(110) The above-described composition also falls within a range of 0.5x1.0 and 0z<0.1, and has an ON/OFF ratio of 110.sup.8 and maximum current density of 25 mA/mm.

(111) The transistor characteristics illustrated in FIGS. 13 to 18 are characteristics of part of a number of transistors experimentally manufactured by the present inventors. As a result of performing characteristics analysis on a number of transistors, the above-described conclusion has been reached as to composition of the nitride semiconductor.

(112) That is, when the composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 10.sup.2 or higher can be obtained.

(113) Further, when the composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 10.sup.2 or higher can be obtained.

(114) Still further, when the composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.5x1.0 and 0z<0.1, transistor characteristics having maximum current density exceeding 5 mA/mm can be obtained.

(115) While the semiconductor device according to the present invention including a nitride semiconductor layer expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) as a channel has been described above, it goes without saying that the transistor configuration can be variously changed. Some examples of the transistor configuration will be described below.

(116) FIG. 19 is a diagram illustrating a configuration example of a transistor 1c having a laminate structure (heterojunction structure) in which an AlN layer and a second nitride semiconductor layer 6c are bonded on the above-described nitride semiconductor layer 4c of In.sub.xGa.sub.yAl.sub.zN.

(117) In the example illustrated in FIG. 19, a substrate 2c is a synthetic quartz substrate. The nitride semiconductor layer 4c is, for example, a polycrystalline or amorphous film having a film thickness of 3 nm. An amorphous HfO.sub.2 layer having a film thickness of 15 nm is provided on the second nitride semiconductor layer 6c as an insulating layer 5c. By placing the AlN layer between the nitride semiconductor layer 4c and the HfO.sub.2 layer as the insulating layer 5c, as the second nitride semiconductor layer 6c, a favorable interface is obtained.

(118) FIG. 20 is a diagram illustrating a configuration example of a transistor 1d having a bottom gate structure.

(119) Also in the example illustrated in FIG. 20, a substrate 2d is a synthetic quartz substrate. A nitride semiconductor layer 4d is, for example, a polycrystalline or amorphous film having a film thickness of 3 nm. An amorphous HfO.sub.2 layer having a film thickness between 100 nm and 150 nm is provided between the nitride semiconductor layer 4d and the substrate 2d as an insulating layer 5d, and a gate 63 is formed with an ITO film having a thickness of approximately 90 nm.

(120) As described above, the semiconductor device according to the present invention may have a laminate structure (heterojunction structure) in which the second nitride semiconductor layer having a different composition from that of the nitride semiconductor layer is bonded on at least one principle surface of the above-described nitride semiconductor layer.

(121) At this time, the second nitride semiconductor layer may be a nitride semiconductor layer expressed with the above-described general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0). For example, a transistor may be configured such that the nitride semiconductor layer is In.sub.x1Ga.sub.y1Al.sub.z1N, and the second nitride semiconductor layer is In.sub.x2Ga.sub.y2Al.sub.z2N (where x2x1), and may be configured to have a double heterostructure in which the nitride semiconductor layer of In.sub.x1Ga.sub.y1Al.sub.z1N is vertically put between the second nitride semiconductor layer of In.sub.x2Ga.sub.y2Al.sub.z2N.

INDUSTRIAL APPLICABILITY

(122) According to the present invention, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAlN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics.

REFERENCE SIGNS LIST

(123) 1a, 1b, 1c, 1d transistor 2a, 2b, 2c, 2s substrate 3a first insulating layer 4a, 4b, 4c, 4d nitride semiconductor layer 5a second insulating layer 5b, 5c, 5d insulating layer 6c second nitride semiconductor layer 61 source electrode 62 drain electrode 63 gate electrode S1a, S1b principle surface