SYNAPTIC TRANSISTOR

Abstract

Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.

Claims

1. A synaptic transistor, comprising: a substrate; an expansion gate electrode disposed to extend in one direction on the substrate; a gate insulating layer comprising ions, covering the expansion gate electrode, and disposed on the substrate; a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode; source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer; and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.

2. The synaptic transistor of claim 1, wherein the ions move from the side of the pad electrode to the side of the channel layer, when a positive bias is applied to the pad electrode.

3. The synaptic transistor of claim 1, wherein the ions move from the side of the channel layer to the side of the pad electrode, when a negative bias is applied to the pad electrode.

4. The synaptic transistor of claim 1, wherein the gate insulating layer is formed with a seating groove in which the pad electrode is seated to correspond to the other end of the expansion gate electrode.

5. The synaptic transistor of claim 1, wherein the hysteresis and synaptic characteristics are controlled according to the area of the channel layer and the thickness of the gate insulating layer disposed below the pad electrode.

6. The synaptic transistor of claim 1, wherein the gate insulating layer is made of Al.sub.2O.sub.3 laminated by atomic layer deposition.

7. A synaptic transistor, comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer comprising hydrogen ions, covering the gate electrode, and disposed on the substrate; a retention layer made of an insulating material having a greater hydrogen bonding force than the gate insulating layer and disposed on the gate insulating layer; a channel layer disposed on the retention layer to correspond to the gate electrode; and source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the retention layer.

8. The synaptic transistor of claim 7, wherein the gate insulating layer is made of Al.sub.2O.sub.3 laminated by atomic layer deposition.

9. The synaptic transistor of claim 7, wherein the hydrogen ions move from the side of the gate electrode to the side of the channel layer, when a positive bias is applied to the gate electrode.

10. The synaptic transistor of claim 7, wherein the hydrogen ions move from the side of the channel layer to the side of the gate electrode, when a negative bias is applied to the gate electrode.

11. The synaptic transistor of claim 7, wherein the hydrogen ions move at a slower rate in the retention layer than in the gate insulating layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 is a plan view of a synaptic transistor according to a first exemplary embodiment of the present invention.

[0032] FIG. 2 is a cross-sectional view taken along Section Line II-II of FIG. 1.

[0033] FIG. 3 is a cross-sectional view taken along Section Line III-III of FIG. 1.

[0034] FIG. 4 is a diagram for describing the operation principle of a synaptic transistor according to the first exemplary embodiment of the present invention.

[0035] FIG. 5 is a graph showing the drain-source current with respect to the gate voltage according to the thickness of a gate insulating layer disposed below a pad electrode.

[0036] FIG. 6 is a graph showing the threshold voltage difference with respect to the area of the channel layer according to the thickness of a gate insulating layer disposed below a pad electrode.

[0037] FIG. 7 is a graph showing the amount of current change with respect to the number of pulses according to the thickness of a gate insulating layer disposed below a pad electrode.

[0038] FIG. 8 is a graph showing the amount of current change with respect to the number of pulses according to the area of a channel layer.

[0039] FIGS. 9A to 9D are diagrams for describing the manufacturing method of a synaptic transistor according to the first exemplary embodiment of the present invention with reference to FIG. 2.

[0040] FIGS. 10A to 10E are diagrams for describing the manufacturing method of a synaptic transistor according to the first exemplary embodiment of the present invention with reference to FIG. 3.

[0041] FIG. 11 is a plan view of the synaptic transistor according to a second exemplary embodiment of the present invention.

[0042] FIG. 12 is a cross-sectional view taken along Section Line II-II of FIG. 11.

[0043] FIG. 13 is a cross-sectional view taken along Section Line III-III of FIG. 11.

[0044] FIG. 14A and FIG. 14B is a diagram for describing the operation principle of the short-term memory characteristics of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0045] FIG. 15 is a diagram for describing the operation principle of writing of the long-term memory characteristics of a synaptic transistor according to the second exemplary embodiment.

[0046] FIG. 16 is a diagram for describing the operation principle of erasing of the long-term memory characteristics of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0047] FIGS. 17A to 17F are diagrams for describing the manufacturing method of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0048] FIG. 18 is a plan view of the synaptic transistor according to a third exemplary embodiment of the present invention.

[0049] FIG. 19 is a cross-sectional view taken along Section Line II-II of FIG. 18.

[0050] FIG. 20 is a cross-sectional view taken along Section Line III-III of FIG. 18.

[0051] FIG. 21 is a diagram for describing the operation principle of a synaptic transistor according to the third exemplary embodiment of the present invention.

[0052] FIG. 22 is a graph showing the threshold voltages of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention.

[0053] FIG. 23 is a graph showing the sub-threshold swings (SS) of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention.

[0054] FIG. 24 is a graph illustrating the mobilities of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention.

[0055] FIG. 25 is a graph illustrating the amount of change in current with respect to the number of pulses of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention.

[0056] FIG. 26 is a graph illustrating the amount of change in current with respect to the time of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the invention.

[0057] FIGS. 27A to 27E are diagrams for describing the manufacturing method of a synaptic transistor according to the third exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0058] FIG. 1 is a plan view of a synaptic transistor according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along Section Line II-II of FIG. 1, and FIG. 3 is a cross-sectional view taken along Section Line III-III of FIG. 1.

[0059] Referring to FIGS. 1 to 3, the synaptic transistor according to a first exemplary embodiment of the present invention may be configured by including a substrate 100, an expansion gate electrode 110, a gate insulating layer 120, a channel layer 130, source and drain electrodes 141 and 142 and a pad electrode 143.

[0060] The expansion gate electrode 110 is disposed to extend in one direction on the substrate 100, and the gate insulating layer 120 covers the expansion gate electrode 110 and is disposed on the substrate 100.

[0061] The channel layer 130 is disposed on the gate insulating layer 120 to correspond to one end of the expansion gate electrode 110, and the source electrode 141 and the drain electrode 142 are spaced apart from each other, cover both ends of the channel layer 130 and are disposed on the gate insulating layer 120. Herein, the channel layer 130 may be made of indium gallium zinc oxide (IGZO), which is an amorphous structure, and the gate electrode 110, the source and drain electrodes 141, 142 and the pad electrode 143 may be made of Cu, which is a conductive material, but are not limited thereto.

[0062] The pad electrode 143 is disposed on the gate insulating layer 120 to correspond to the other end of the expansion gate electrode 110.

[0063] Herein, the gate insulating layer 120 may be formed with a seating groove 121 in which the pad electrode 120 is seated to correspond to the other end of the expansion gate electrode 110, and the pad electrode 143 may be seated in the seating grooves 121 formed in the gate insulation layer 120.

[0064] The gate insulating layer 120 includes ions, and these ions may be hydrogen ions.

[0065] To this end, the gate insulating layer 120 may be made of Al.sub.2O.sub.3 laminated by atomic layer deposition (ALD). In this case, the gate insulating layer 120 forms a weak ionic bond of AlOH by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated by gate bias into AlO.sup. and H.sup.+ such that a large number of hydrogen ions are included in the gate insulating layer 120.

[0066] The hydrogen ions included in the gate insulating layer 120 move inside the gate insulation layer 120 in accordance with the gate bias applied to the pad electrode 143, and by adjusting the number of the hydrogen ions moved to the side of the channel layer 130, it induces a gating effect and at the same time induces hysteresis.

[0067] FIG. 4 is a diagram for describing the operation principle of a synaptic transistor according to the first exemplary embodiment of the present invention.

[0068] As illustrated in FIG. 4(a), when a positive bias is applied to the pad electrode 143, hydrogen ions (H.sup.+) move from the side of the pad electrode 143 to the side of the channel layer 130. That is, when a positive bias is applied to the pad electrode 143, the hydrogen ions (H.sup.+) inside the gate insulating layer 120 located below the pad electrode 143 move downward by the repulsive force thereof, and the hydrogen ions (H.sup.+) inside the gate insulating layer 130 located below the channel layer 130 relatively move upward due to the moved hydrogen ions (H.sup.+).

[0069] As such, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 130 increases, the threshold voltage decreases and the electrical conductivity increases.

[0070] In contrast, as illustrated in FIG. 4(b), when a negative bias is applied to the pad electrode 143, hydrogen ions (H.sup.+) move from the side of the channel layer 130 to the side of the pad electrode 143. That is, when a negative bias is applied to the pad electrode 143, the hydrogen ions (H.sup.+) inside the gate insulating layer 120 located below the pad electrodes 143 move upward by the attraction force thereof, and the hydrogen ions (H.sup.+) inside the gate insulating layer 130 located below the channel layer 130 relatively move downward due to the moved hydrogen ions (H.sup.+).

[0071] As such, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 130 decreases, the threshold voltage increases and the electrical conductivity decreases.

[0072] The synaptic transistor according to the first exemplary embodiment of the present invention is characterized in that hysteresis and the synaptic characteristics are adjusted according to the area of the channel layer 130 and the thickness of the gate insulating layer 120 disposed below the pad electrode 143.

[0073] Specifically, in the synaptic transistor according to the first exemplary embodiment of the present invention, as the area of the channel layer 130 increases and the thickness of the gate insulating layer 120 disposed below the pad electrode 143 increases, more hydrogen ions are included inside the gate insulation layer 120, and the distance over which the hydrogen ions can move is increased, resulting in greater hysteresis.

[0074] This greater hysteresis makes it possible to have a relatively high signal-to-noise ratio by providing immunity to a change in the threshold voltage V.sub.T occurring in the manufacturing process of synaptic transistors.

[0075] The hysteresis (V.sub.hysteresis) of the synaptic transistor according to the first exemplary embodiment of the present invention may be defined by Mathematical Formula 1 below.

[00001]$\begin{array}{cc}{V}_{\mathrm{hysteresis}}=\frac{Q_{\mathrm{ox}1}{A}_1{T}_{\mathrm{ox}1}^2+Q_{\mathrm{ox}2}{A}_2{T}_{\mathrm{ox}2}^2}{{}_{\mathrm{ox}}}& <\mathrm{Mathematical}\mathrm{Formula}1>\end{array}$

[0076] Herein, Q.sub.ox1 is the total amount of ions included in the gate insulating layer 120 disposed below the pad electrode 143, Q.sub.ox2 is the entire amount of ions included in the gate insulating layer 120 located below the channel layer 130, and .sub.ox is the dielectric constant of the gate insulation layer 120.

[0077] According to Mathematical Formula 1 above, it can be confirmed that the hysteresis (V.sub.hysteresis) of the synaptic transistor is determined by the area A.sub.1 of the pad electrode 143, the area A.sub.2 of the channel layer 130, the thickness T.sub.ox1 of the gate insulating layer 120 disposed below the pad electrode 143 and the thickness T.sub.ox2 of the gate insulating layer 120 located below the channel layer 130.

[0078] In particular, it can be confirmed that as the area A.sub.2 of the channel layer 130 increases and the thickness T.sub.ox1 of the gate insulating layer 120 disposed below the pad electrode 143 increases, the hysteresis (V.sub.hysteresis) of the synaptic transistor increases.

[0079] FIG. 5 is a graph showing the drain-source current with respect to the gate voltage according to the thickness of a gate insulating layer disposed below a pad electrode, and FIG. 6 is a graph showing the threshold voltage difference with respect to the area of the channel layer according to the thickness of a gate insulating layer disposed below a pad electrode.

[0080] Referring to FIG. 5, the width W.sub.2 and the length L.sub.2 of the channel layer 130 were formed to be 50 m, respectively, and the thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 disposed below the pad electrode 143 was formed to be 0, 10 and 25 nm, respectively. Then, the gate-source voltage V.sub.GS was applied in a range of 20 to 20 V in a state where the source-drain voltage V.sub.DS was applied at 2V for each thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120, and the drain-source current I.sub.DS was measured.

[0081] As a result of the measurement, it was experimentally confirmed that as the thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 increased, the hysteresis increased.

[0082] Referring to FIG. 6, differences in the forward threshold voltage V.sub.T.forward and the reverse threshold voltage V.sub.T.reverse were measured for each thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 while changing the area A.sub.2 of the channel layer 130 in a range of 1 to 2,500 m.sup.2 after forming the thickness T.sub.ox1 of the gate insulating layer 120 disposed below the pad electrode 143 to be 0, 10 and 25 nm, respectively.

[0083] As a result of the measurement, it was experimentally confirmed that as the area A.sub.2 of the channel layer 130 increased, the difference between the forward threshold voltage V.sub.T.forward and the reverse threshold voltage V.sub.T.reverse, that is, hysteresis, increased. In particular, it was confirmed that as the thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 increased, the hysteresis increase rate further increased.

[0084] In the synaptic transistor according to the first exemplary embodiment of the present invention, as the thickness of the gate insulating layer 120 disposed below the pad electrode 143 increases, the gating effect by hydrogen ions increases, and as the area of the channel layer 130 becomes smaller, the increase width of the drain current becomes larger, and thus, the synaptic characteristics may be improved.

[0085] FIG. 7 is a graph showing the amount of current change with respect to the number of pulses according to the thickness of a gate insulating layer disposed below the pad electrode, and FIG. 8 is a graph showing the amount of current change with respect to the number of pulses according to the area of a channel layer.

[0086] Referring to FIG. 7, the width W.sub.2 and the length L.sub.2 of the channel layer 130 were formed to be 50 m and 20 m, respectively, and the thicknesses T.sub.ox1 of the gate insulating layer (pad oxide) 120 disposed below the pad electrode 143 were formed to be 0, 10 and 25 nm, respectively. Then, pulses were applied in a range of 0 to 32 for each thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120, and the current change amount I was measured.

[0087] As a result of the measurement, it was experimentally confirmed that as the thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 increased, the current change amount I corresponding to the number of pulses increased.

[0088] Referring to FIG. 8, the thickness T.sub.ox1 of the gate insulating layer (pad oxide) 120 disposed below the pad electrode 143 was formed to be 10 nm, and the areas A.sub.2 of the channel layer 130 were formed to be 20, 50, 100, 200 and 500 m.sup.2. Then, pulses were applied in a range of 0 to 32 for each area A.sub.2 of the channel layer 130, and the current change amount I was measured.

[0089] As a result of the measurement, it was experimentally confirmed that the smaller the area A.sub.2 of the channel layer 130, the larger the current change amount I corresponding to the number of pulses.

[0090] As described above, in the synaptic transistor according to the first exemplary embodiment of the present invention, as the thickness of the gate insulating layer 120 disposed below the pad electrode 143 increases, the gating effect by hydrogen ions increases, and as the area of the channel layer 130 becomes smaller, the increase width of the drain current increases, and thus, the synaptic characteristics may be improved.

[0091] In addition, the synaptic transistor according to the first exemplary embodiment of the present invention may improve energy efficiency, which is an important indicator of neuromorphic computing, due to improved synaptic characteristics.

[0092] FIGS. 9A to 9D are diagrams for describing the manufacturing method of a synaptic transistor according to the first exemplary embodiment of the present invention with reference to FIG. 2, and FIGS. 10A to 10E are diagrams for describing the manufacturing method of a synaptic transistor according to the first exemplary embodiment of the present invention with reference to FIG. 3.

[0093] First, referring to FIGS. 9A and 10A, the expansion gate electrode 110 is formed to extend in one direction on the substrate 100. For example, Cu may be melted using the electron beam vacuum evaporation (e-beam evaporator) to form an expansion gate electrode 110 having a thickness of about 20 nm on the substrate 100.

[0094] Next, referring to FIGS. 9B and 10B, the gate insulating layer 120 is formed on the substrate 100 so as to cover the expansion gate electrode 110. In this case, the gate insulating layer 120 may include hydrogen ions.

[0095] For example, atomic layer epitaxy (ALD) may be used to deposit Al.sub.2O.sub.3 to a thickness of about 40 nm to form a gate insulating layer 120. In this case, the gate insulating layer 120 forms a weak ionic bond of AlOH by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated by gate bias into AlO.sup. and H.sup.+ such that a large number of hydrogen ions are included in the gate insulating layer 120.

[0096] Next, referring to FIG. 10C, a seating groove 121 is formed in the gate insulating layer 120 to correspond to the other end of the expansion gate electrode 110. For example, the gate insulating layer 120 may be etched to a depth of about 30 nm using the buffered oxide etch (BOE) etching process to form a seating groove 121.

[0097] Next, referring to FIGS. 9C and 10D, a channel layer 130 is formed on the gate insulating layer 120 to correspond to one end of the expansion gate electrode 110. For example, the channel layer 130 may be formed by depositing IGZO to a thickness of about 35 nm using the sputtering technique.

[0098] Next, referring to FIGS. 9D and 10E, a source electrode 141 and a drain electrode 142 are formed on the gate insulating layer 120 so as to cover both ends of the channel layer 130, and a pad electrode 143 is formed in the seating groove 121. For example, the source and drain electrodes 141 and 142 and the pad electrode 143 may be formed to a thickness of about 30 nm above the gate insulating layer 120 by melting Cu using the electron beam vacuum evaporation (e-beam evaporator).

[0099] FIG. 11 is a plan view of the synaptic transistor according to a second exemplary embodiment of the present invention, FIG. 12 is a cross-sectional view taken along Section Line II-II of FIG. 11, and FIG. 13 is a cross-sectional view taken along Section Line III-III of FIG. 11.

[0100] Referring to FIGS. 11 to 13, as a synaptic transistor with long-term and short-term memory characteristics, the synaptic transistor according to a second exemplary embodiment of the present invention may be configured by including a substrate 200, a bottom gate electrode 210, a first gate insulating layer 220, a floating gate electrode 230, a second gate insulation layer 240, a channel layer 250 and source and drain electrodes 261 and 262.

[0101] The bottom gate electrode 210 is disposed to extend in one direction on the substrate 200, and the first gate insulating layer 220 covers the bottom gate electrode 210 and is disposed on the substrate 200.

[0102] The floating gate electrode 230 is disposed on the first gate insulating layer 220 to correspond to the bottom gate electrode 210, and the second gate insulation layer 240 covers the floating gate electrode 230 and is disposed on the first gate insulating layer 220.

[0103] The channel layer 250 is disposed on the second gate insulating layer 240 to correspond to the floating gate electrode 230, and the source electrode 261 and the drain electrode 262 are spaced apart from each other, cover both ends of the channel layer 250 and are disposed on the second gate insulating layer 240. Herein, the channel layer 250 may be made of indium gallium zinc oxide (IGZO), which is an amorphous structure, and the bottom gate electrode 210, the floating gate electrode 230, the source electrode 261 and the drain electrode 262 may be made of Cu, which is a conductive material, but are not limited thereto.

[0104] The first gate insulating layer 220 and the second gate insulating layer 240 include ions, and these ions may be hydrogen ions.

[0105] To this end, the first and second gate insulating layers 220, 240 may be made of Al.sub.2O.sub.3 laminated by low-temperature atomic layer deposition (ALD). In this case, the first and second gate insulating layers 220, 240 form a weak ionic bond of AlOH by H.sub.2O used in the low-temperature atomic layer deposition process. This ionic bond is separated by gate bias into AlO.sup. and H.sup.+ such that a large number of hydrogen ions are included in the first and second gate insulating layers 220, 240.

[0106] The hydrogen ions included in the first and second gate insulating layers 220, 240 move inside the first gate insulating layer 220, 240 in accordance with the gate bias applied to the bottom gate electrode 210, and by adjusting the number of the hydrogen ions moved towards the channel layer 250, it induces a gating effect and at the same time induces hysteresis.

[0107] The first and second gate insulating layers 220, 240 are formed with contact holes CH that expose a portion of the bottom gate electrode 220 at positions spaced apart by a certain distance from the channel layer 250.

[0108] FIG. 14A and FIG. 14B is a diagram for describing the operation principle of the short-term memory characteristics of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0109] FIG. 14B (a) is an energy band diagram linked to FIG. 14A (a). And FIG. 14 B (b) is an energy band diagram linked to FIG. 14A (b).

[0110] As illustrated in FIG. 14A (a) and FIG. 14B (a), when a positive bias less than a reference voltage is applied to the bottom gate electrode 210 exposed by the contact hole CH, hydrogen ions H.sup.+ move from the side of the bottom gate electrode 210 to the side of the channel layer 250. That is, when a positive bias is applied to the bottom gate electrode 210, the hydrogen ions (H.sup.+) inside the first gate insulating layer 220 located above the bottoms gate electrode 210 move upward by the repulsive force thereof, and the hydrogen ions (H.sup.+) inside the second gate insulation layer 240 located above the floating gate electrode 230 move upward by the repulsive force thereof. Accordingly, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 250 increases, the threshold voltage decreases and the electrical conductivity increases.

[0111] Herein, the reference voltage means a voltage at which electrons included in the floating gate electrode 230 may move over the first gate insulating layer 220 to the bottom gate electrode 210.

[0112] On the other hand, as illustrated in FIG. 14A (b) and FIG. 14B (b), when a negative bias is applied to the bottom gate electrode 210 exposed by the contact hole CH, hydrogen ions (H.sup.+) move from the side of the channel layer 250 to the side of the bottom gate electrode 210. That is, when a negative bias is applied to the bottom gate electrode 210, the hydrogen ions (H.sup.+) inside the first gate insulating layer 220 located below the floating gate electrode 230 move downward by the attractive force thereof, and the hydrogen ions (H.sup.+) inside the second gate insulating layers 240 located below the channel layer 250 move downward by the attractive force thereof. Accordingly, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 250 decreases, the threshold voltage increases and the electrical conductivity decreases.

[0113] Herein, the reference voltage means a voltage at which electrons included in the bottom gate electrode 210 may move over the first gate insulating layer 220 to the floating gate electrode 230.

[0114] According to such an operation principle, the synaptic transistor according to the second exemplary embodiment of the present invention may perform the operation of short-term memory characteristics.

[0115] FIG. 15 is a diagram for describing the operation principle of writing of the long-term memory characteristics of a synaptic transistor according to the second exemplary embodiment, and FIG. 16 is a diagram for describing the operation principle of erasing of the long-term memory characteristics of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0116] The synaptic transistor according to the second exemplary embodiment of the present invention is made to exhibit long-term memory characteristics using the Fowler Nordheim (FN) tunneling mechanism.

[0117] Specifically, as illustrated in FIG. 15, when a positive bias greater than or equal to a reference voltage is applied to the bottom gate electrode 210, the electrons (e) included in the floating gate electrode 230 move over the first gate insulating layer 220 to the bottom gate electrode 210. Then, the moved electrons (e) are trapped by the bottom gate electrode 210 such that the threshold voltage of the channel layer 250 decreases and the electric conductivity increases.

[0118] Herein, the reference voltage means a voltage at which electrons included in the floating gate electrode 230 may move over the first gate insulating layer 220 to the bottom gate electrode 210.

[0119] According to such an operation principle, the synaptic transistor according to the second exemplary embodiment of the present invention may perform the operation of writing of long-term memory characteristics.

[0120] Unlike the above, as illustrated in FIG. 16, when a positive bias greater than or equal to a reference voltage is applied to the bottom gate electrode 210, the electrons (e) included in the bottom gate electrode 210 move over the first gate insulating layer (tunneling oxide) 220 to the floating gate electrode 230. Then, the moved electrons (e) are trapped by the floating gate electrode 230 such that the threshold voltage of the channel layer 250 increases and the electrical conductivity decreases.

[0121] Herein, the reference voltage means a voltage at which electrons included in the bottom gate electrode 210 can move over the first gate insulating layer 220 to the floating gate electrode 230.

[0122] According to such an operation principle, the synaptic transistor according to the second exemplary embodiment of the present invention may perform the operation of erasing of long-term memory characteristics.

[0123] As described above, the synaptic transistor according to the second exemplary embodiment of the present invention may provide a synaptic transistor that may provide both short-term memory characteristics and long-term memory characteristics. That is, it is possible to provide short-term memory characteristics by the movement of hydrogen ions present inside the first and second gate insulating layer 220 and 240, and to provide long-term memory characteristics by charge trap inside the bottom gate 210 or floating gate 230.

[0124] FIGS. 17A to 17F are diagrams for describing the manufacturing method of a synaptic transistor according to the second exemplary embodiment of the present invention.

[0125] First, referring to FIG. 17A, a bottom gate electrode 210 is formed on the substrate 200. For example, Cu may be melted using the electron beam vacuum evaporation (e-beam evaporator) to form a bottom gate electrode 210 having a thickness of about 20 nm on the substrate 200.

[0126] Next, referring to FIG. 17B, a first gate insulating layer 220 is formed on the substrate 200 so as to cover the bottom gate electrode 210. In this case, the first gate insulating layer 220 may include hydrogen ions.

[0127] For example, low-temperature atomic layer deposition (ALD) may be used to deposit Al.sub.2O.sub.3 to a relatively thin thickness of about 10 nm to form a first gate insulating layer 220. In this case, the first gate insulating layer 220 forms a weak ionic bond of AlOH by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated into AlO.sup. and H.sup.+ by gate bias such that a large number of hydrogen ions are included in the first gate insulation layer 220.

[0128] Next, referring to FIG. 17C, a floating gate electrode 230 is formed on the first gate insulating layer 220 to correspond to the bottom gate electrode 210. For example, the floating gate electrode 230 may be formed on the first gate insulating layer 220 by melting Cu using the electron beam vacuum evaporation (e-beam evaporator). In this case, the floating gate electrode 230 is preferably formed to be relatively thick with a thickness of about 30 nm to avoid interference with the channel layer 250 located thereon when electrons (e) are trapped in the floating gate electrode 230.

[0129] Next, referring to FIG. 17D, a second gate insulating layer 240 is formed on the first gate insulating layer 220 so as to cover the floating gate electrode 230. In this case, the second gate insulating layer 240 may include hydrogen ions.

[0130] For example, low-temperature atomic layer deposition (ALD) may be used to deposit Al.sub.2O.sub.3 to form a second gate insulating layer 240. In this case, the second gate insulating layer 240 is preferably formed to be relatively thick with a thickness of about 40 nm such that electrons (e) of the channel layer 250 do not pass to the floating gate electrode 230. In addition, the second gate insulating layer 240 forms a weak ionic bond of AlOH by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated into AlO.sup. and H.sup.+ by gate bias such that a large number of hydrogen ions are included in the second gate insulation layer 240.

[0131] Next, referring to FIG. 17E, a channel layer 250 is formed on the second gate insulating layer 240 to correspond to the floating gate electrode 230. For example, the channel layer 250 may be formed by depositing IGZO to a thickness of about 35 nm using the sputtering technique.

[0132] Next, referring to FIG. 17F, a source electrode 261 and a drain electrode 262 are formed to be spaced apart from each other on the second gate insulating layer 240 so as to cover both ends of the channel layer 250. For example, the source and drain electrodes 141, 142 may be formed to a thickness of about 30 nm on the second gate insulating layer 240 by melting Cu using the electron beam vacuum evaporation (e-beam evaporator).

[0133] Next, referring to FIG. 13, part of the bottom gate electrode 210 is exposed to the outside by etching the first and second gate insulating layers 220 and 240, which are at positions spaced apart from the channel layer 250 by a certain distance, to a depth of about 50 nm using the buffered oxide etch (BOE) process.

[0134] FIG. 18 is a plan view of the synaptic transistor according to a third exemplary embodiment of the present invention, FIG. 19 is a cross-sectional view taken along Section Line II-II of FIG. 18, and FIG. 20 is a cross-sectional view taken along Section Line III-III of FIG. 18.

[0135] Referring to FIGS. 18 to 20, the synaptic transistor according to a third exemplary embodiment of the present invention may be configured by including a substrate 300, a gate electrode 310, a gate insulating layer 321, a retention layer 322, a channel layer 330, and source and drain electrodes 341 and 342.

[0136] The gate electrode 310 is disposed to extend in one direction on the substrate 300, the gate insulating layer 321 covers the gate electrode 310 and is disposed on the substrate 300, and the retention layer 322 is disposed on the gate insulating layers 321.

[0137] The channel layer 330 is disposed on the retention layer 322 to correspond to one end of the gate electrode 310, and the source electrode 341 and the drain electrode 342 are spaced apart from each other, cover both ends of the channel layer 330, and are disposed on the retention layer 322. Herein, the channel layer 330 may be made of indium gallium zinc oxide (IGZO), which is an amorphous structure, and the gate electrode 310 and the source and drain electrodes 341, 342 may be made of Cu, which is a conductive material, but are not limited to

[0138] The gate insulating layer 321 includes ions, and these ions may be hydrogen ions.

[0139] To this end, the gate insulating layer 321 may be made of Al.sub.2O.sub.3 laminated by low-temperature atomic layer deposition (ALD). In this case, a weak ionic bond of AlOH is formed by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated into AlO.sup. and H.sup.+ by gate bias such that a large number of hydrogen ions are included in the gate insulating layer 321.

[0140] The hydrogen ions included in the gate insulating layer 321 move inside the gate insulation layer 321 and the retention layer 322 in accordance with the gate bias applied to the gate electrode 310, and by adjusting the number of the hydrogen ions moved to the side of the channel layer 330, it induces a gating effect and at the same time induces hysteresis.

[0141] The retention layer 322 is made of an insulating material having a greater hydrogen bonding force than the gate insulating layer 321. For example, the retention layer 322 may be made of SiO.sub.2, Si.sub.3N.sub.4 or the like.

[0142] Herein, the SiH bonding force inside the retention layer 322 is stronger than the AlH bonding force (28 KJ/mol) inside the gate insulating layer 321.

[0143] Accordingly, the movement speed of hydrogen ions in the retention layer 322 is slower than in the gate insulating layer 321. That is, hydrogen ions inside the retention layer 322 move relatively slowly into the gate insulating layer 321 to improve retention characteristics.

[0144] FIG. 21 is a diagram for describing the operation principle of a synaptic transistor according to the third exemplary embodiment of the present invention.

[0145] As illustrated in FIG. 21(a), when a positive bias is applied to the gate electrode 310, hydrogen ions (H.sup.+) move from side of the gate electrode 310 to the side of the channel layer 330. That is, when a positive bias is applied to the gate electrode 310, the hydrogen ions (H.sup.+) inside the gate insulating layer 321 move upward by the repulsive force thereof to be adjacent to the channel layer 330 via the retention layer 322.

[0146] As such, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 330 increases, the threshold voltage decreases and the electrical conductivity increases.

[0147] Unlike the above, as illustrated in FIG. 21(b), when a negative bias is applied to the gate electrode 310, the hydrogen ions (H.sup.+) inside the retention layer 322 move downward due to the attraction force thereof to be adjacent to the gate electrode 310 via the gate insulating layer 321.

[0148] As such, as the number of hydrogen ions (H.sup.+) adjacent to the channel layer 330 decreases, the threshold voltage increases and the electrical conductivity decreases.

[0149] Meanwhile, since the SiH bonding force in the retention layer 322 is stronger than the AlH bonding force (28 KJ/mol) in the gate insulating layer 321, the movement speed of hydrogen ions in the retention layer 322 becomes slower than that in the gate insulation layer 322. That is, the hydrogen ions inside the retention layer 322 move relatively slowly into the gate insulating layer 321 to improve the retention characteristics.

[0150] As such, in the synaptic transistor according to the third exemplary embodiment of the present invention, by further disposing the retention layer 322 between the gate insulating layer 321 and the channel layer 322, it is possible to lower the threshold voltage and at the same time improve the retention characteristics for long-term memory.

[0151] FIG. 22 is a graph showing the threshold voltages of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention, FIG. 23 is a graph showing the sub-threshold swings (SS) of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention, and FIG. 24 is a graph illustrating the mobilities of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention. In addition, FIG. 25 is a graph illustrating the amount of change in current with respect to the number of pulses of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention, and FIG. 26 is a graph illustrating the amount of change in current with respect to the time of a conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the invention.

[0152] Herein, the conventional synaptic transistor is denoted by A-Type in which the retention layer 322 is not disposed between the gate insulating layer 321 and the channel layer 330, and the synaptic transistor according to the third exemplary embodiment of the present invention is denoted by B-Type. Then, the width W and the length L of the channel layer 330 were formed to be 50 m and 20 m, respectively, and the experiment was performed.

[0153] Referring to FIG. 22, it can be confirmed that the threshold voltage V.sub.T of A-Type is about 2.1 V, and the threshold voltage V.sub.T of B-Type is about 0.3 V. Thus, it can be experimentally confirmed that the synaptic transistor according to the third exemplary embodiment of the present invention has a low threshold voltage V.sub.T compared to the conventional one.

[0154] Referring to FIG. 23, it can be confirmed that the sub-threshold swing (SS) of A-Type is about 0.2 V/dec and the sub-threshold swing (SS) of B-type is about 0.3 V/dec. As described above, it can be experimentally confirmed that the sub-threshold swing (SS) of the synaptic transistor according to the third exemplary embodiment of the present invention has almost no difference from that of the conventional one.

[0155] Referring to FIG. 24, it can be confirmed that the mobility of A-Type (.sub.FE,sat) is about 11 cm.sup.2/Vs, and the mobility of B-Type (.sub.FE,sat) is about 9 cm.sup.2/Vs. Thus, it can be experimentally confirmed that the mobility of the synaptic transistor (.sub.FE,sat) according to the third exemplary embodiment of the present has almost no difference from that of the conventional one.

[0156] As such, the synaptic transistor according to the third exemplary embodiment of the present invention may lower the threshold voltage V.sub.T and improve the electric conductivity without affecting the sub-threshold swing (SS) and mobility (.sub.FE,sat) compared to the conventional one.

[0157] Referring to FIG. 25, the current change amount I was measured by applying pulses in a range of 0 to 64 to the conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention.

[0158] As a result of the measurement, it can be experimentally confirmed that the current change amount I of the synaptic transistor according to the third exemplary embodiment of the present invention was increased in accordance with the pulse number compared to the conventional one.

[0159] As such, in the synaptic transistor according to the third exemplary embodiment of the present invention, an increase width of the drain current in accordance with the pulse number compared to the conventional one is increased, and the synaptic characteristics may be improved.

[0160] Referring to FIG. 26(a), the current change amount I according to the time change after applying a pulse to the conventional synaptic transistor and the synaptic transistor according to the third exemplary embodiment of the present invention was measured.

[0161] As a result of the measurement, it can be experimentally confirmed that the A-Type does not maintain the current for 400 seconds after the application of the pulse and recovers all, whereas the B-Type maintains about 65% of the current for 400 seconds after the application of the pulse.

[0162] Referring to FIGS. 26(b) and 26(b), the graph of FIG. 26(a) was subjected to exponential fitting to calculate and compare tau values of A-Type and B-Type.

[0163] Specifically, the graph of FIG. 26(a) may be defined by FIG. 26(b) and Mathematical Formula 1 below, and the first and second tau values .sub.1, .sub.2 may be calculated by Mathematical Expression 1.

[00002]$\begin{array}{cc}{I}_1\exp \left(-t/{}_1\right)+I2\exp \left(-t/{}_2\right)& <\mathrm{Mathematical}\mathrm{Expression}1>\end{array}$

[0164] As a result of the calculation, it can be confirmed that the first tau value (.sub.1,A-Type) of A-Type and the first tau value (.sub.1,B-Type), of B-Type are equal to 0.01, whereas the second tau value of A-Type (.sub.2,A-type) is 410.sup.3, and the second tau value of B-Type (.sub.2,B-type) is 410.sup.4, and thus, the retention characteristics of B-Type were improved by 10 times or more than that of A-Type.

[0165] In summary, the synaptic transistor according to the third exemplary embodiment of the present invention may improve the retention characteristics while lowering the threshold voltage without deterioration of the relatively large characteristics (e.g., mobility) compared to the conventional transistor.

[0166] FIGS. 27A to 27E are diagrams for describing the manufacturing method of a synaptic transistor according to the third exemplary embodiment of the present invention.

[0167] First, referring to FIG. 27A, a gate electrode 310 is formed to extend in one direction on the substrate 300. For example, Cu may be melted using the electron beam vacuum evaporation (e-beam evaporator) to form a gate electrode 310 having a thickness of about 20 nm on the substrate 300.

[0168] Next, referring to FIG. 27B, a gate insulating layer 321 is formed on the substrate 300 so as to cover the gate electrode 310. In this case, the gate insulating layer 321 may include hydrogen ions.

[0169] For example, low-temperature atomic layer deposition (ALD) may be used to deposit Al.sub.2O.sub.3 to a thickness of about 40 nm to form a gate insulating layer 321. In this case, a weak ionic bond of AlOH is formed by H.sub.2O used in the atomic layer deposition process. This ionic bond is separated into AlO.sup. and H.sup.+ by gate bias such that a large number of hydrogen ions are included in the gate insulating layer 321.

[0170] Next, referring to FIG. 27C, a retention layer 322 is formed on the gate insulating layer 321. In this case, the retention layer 322 may be formed of an insulating material having a stronger hydrogen bonding force than the gate insulating layer 321. For example, the retention layer 322 may be formed of SiO.sub.2, Si.sub.3N.sub.4 or the like.

[0171] Next, referring to FIG. 27D, a channel layer 330 is formed on the retention layer 322 to correspond to one end of the gate electrode 310. For example, the channel layer 330 may be formed by depositing IGZO to a thickness of about 35 nm using the sputtering technique.

[0172] Next, referring to FIG. 27E, a source electrode 341 and a drain electrode 342 are formed on the retention layer 322 so as to be spaced apart from each other and cover both ends of the channel layer 330. For example, the source and drain electrodes 341 and 342 may be respectively formed to a thickness of about 30 nm on the retention layer 322 by melting Cu using the electron beam vacuum evaporation (e-beam evaporator).