BI-MODE INSULATED GATE TRANSISTOR

Abstract

The present invention discloses a bi-mode insulated gate transistor, belonging to the technical filed of IGBTs. The bi-mode insulated gate transistor includes a reverse conducting region and a pilot region, wherein the reverse conducting region and the pilot region each include P+ collector regions, a drift region and a MOS cell region, the drift regions are disposed over the P+ collector regions, and the MOS cell regions are disposed over the drift regions; the reverse conducting region further includes N+ collector regions, and the N+ collector regions and the P+ collector regions are distributed alternatively; the pilot region further includes a separation region or a low-doped region, the separation region isolates the P+ collector regions of the pilot region from the P+ collector regions and the N+ collector regions of the reverse conducting region, and the low doped region is disposed over the P+ collector regions of the pilot region. In the present invention, the resistance of an electron current channel over the pilot region or a built-in potential of a PN junction of the collector of the pilot region is increased when a device works in a VDMOS mode, in order to reduce the size of the pilot region of the bi-mode insulated gate transistor, so that the uniformity of current intensity inside the device in work is increased, and the overall reliability of the device is further improved.

Claims

1. A bi-mode insulated gate transistor, comprising a reverse conducting region and a pilot region; wherein the reverse conducting region and the pilot region each comprise P+ collector regions, a drift region and a MOS cell region, wherein the drift regions are disposed over the P+ collector regions, and the MOS cell regions are disposed over the drift regions; the reverse conducting region further comprises N+ collector regions, and the N+ collector regions and the P+ collector regions are alternatively distributed; and wherein the guide region further comprises a separation region or a low doped region, the separation region isolates the P+ collector regions of the pilot region from the P+ collector regions and the N+ collector regions of the reverse conducting region, and the low doped region is disposed over the P+ collector regions of the pilot region.

2. The bi-mode insulated gate transistor of claim 1, wherein the reverse conducting region and the pilot region each further comprise an N+ buffer layer, the N+ buffer layer of the reverse conducting region is between the P+ collector regions or the N+ collector regions of the reverse conducting region and the drift region of the reverse conducting region, the N+ buffer layer of the pilot region is between the P+ collector regions of the pilot region and the drift region of the pilot region, and the separation region of the pilot region isolates the N+ buffer layer of the reverse conducting region and the N+buffer layer of the pilot region.

3. The bi-mode insulated gate transistor of claim 2, wherein an insulator region is below the separation region, the insulator region is located between a silicon substrate and a collector metal layer, and the width of the insulator region is adjusted to realize potential isolation of the N+ buffer layer of the pilot region and collector metal.

4. The bi-mode insulated gate transistor of claim 1, wherein the separation region is a groove filled with an insulator.

5. The bi-mode insulated gate transistor of claim 2, wherein the concentration of the N+ buffer layer of the pilot region is smaller than that of the N+ buffer layer of the reverse conducting region.

6. The bi-mode insulated gate transistor of claim 2, wherein the concentration of the low doped region is smaller than those of the N+ buffer layer of the pilot region and the P+ collector region of the pilot region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a bi-mode insulated gate transistor provided by embodiment 1 of the present invention, wherein over one side of an insulator close to a reverse conducting region is a P+ collector region;

[0019] FIG. 2 is a bi-mode insulated gate transistor provided by embodiment 1 of the present invention, wherein over one side of an insulator close to a reverse conducting region is an N+ collector region;

[0020] FIG. 3 is a backside layout of a bi-mode insulated gate transistor with an N+ collector region of a strip shape provided by embodiment 1 of the present invention;

[0021] FIG. 4 is a backside layout of a bi-mode insulated gate transistor with an N+ collector region of a round shape provided by embodiment 1 of the present invention;

[0022] FIG. 5 is a bi-mode insulated gate transistor provided by embodiment 2 of the present invention, wherein over one side of a groove an insulator close to a reverse conducting region is a P+ collector region and a separation region is a groove;

[0023] FIG. 6 is a bi-mode insulated gate transistor provided by embodiment 2 of the present invention, wherein on one side of a groove of an insulator close to a reverse conducting region is an N+ collector region and a separation region is a groove;

[0024] FIG. 7 is a bi-mode insulated gate transistor provided by embodiment 3 of the present invention, wherein no N+ buffer layer is provided, and on one side of a groove of an insulator close to a reverse conducting region is a P+ collector region;

[0025] FIG. 8 is a bi-mode insulated gate transistor provided by embodiment 3 of the present invention, wherein no N+ buffer layer is provided, and on one side of a groove of an insulator close to a reverse conducting region is an N+ collector region;

[0026] FIG. 9 is a bi-mode insulated gate transistor provided by embodiment 4 of the present invention, wherein the doped concentration of the buffer layer of a pilot region is smaller than that of the buffer layer of a reverse conducting region and the buffer layer with low concentration partially covers a P+ collector region;

[0027] FIG. 10 is a bi-mode insulated gate transistor provided by embodiment 4 of the present invention, wherein the doped concentration of the buffer layer of a pilot region is smaller than that of the buffer layer of a reverse conducting region and the buffer layer with low concentration wholly covers a P+ collector region;

[0028] FIG. 11 is a bi-mode insulated gate transistor provided by embodiment 5 of the present invention, wherein a pilot region includes a low doped region wholly covering a P+ collector region.

[0029] FIG. 12 is a bi-mode insulated gate transistor provided by embodiment 5 of the present invention, wherein a pilot region includes a low doped region partially covering a P+ collector region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Referring to FIG. 1, embodiments of the present invention provide a bi-mode insulated gate transistor, including a reverse conducting region and a pilot region; [0031] the reverse conducting region and the pilot region each include P+ collector regions, a drift region and a MOS cell region, wherein the drift regions are disposed over the P+ collector regions, and the MOS cell regions are disposed over the drift regions; [0032] the reverse conducting region further includes N+ collector regions, and the N+ collector regions and the P+ collector regions are alternatively distributed; [0033] the guide region further includes a separation region or a low doped region, the separation region isolates the P+ collector regions of the pilot region from the P+ collector regions and the N+ collector regions of the reverse conducting region, and the low doped region is disposed over the P+ collector regions of the pilot region. [0034] As for the bi-mode insulated gate transistor provided by the present invention, the separation region or the insulator groove is arranged to increase the resistance of an electron current channel of a device in a VDMOS mode, and reduce the size of the pilot region of the bi-mode insulated gate transistor. The current inside the chip is distributed more uniformly when the device is in work, so that the overall reliability of the device is improved. In addition, the low doped region is arranged to reduce the turn-on voltage of a collector PN of the pilot region, so as to reduce the size of the pilot region of the bi-mode insulated gate transistor. The current inside the chip is distributed more uniformly when the device is in work, so that the overall reliability of the device is improved.

Embodiment 1

[0035] Referring to FIGS. 1, 2 3 and 4, the pilot region includes a separation region in the embodiment, the basic conception of which is that the N+ buffer layer of the pilot region is separated from the N+ buffer layer of the reverse conducting region, that is to say, the two buffer layers are isolated from each other, as shown in FIGS. 1 and 2. The separation region is a doped semiconductor substrate to which no buffer layer is introduced, and generally, the doped concentration of the separation region is generally the same as that of an N drift region. Of course, a small amount of impurities may be properly introduced or the separation region is manufactured into a semiconductor structure of which the resistivity is large than that of the N drift region.

[0036] In order to ensure the voltage withstanding performance of a device, an insulator region of a certain size is manufactured under the separation region, and is located between the semiconductor substrate and a collector metal layer. Potential isolation of the N+ buffer layer and a collector metal should be ensured through the width of the insulator, the insulator region has the function of preventing punch-through breakdown caused by contact of a boundary of a depletion region and the collector metal when the device withstands voltage.

[0037] In the embodiment, over one side of the insulator close to the reverse conducting region may be arranged a segment of a P+ collector region (as in FIG. 1), or may be directly arranged an N+ collector region (as in FIG. 2).

[0038] FIGS. 3 and 4 are used as examples for a backside layout. Isolation of the buffer layer of the pilot region may reduce the space between the N+ collector regions on two sides of or surrounding the pilot region to a level equivalent to the space between the N+ collector regions of the reverse conducting region. Thus, the N+ collector regions can be uniformly and regularly distributed within a whole chip, thus greatly improving the current uniformity. In this way, when the device is in a VDMOS mode, electron current over the pilot region must flow through the buffer layer (with the distribution resistance of Rb1) of the pilot region, a low doped region (with the distribution resistance of Rd) of the separation region, and a buffer layer (with the distribution resistance of Rb2) of the reverse conducting region. The low doped region is between the buffer layers, so Rd>>Rb1+Rb2. The introduction of Rd enables the pilot region to be sufficient to suppress snap-back of the device without widening the P+ collector regions, so that the space between the N+ collector regions on two sides of or surrounding the pilot region is reduced. The size of Rd can be controlled by adjusting the width and doped concentration of the low doped region at discontinuity of the buffer layer, so that the width of the pilot region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, so that the problem of current uniformity is greatly improved. Generally, the larger the width of the low doped region between the buffer layers is, the lower the doped concentration is, the larger Rd is, and the more the reduction of the width of the pilot region may be. However, it is not better that the resistance of Rd is larger, as long as it can ensure that snap-back of the device does not occur.

Embodiment 2

[0039] The bi-mode insulated gate transistor provided by the embodiment is similar to that in embodiment 1 in structure. The two differ in that the separation region of embodiment 2 is a groove filled with an insulator, and the N+ buffer layer and the collector region are separated by the groove filled with the insulator (as shown in FIGS. 5 and 6). The buffer layer at the left side of the groove as shown in the figure is the buffer layer of the pilot region, and the buffer layer at the right side of the groove is the buffer layer of the reverse conducting region.

[0040] In the embodiment, over one side of the insulator close to the reverse conducting region may be arranged a segment of a P+ collector region (as in FIG. 5), or may be directly arranged an N+ collector region (as in FIG. 6).

[0041] When the device is in a VDMOS mode, electron current over the pilot region must flow through the buffer layer (with the distribution resistance of Rb1) of the pilot region, low doped regions (with the distribution resistance of Rd) on two sides of and above the groove, and a buffer layer (with the distribution resistance of Rb2) of the reverse conducting region. The low doped regions are on two ides of and above the groove, so Rd>>Rb1+Rb2. The introduction of Rd enables the pilot region to be sufficient to suppress snap-back of the device without widening the P+ collector region, so that the space between the N+ collector regions on two sides of or surrounding the pilot region is reduced. The size of Rd can be controlled by adjusting the width and depth of the groove, so that the width of the pilot region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, so that the problem of current uniformity is greatly improved. Generally, the larger the width and depth of the groove are, the larger Rd is, and the more the reduction of the width of the pilot region may be. However, it is not better that the resistance of Rd is larger, as long as it is ensured that snap-back of the device does not occur.

Embodiment 3

[0042] In fact, not only can the bi-mode insulated gate transistor of an FS structure adopt this solution, but also the current uniformity of the bi-mode insulated gate transistor of an NPT structure can be improved. The structure of the reverse conducting region proposed in embodiment 3 is similar to that of embodiment 2. The two differ in that the structure in embodiment 3 does not include the N+ buffer layer structure.

[0043] In the embodiment, on one side of the insulator close to the reverse conducting region may be arranged a segment of a P+ collector region (as in FIG. 7), or may be directly arranged an N+ collector region (as in FIG. 8).

[0044] When the device is in a VDMOS mode, electron current over the pilot region must flow through the drift region (with the distribution resistance of Rd1) of the pilot region, low doped regions (with the distribution resistance of Rd) on two sides of and above the groove, and the drift region (with the distribution resistance of Rd2) over the N+ collector region of the reverse conducting region. The introduction of Rd enables the pilot region to be sufficient to suppress snap-back of the device without widening the P+ collector region, so that the space between the N+ collector regions on two sides of or surrounding the pilot region is reduced. The size of Rd can be controlled by adjusting the width and depth of the groove, so that the width of the pilot region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, so that the problem of current uniformity is greatly improved. Generally, the larger the width and depth of the groove are, the larger Rd is, and the more the reduction of the width of the pilot region may be. However, it is not better that the resistance of Rd is larger, as long as it is ensured that snap-back of the device does not occur.

Embodiment 4

[0045] In the embodiment, the doped concentration of the N+ buffer layer of the pilot region is properly reduced on the premise of ensuring enough voltage withstanding of the device. That is to say, the doped concentration of the buffer layer of the pilot region is smaller than that of the buffer layer of the reverse conducting region.

[0046] In the embodiment, the low doped buffer layer over the pilot region can partially cover the P+ collector region (as in FIG. 9), or wholly cover the P+ collector region (as in FIG. 10), or even wholly or partially cover adjacent N+ collector regions.

[0047] When the device is in a VDMOS mode, electron current over the pilot region must flow through the low doped buffer layer (with the distribution resistance of Rb1) of the pilot region, and a high doped buffer layer (with the distribution resistance of Rb2) of the pilot region. Due to the introduction of the low doped buffer layer, Rb1+Rb2 reaches a high level. In addition, due to the introduction of the low doped buffer layer, the turn-on voltage of the PN junction formed by the P+ collector region and the N+ buffer layer is reduced. The two factors above enable the pilot region to be sufficient to suppress snap-back of the device without widening the P+ collector region, so that the space between the N+ collector regions on two sides of or surrounding the pilot region is reduced. The size of Rb1 can be controlled by adjusting the length of the low doped buffer layer, so that the width of the pilot region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, so that the problem of current uniformity is greatly improved. Generally, the larger the length of the low doped buffer layer is, the larger Rb1 is, and the more the reduction of the width of the pilot region may be. However, it is not better that the resistance of Rb1 is larger, as long as it is ensured that snap-back of the device does not occur.

Embodiment 5

[0048] In the embodiment, the doped concentration of the low doped region is smaller than those of the N+ buffer layer of the pilot region and the P+ collector regions of the pilot region.

[0049] The low doped region may be P-type or N-type, or may also include a P region and an N region. In the case of including both the P region and the N region, it needs to ensure the P-type low doped region is located over the P+ collector region, and the N-type low doped region is located between the P-type low-doped region and the N+ buffer layer.

[0050] In the embodiment, the low doped region of the pilot region can partially cover the P+ collector region (as in FIG. 11), or wholly cover the P+ collector region (as in FIG. 12), or even wholly or partially cover adjacent N+ collector regions.

[0051] The low doped region is introduced between the N+ buffer layer of the pilot region and the P+ collector region of the device, so that a low doped semiconductor is located on one or two sides of the PN junction of the collector, in order to greatly reduce the turn-on voltage of the PN junction. Therefore, the pilot region is sufficient to suppress snap-back of the device without widening the P+ collector region, so that the space between the N+ collector regions on two sides of or surrounding the pilot region is reduced. The amplitude of turn-on voltage of the PN junction can be controlled by adjusting the concentration of the low doped region, so that the width of the pilot region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, so that the problem of current uniformity is greatly improved. Generally, the lower the doped concentration of the low doped region is, the smaller the voltage required by turning on the collector junction is, and the more the reduction of the width of the pilot region may be.

[0052] According to the bi-mode insulated gate transistor provided by the embodiments of the present invention, the width of the pilot region of the bi-mode insulated gate transistor can be reduced from hundreds of micrometers to dozens of micrometers, thus greatly improving the current uniformity of the chip of the bi-mode insulated gate transistor and improving the reliability of the device. Specifically, the power circulation capability, the capability of resisting current overshoot and the capability of resisting short circuit and the like of the device can be improved.

[0053] The layout solution in actual engineering may include various patterns, however, a pilot structure of a small size is formed by isolating part of the P+ collector region according to the structure provided by the embodiments of the present invention. Those solutions through which the width of the P+ collector region of the pilot region can be reduced are not listed one by one in the patent, and all solutions adopting specific technical solutions to reduce the width of the P+ collector region of the pilot region so as to improve the current uniformity are within the protection scope of the patent.

[0054] Therefore, the bi-mode insulated gate transistor has the disadvantage that the space between the N+ collector regions on two sides of or surrounding the pilot region is too large, which results in current concentration. The thought of the patent is to reduce the width of the pilot region by virtue of various methods, that is, to reduce the space between the N+ collector regions on two sides of or surrounding the pilot region, thus the current distribution of the pilot region of the bi-mode insulated gate transistor can be further improved and further the reliability of the device is improved.

[0055] Finally, it should be noted that the specific embodiments above are merely used for illustrating, rather than limiting the technical solution of the present invention. Although the present invention has been illustrated in detail with reference to examples, it should be understood by those of ordinary skill in the art they can make modifications or equivalent substitutions to the technical of the present invention without departing from the spirit and scope of the technical solution of the present invention, and these modifications or equivalent substitutions should be encompassed in the claims of the present invention.