Individually read-accessible twin memory cells

Abstract

The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

Claims

1. A non-volatile memory on a semiconductor substrate, comprising: a first memory cell including a first floating-gate transistor, a select transistor electrically coupled to the first floating-gate transistor of the first memory cell, and a second floating-gate transistor, the select transistor of the first memory cell having a vertical control gate embedded in the substrate and a vertical channel region extending along a first face of the vertical control gate; a second memory cell including a first floating-gate transistor, a select transistor electrically coupled to the first floating-gate transistor of the second memory cell, and a second floating-gate transistor, the select transistor of the second memory cell sharing the vertical control gate of the select transistor of the first memory cell and having a vertical channel region that extends along a second face of the vertical control gate that is on an opposite side of the vertical control gate with respect to the first face; a first bit line electrically coupled to the first floating-gate transistor of the first memory cell; a second bit line electrically coupled to the first floating-gate transistor of the second memory cell; a first control gate line electrically coupled to a control gate of the first floating-gate transistor of the first memory cell; and a second control gate line electrically coupled to a control gate of the first floating-gate transistor of the second memory cell.

2. The memory according to claim 1, comprising: a read circuit configured to: read the first memory cell by applying a positive select voltage to the first control gate line and reading the first memory cell through the first bit line; and read the second memory cell by applying a positive select voltage to the second control gate line and reading the second memory cell through the second bit line.

3. The memory according to claim 2, wherein the read circuit includes a word line decoder configured to: allocate to the first and second control gate lines a same line address, and in response to a request to read, program, or erase a requested memory cell of the memory cells, select the control gate line to which the requested memory cell is coupled according, firstly, to the line address of the first and second control gate lines and, secondly, to a least significant bit of a column address of the requested memory cell.

4. The memory according to claim 1, wherein the second floating-gate transistors of the first memory cell and the second memory cell each includes a floating gate, a conductive region extending below the floating gate, a conduction terminal electrically coupled to the conductive region, and a tunnel dielectric layer extending between the conductive region and the floating gate.

5. The memory according to claim 1, comprising a third bit line electrically coupled both to the second floating-gate transistor of the first memory cell and to the second floating-gate transistor of the second memory cell.

6. The memory according to claim 1, wherein the first floating gate transistor of the first memory cell includes a first floating gate, and the second floating-gate transistor of the first memory cell includes a second floating gate electrically coupled to the first floating gate.

7. The memory according to claim 4, wherein the conductive region is a doped region of the substrate.

8. An integrated circuit on a semiconductor chip, comprising a non-volatile memory that includes: a first memory cell including a first floating-gate transistor having a first floating gate, a select transistor electrically coupled to the first floating-gate transistor of the first memory cell, and a second floating-gate transistor having a second floating gate, the second floating gate being electrically coupled to the first floating gate, the select transistor of the first memory cell having a vertical control gate embedded in the substrate and a vertical channel region extending along a first face of the vertical control gate; a second memory cell including a first floating-gate transistor, a select transistor electrically coupled to each other, the select transistor of the second memory cell sharing the vertical control gate of the select transistor of the first memory cell and having a vertical channel region that extends along a second face of the vertical control gate that is on an opposite side of the vertical control gate with respect to the first face; a first bit line electrically coupled to the first floating-gate transistor of the first memory cell; a second bit line electrically coupled to the first floating-gate transistor of the second memory cell; a first control gate line electrically coupled to a control gate of the first floating-gate transistor of the first memory cell; and a second control gate line electrically coupled to a control gate of the first floating-gate transistor of the second memory cell.

9. The integrated circuit according to claim 8, comprising a read circuit configured to: read the first memory cell by applying a positive select voltage to the first control gate line and reading the first memory cell through the first bit line; and read the second memory cell by applying a positive select voltage to the second control gate line and reading the second memory cell through the second bit line.

10. The integrated circuit according to claim 9, wherein the read circuit includes a word line decoder configured to: allocate to the first and second control gate lines a same line address; and in response to a request to read, program, or erase a requested memory cell of the memory cells, select the control gate line to which the requested memory cell is coupled according, firstly, to the line address of the first and second control gate lines and, secondly, to a least significant bit of a column address of the requested memory cell.

11. The integrated circuit according to claim 8, wherein the second floating-gate transistor includes a conductive region extending below the second floating gate, a conduction terminal electrically coupled to the conductive region, and a tunnel dielectric layer extending between the conductive region and the second floating gate.

12. The integrated circuit according to claim 8, wherein the second memory cell includes a second floating-gate transistor having a third floating gate, and the first floating-gate transistor of the second memory cell includes a fourth floating gate that is electrically coupled to the third floating gate.

13. The integrated circuit according to claim 8, wherein the first and second floating gates are formed by a same piece of a conductive material.

14. The integrated circuit according to claim 11, wherein the conductive region is a doped region of the substrate.

15. A method for manufacturing a memory, comprising: forming a first memory cell including a first floating-gate transistor and a select transistor electrically coupled to each other, the select transistor of the first memory cell having a vertical control gate embedded in a substrate and a vertical channel region extending along a first face of the vertical control gate; forming a second memory cell including a first floating-gate transistor and a select transistor electrically coupled to each other, the select transistor of the second memory cell sharing the vertical control gate of the select transistor of the first memory cell and having a vertical channel region that extends along a second face of the vertical control gate that is on an opposite side of the vertical control gate with respect to the first face; forming a first bit line electrically coupled to the first floating-gate transistor of the first memory cell; forming a second bit line electrically coupled to the first floating-gate transistor of the second memory cell, the forming of the first bit line and the second bit line including: forming, in a first level of metal, two first bit line sections that are each electrically coupled to a drain region of one of the first floating-gate transistors; forming, in a second level of metal, two second bit line sections that are each electrically coupled to one of the two first bit line sections; and forming, in a third level of metal, two third bit line sections that are each electrically coupled to one of the two second bit line sections; forming a first control gate line electrically coupled to a control gate of the first floating-gate transistor of the first memory cell; and forming a second control gate line electrically coupled to a control gate of the first floating-gate transistor of the second memory cell.

16. The manufacturing method of claim according to claim 15, comprising: forming in the substrate isolating trenches delimiting a first strip of substrate; forming the control gate common to the select transistors of the first and second memory cells by forming in the substrate a conductive trench arranged transversally to the first strip of substrate; forming on the substrate a first dielectric layer and forming on the first dielectric layer a conductive floating gate of one of the first and second floating-gate transistors, the floating gate arranged transversally to the strip of substrate; forming a second dielectric layer on the floating gate; forming a control gate on the second dielectric layer, to obtain a gate stack; doping the strip of substrate at opposite sides of the gate stack.

17. The manufacturing method according to claim 16, comprising doping a second strip of substrate before forming the gate stack and before doping the substrate on opposite sides of the gate stack, to form a conducting region opposite the floating gate of the second floating-gate transistor.

18. The memory according to claim 6, wherein the first and second floating gates are formed by a same piece of a conductive material.

19. The integrated circuit according to claim 12, wherein the memory includes a third bit line electrically coupled both to the second floating-gate transistor of the first memory cell and to the second floating-gate transistor of the second memory cell.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) Some embodiments of and methods for manufacturing a memory array and memory cell structure according to the present disclosure, and methods for reading and writing memory cells according to the present disclosure, will be described below in relation with, but not limited to, the accompanying figures, in which:

(2) FIG. 1 described above is the wiring diagram of a conventional memory array and memory cell structure,

(3) FIG. 2 is the wiring diagram of a first embodiment of a memory array and memory cell structure according to a first improvement according to the present disclosure,

(4) FIG. 3 is a cross-section of a memory cell in FIG. 2,

(5) FIG. 4 is another cross-section of the memory cell,

(6) FIG. 5 shows voltages applied to the memory array in FIG. 2 to erase a memory cell,

(7) FIG. 6 is a cross-section of a memory cell in FIG. 5, and shows voltages applied to the memory cell,

(8) FIG. 7 is another cross-section of the memory cell, and shows the voltages applied to the memory cell,

(9) FIG. 8 shows voltages applied to the memory array in FIG. 2 to program a memory cell by Fowler Nordheim effect,

(10) FIG. 9 is a cross-section of a memory cell in FIG. 8 and shows voltages applied to the memory cell,

(11) FIG. 10 is another cross-section of the memory cell and shows the voltages applied to the memory cell,

(12) FIG. 11 shows voltages applied to the memory array in FIG. 2 to program a memory cell by hot-electron injection,

(13) FIG. 12 is a cross-section of a memory cell in FIG. 11 and shows voltages applied to the memory cell,

(14) FIG. 13 shows voltages applied to the memory array in FIG. 2 to read a memory cell,

(15) FIG. 14 is a cross-section of a memory cell in FIG. 13 and shows voltages applied to the memory cell,

(16) FIGS. 15 to 24 show steps of a method for manufacturing a memory cell shown on FIGS. 2 to 4,

(17) FIG. 25 is the wiring diagram of a memory comprising the memory array in FIG. 2,

(18) FIG. 26 is the wiring diagram of a second embodiment of a memory array and memory cell structure according to the first improvement,

(19) FIG. 27 is the wiring diagram of a first embodiment of a memory array and memory cell structure according to a second improvement according to the present disclosure,

(20) FIGS. 28 to 32 show steps of a method for manufacturing a memory cell shown on FIG. 27,

(21) FIG. 33 shows voltages applied to the memory array in FIG. 27 to read a memory cell,

(22) FIG. 34 is the wiring diagram of a memory comprising the memory array in FIG. 27,

(23) FIG. 35 is the wiring diagram of a second embodiment of a memory array and memory cell structure according to the second improvement.

DETAILED DESCRIPTION

(24) FIG. 2 is the wiring diagram of one embodiment of two memory cells C.sub.i,j, C.sub.i1,j and of a memory array MA1 according to a first improvement according to the present disclosure of the memory array and memory cell structure in FIG. 1.

(25) The memory cells are read- and write-accessible via a first bit line RBL.sub.j, a second bit line EBL.sub.j, a word line WL.sub.i1,i, and two control gate lines CGL.sub.i, CGL.sub.i1. The memory cell C.sub.i,j belongs to a physical page P.sub.i of the memory array and the memory cell C.sub.i1,j belongs to an adjacent page P.sub.i1. The pages P.sub.i, P.sub.i1 may comprise various other memory cells and the memory array MA1 may comprise various other pages.

(26) The memory cell C.sub.i,j comprises two floating-gate transistors TR.sub.i,j, TE.sub.i,j the floating gates FGr, FGe of which are interconnected, the floating-gate transistor TR.sub.i,j being dedicated to reading the transistor memory cell and the floating-gate transistor TE.sub.i,j being dedicated to erasing the memory cell. According to one embodiment, the floating gates FGr, FGe are interconnected by manufacturing the two floating gates from a same conducting element CFG.

(27) The transistor TR.sub.i,j has a control gate CGr connected to the control gate line CGL.sub.i, a drain terminal D connected to the bit line RBL.sub.j and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL. The transistor TE.sub.i,j has a control gate CGe connected to the control gate line CGL.sub.i, a drain terminal D connected to the bit line EBL.sub.j and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL.

(28) The memory cell C.sub.i,j has the same structure as the memory cell C.sub.i,j and comprises two floating-gate transistors TR.sub.i1,j, TE.sub.i1,j the floating gates FGr, FGe of which are interconnected and/or formed by a same conducting element CFG. The transistor TR.sub.i1,j has a control gate CGr connected to the control gate line CGL.sub.i1, a drain terminal D connected to the bit line RBL.sub.j and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL. The floating-gate transistor TE.sub.i1,j has a control gate CGe connected to the control gate line CGL.sub.i1, a drain terminal D connected to the bit line EBL.sub.j and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL.

(29) The select transistors ST associated with the floating-gate transistors TR.sub.i,j, TR.sub.i1,j have a common control gate CSG connected to the word line WL.sub.i1,i, that is preferentially produced in the form of a vertical gate embedded in a substrate receiving the memory array MA0. Similarly, the select transistors ST associated with the floating-gate transistors TE.sub.i,j, TE.sub.i1,j have a common embedded vertical control gate CSG that is connected to the word line WL.sub.i1,i. The memory cell C.sub.i,j is thus, structurally, the equivalent of the combination of the memory cells M.sub.i,j, M.sub.i,j+1 shown on FIG. 1, the floating gates of which have been electrically coupled. Similarly, the memory cell is, structurally, the equivalent of the combination of the memory cells M.sub.i1,j, M.sub.i1,j+1 shown on FIG. 1 the floating gates of which have been electrically coupled. The two memory cells may thus be referred to as dual memory cells. As their select transistors ST have the same control gate in pairs, these memory cells may also be referred to as twin memory cells.

(30) However, the floating-gate transistor TE.sub.i,j differs from the floating-gate transistor T.sub.i,j+1 of the memory cell M.sub.i,j+1 in that it comprises a conducting region IS that extends opposite its floating gate FGe with interposition of a tunnel dielectric layer, and which is electrically coupled to its drain terminal D. Similarly, the floating-gate transistor TE.sub.i1,j differs from the floating-gate transistor T.sub.i1,j+1 of the memory cell M.sub.i1,j+1 in that it comprises a conducting region IS that extends opposite its floating gate FGe through a tunnel dielectric layer, and which is electrically coupled to its drain terminal D.

(31) FIG. 3 is a cross-section of one embodiment of the transistors TE.sub.i,j, TE.sub.i1,j and of their respective select transistors ST. The floating-gate transistors are produced on a substrate PW, for example made of silicon, forming the upper region of a semiconductor chip WF. The chip WF is initially a wafer on which several integrated circuits are produced, which is then cut into individual chips.

(32) The source lines SL of the select transistors ST are formed by a deep doped region n0 that here forms a collective source plane for the entire memory array. The common control gate CSG of the select transistors ST is formed with a conducting material, for example polysilicon (polycrystalline silicon), deposited in a trench made in the substrate, and isolated from the latter by a dielectric layer D0. This conducting trench also forms the word line WL.sub.i1,i according to an axis perpendicular to the plane of the figure.

(33) The floating gates FGe of the transistors TE.sub.i,j, TE.sub.i1,j are arranged on either side of the trench CSG, and are supported by the substrate PW through a tunnel dielectric layer D1. They are formed here by a conducting part, for example made of polysilicon, which extends up to the transistors TR.sub.i,j, TR.sub.i1,j (not shown in this section plane, cf. FIG. 4) to also form the floating gates of these transistors.

(34) The control gates CGe of the transistors TE.sub.i,j, TE.sub.i1,j extend above the floating gates through a dielectric layer D2. They are formed here by conducting strips of polysilicon that also form the control gate lines CGL.sub.i, CGL.sub.i1 according to an axis perpendicular to the plane of the figure.

(35) Doped regions n2 and n3 implanted on either side of the gate stack FG/CGe respectively form the drain (D) and source (S) regions of the transistors TE.sub.i,j, TE.sub.i1,j, the regions n3 also forming the drain regions (D) of the select transistors ST. The source regions (S) of the select transistors ST are here formed by the layer n0, the common vertical gate CSG of the select transistors extending here up to the region n0. In one alternative embodiment, the lower end of the conducting trench CSG does not reach the region n0 and a deep doped pocket is implanted between the trench and the layer n0 to form the source region of the select transistors ST.

(36) The gate stacks FG/CGe of the transistors TE.sub.i,j, TE.sub.i1,j are covered with a dielectric layer D3 over which the bit line EBL.sub.j extends. Contacts C1 pass through the layer D3 to electrically couple the bit line EBL.sub.j to the drain regions n2 (D) of the transistors TE.sub.i,j, TE.sub.i1,j. The conducting regions IS of the transistors TE.sub.i,j, TE.sub.i1,j are here doped regions n1 of the substrate which extend beneath the floating gates FG, between the drain n2 and source n3 regions of the transistors TE.sub.i,j, TE.sub.i1,j, and are thus covered with the tunnel dielectric layer D1. The dielectric layers D0, D1, D2 and D3 are for example made of silicon dioxide SiO2.

(37) FIG. 4 is a cross-section of the floating-gate transistors TR.sub.i,j, TR.sub.i1,j of the memory cells C.sub.i,j, and of their respective select transistors ST. The structure of these transistors is substantially identical to that of the transistors TE.sub.i,j, TE.sub.i1,j and will not be described again. The control gates CGe of these transistors are formed by the polysilicon parts forming the control gate lines CGL.sub.i, CGL.sub.i1 and their floating gates FG are formed by the same polysilicon parts as those which form the floating gates of the transistors TE.sub.i,j, TE.sub.i1,j (FIG. 3). Their drain regions n2 (D) are coupled by contacts C1 to the bit line RBL.sub.j which extends over the dielectric layer D3.

(38) The transistors TR.sub.i,j, TR.sub.i1,j differ from the transistors TE.sub.i,j, TE.sub.i1,j in that they do not have the conducting region IS extending beneath the floating gate FG. Thus, when these transistors are biased by an appropriate gate voltage, a conducting channel CH1 or CHF can form between the drain region n2 (D) and the source region n3 (S). A vertical conducting channel CH2 or CH2 can also form between the drain n3 (D) and source (S) regions of the select transistor ST if the common vertical gate CSG of these transistors simultaneously receives a bias voltage. More particularly, the vertical channel region CH2 of the select transistor ST of the memory cell C.sub.i,j extends opposite a first face of the embedded vertical control gate CSG, and the vertical channel region CH2 of the select transistor ST of the memory cell C.sub.i1,j extends opposite a second face of the embedded vertical control gate, and thus opposite the channel region CH2 of the select transistor of the memory cell C.sub.i,j.

(39) The transistors TR.sub.i,j, TR.sub.i1,j may also differ from the transistors TE.sub.i,j, TE.sub.i1,j by the thickness of their tunnel dielectric layer D1, which can be different from the one that extends beneath the floating gates of the transistors TE.sub.i,j, TE.sub.i1,j, this choice being offered to those skilled in the art depending on the method for programming the memory cells selected, i.e., by Fowler Nordheim effect by means of the transistors TE.sub.i,j, TE.sub.i1,j or by hot-electron injection by means of the transistors TR.sub.i,j, TR.sub.i1,j, these two options being described below.

(40) Unlike the transistors TR.sub.i,j, TR.sub.i1,j the transistors TE.sub.i,j, TE.sub.i1,j cannot have any conducting channel CH1 controlled by the voltage applied to them, due to the fact that the region extending between their drain n2 and source n3 regions is short-circuited by the doped region n1 (FIG. 3). These transistors are thus always on whatever their gate voltage, and cannot be used to read the memory cells C.sub.i,j, C.sub.i1,j. However, they can be used to erase the memory cells in conditions where no drain-source current passes through them, i.e., by Fowler Nordheim effect. They may also be used to program the memory cells in conditions where no drain-source current passes through them, i.e., also by Fowler Nordheim effect, as we will see it below.

(41) As a result, the select transistors ST associated with the transistors TE.sub.i,j, TE.sub.i1,j are not used and are present here only to streamline the manufacturing of the memory cells, in accordance with one embodiment of a manufacturing method described below. It may indeed be simpler to produce a useless transistor within a set of transistors used, when the non-production of the useless transistor would involve additional masking and photolithography steps. As, firstly, these select transistors are on when the word line to which they are connected receives a positive voltage, and as, secondly, the floating-gate transistors TE.sub.i,j, TE.sub.i1,j are always on due to their region IS, it is necessary, when designing the control units of the memory, to ensure that the corresponding bit line EBL.sub.j cannot simultaneously receive a voltage different from zero.

(42) In short, the transistor TE.sub.i,j can be used as transistor for erasing the memory cell C.sub.i,j by Fowler Nordheim effect, which involves a static programming without any programming current, whereas the transistor TR.sub.i,j can be used as transistor for reading the memory cell. Similarly, the transistor TE.sub.i1,j can be used as transistor for erasing the memory cell C.sub.i1,j by Fowler Nordheim effect and the transistor TR.sub.i1,j can be used as transistor for reading the memory cell. The bit line RBL.sub.j can be used as bit line for reading and the bit line EBL.sub.j as bit line for erasing the memory cell C.sub.i,j or the memory cell C.sub.i1,j.

(43) As regards the programming of the memory cells C.sub.i,j, C.sub.i1,j, some embodiments of the present disclosure provide two methods, between which those skilled in the art may choose, i.e., a programming method by Fowler Nordheim effect by means of the erase transistor TE.sub.i,j or TE.sub.i1,j, or a programming method by hot-electron injection by means of the read transistor TR.sub.i,j or TE.sub.i1,j.

(44) Methods for erasing, programming and reading cells of the memory array MA1 will be described below, assuming as an example that it is desirable to erase, program and read the memory cell C.sub.i,j.

(45) Erasing of a Memory Cell by Fowler Nordheim Effect Via the Erase Transistor TE.sub.i,j

(46) A method for erasing the memory cell C.sub.i,j without erasing the memory cell C.sub.i1,j, via the erase transistor TE.sub.i,j, is described in Table 1 in the Annex, which is an integral part of the description.

(47) FIGS. 5 and 6 show this erasing method. FIG. 5 is the wiring diagram in FIG. 2 in which the voltage values contained in Table 1 have been entered. FIG. 6 is a cross-section of the transistors TE.sub.i,j, TE.sub.i1,j identical to that of FIG. 3, in which the voltage values contained in Table 1 have been entered.

(48) The conducting region IS of the transistor TE.sub.i,j is taken to the positive voltage EBLV applied to the bit line EBL.sub.j, here 6V, through the contact C1 and the drain region n1 (D) of the transistor. As the control gate CGe of the transistor TE.sub.i,j is taken to the negative voltage CGV.sub.i, here 8V, a voltage difference dV equal to 14V (FIG. 6) appears between this control gate and the conducting region IS which causes electrons to be extracted from the floating gate FGe by Fowler Nordheim effect, which puts the transistor TE.sub.i,j to the erased state. As the bit line RBL.sub.j connected to the floating-gate transistor TR.sub.i,j is at high impedance, this transistor does not play any role in the process of erasing the memory cell. As the floating gate of the transistor TR.sub.i,j is however electrically coupled to that of the transistor TE.sub.i,j, the transfer of electric charges also causes the erasing of the transistor TR.sub.i,j, the entire memory cell C.sub.i,j being thus erased through the transistor TE.sub.i,j.

(49) The conducting region IS of the transistor TE.sub.i1,j of the twin memory cell is also taken to the positive voltage EBLV applied to the bit line EBL.sub.j, here 6V, through the contact C1 and the drain region n1 (D) of the transistor. As the control gate CGe of the transistor TE.sub.i1,j is taken to the positive voltage CGV.sub.i1, here 3V, a voltage difference dV equal to 3V appears between this control gate and the conducting region IS, which is insufficient to extract electrons from the floating gate of the transistor. The twin memory cell C.sub.i1,j is thus not erased.

(50) This memory array and memory cell structure thus enables individual erasing of each memory cell, i.e., erasing by bit. This possibility allows a memory erasable by bit, by word or by page to be produced indifferently without changing the general structure of the memory array or of its control units.

(51) FIG. 7 is a cross-section of two transistors TE.sub.i,j+i, TE.sub.i1,j+1 of two memory cells C.sub.i,j+i, C.sub.i1,j+1 (not represented on FIG. 2 or 5) that are contiguous to the memory cells C.sub.i,j, C.sub.i1,j. The memory cells C.sub.i,j+i, C.sub.i1,j+1 are connected to the same word line WL.sub.i1,i as the memory cells C.sub.i,j, C.sub.i1,j but are connected to a different bit line EBL.sub.j+1 that receives the default voltage EBLV*, here 0V. The transistors TE.sub.i,j+1, TE.sub.i1,j+1 have their control gates CGe connected to the same control gate lines CGL.sub.i, CGL.sub.i1,j as the transistors TE.sub.i,j, TE.sub.i1,j and thus receive the same voltages CGV.sub.i, here 8V, and CGV.sub.i1, here 3V. Thus, the voltage difference dV between the control gate CGe of the transistor TE.sub.i,j+1 and its conducting region IS is equal to 8V and this transistor undergoes an erasing stress, i.e., a low-intensity spurious erasing that could, if the transistor were in the programmed state, and after many cycles of erasing other memory cells connected to the control gate lines CGL.sub.i, CGL.sub.i1, substantially alter its threshold voltage and thus cause a corruption of its state, and thus a corruption of the data bit associated with the programmed state.

(52) Furthermore, the voltage difference dV between the control gate CGe of the transistor TE.sub.i1,j+1 and its conducting region IS is 3V and this transistor does not undergo any erasing stress, the control gate line CGL.sub.i1 being taken to only 3V. Similarly, default voltages applied to the memory cells connected to other word lines WL (not represented on the figures) do not cause any erasing stress in these memory cells.

(53) Finally, the erasing method according to the present disclosure enables not only each memory cell to be individually erased, but also limits the appearance of an erasing stress on the memory cells connected to the same control gate line, whereas various other known erasing methods, enabling only erasing by word, or otherwise by page, also cause an erasing stress on the memory cells connected to other word lines. The management of the erasing stress, by methods for refreshing the memory cells known per se, is thus simplified, given the smaller number of memory cells to be refreshed. It is possible, for example, to decide to initiate a sequence for refreshing the memory cells of a word line after N programming cycles of memory cells of this word line, by providing an erase cycle counter associated with the word line.

(54) Programming of a Memory Cell by Fowler Nordheim Effect Via the Erase Transistor TE.sub.i,j

(55) A method for programming the memory cell C.sub.i,j without programming the memory cell via the erase transistor TE.sub.i,j, is described by Table 2 in the Annex.

(56) FIGS. 8 and 9 show this programming method. FIG. 8 is the wiring diagram in FIG. 2 in which the voltage values contained in Table 2 have been entered. FIG. 9 is a cross-section of the transistors TE.sub.i,j, TE.sub.i1,j identical to that of FIG. 3, in which the voltage values contained in Table 2 have been entered.

(57) The conducting region IS of the transistor TE.sub.i,j is taken to the voltage EBLV applied to the bit line EBL.sub.j, here 0V, through the contact C1 and the drain region n1 (D) of the transistor. As the control gate CGe of the transistor TE.sub.i,j is taken to the positive voltage CGV.sub.i, here 14V, a positive voltage difference dV equal to 14V (FIG. 9) appears between this control gate and the conducting region IS which causes electrons to be injected into the floating gate FGe by Fowler Nordheim effect, which puts the transistor TE.sub.i,j to the programmed state. As the bit line RBL.sub.j connected to the floating-gate transistor TR.sub.i,j is at high impedance, this transistor does not play any role in the process of programming the memory cell. As the floating gate of the transistor TR.sub.i,j is however electrically coupled to that of the transistor TE.sub.i,j, the transfer of electric charges also causes the programming of the transistor TR.sub.i,j, the entire memory cell C.sub.i,j being thus programmed through the transistor TE.sub.i,j.

(58) The conducting region IS of the transistor TE.sub.i1,j of the twin memory cell C.sub.i1,j is taken to the voltage EBLV applied to the bit line EBL.sub.j, here 0V, through the contact C1 and the drain region n1 (D) of the transistor. As the control gate CGe of the transistor TE.sub.i1,j is taken to the positive voltage CGV.sub.i1, here 3V, a voltage difference dV equal to 3V appears between this control gate and the conducting region IS, which is insufficient to inject electrons into the floating gate of the transistor. The twin memory cell C.sub.i1,j is thus not programmed.

(59) FIG. 10 is a cross-section of the transistors TE.sub.i,j+i, TE.sub.i1,j+1 of the neighboring memory cells C.sub.i,j+1, C.sub.i1,j+1 already described in connection with FIG. 7, connected to the same word line WL.sub.i1,i as the memory cells C.sub.i,j, C.sub.i1,j but connected to the neighboring bit line EBL.sub.j+1 that receives the default voltage EBLV*, here 6V. The transistors TE.sub.i,j+1, TE.sub.i1,j+1 have their control gates CGe connected to the same control gate lines CGL.sub.i, CGL.sub.i1 as the transistors TE.sub.i,j, TE.sub.i1,j and thus receive the same voltages CGV.sub.i, here 14V, and CGV.sub.i1, here 3V. Thus, the voltage difference dV between the control gate CGe of the transistor TE.sub.i,j+1 and its conducting region IS is 8V and this transistor undergoes a programming stress, i.e., a low-intensity spurious programming.

(60) Furthermore, the voltage difference dV between the control gate CGe of the transistor TE.sub.i,j+1 and its conducting region IS is 3V and this transistor does not undergo any programming stress, the control gate line CGL.sub.i1,j being taken to only 3V. Similarly, default voltages applied to the memory cells connected to other word lines WL (not represented on the figures) do not cause any programming stress in these memory cells.

(61) Finally, this programming method, like the erasing method previously described, only causes an electrical stress to the memory cells connected to the same control gate line, the effects of which can be cancelled out by a refreshing method of the above-mentioned type.

(62) Programming of a Memory Cell by Hot-Electron Injection Via the Read Transistor TR.sub.i,j

(63) A method for programming the memory cell C.sub.i,j without programming the memory cell C.sub.i1,j, via the read transistor TR.sub.i,j, is described by Table 3 in the Annex.

(64) FIGS. 11 and 12 show this programming method. FIG. 11 is the wiring diagram in FIG. 2 in which the voltage values contained in Table 3 have been entered. FIG. 12 is a cross-section of the transistors TR.sub.i,j, TR.sub.i1,j identical to that of FIG. 4, in which the voltage values contained in Table 3 have been entered.

(65) The transistor TR.sub.i,j receives the positive voltage CGV.sub.i, here 10V, on its control gate and is in the on state, the conducting channel CH1 appearing in the substrate PW beneath the gate stack FG/CGr. The select transistor ST associated with the transistor TR.sub.i,j receives the positive select voltage SV, here 1 to 2V, on its embedded vertical gate CSG, and is in the on state, the vertical conducting channel CH2 appearing opposite the gate CSG. As the bit line RBL.sub.j is taken to the positive voltage RBLV, here 4V, and the source line SL is coupled to the ground (0V), a current circulates from the bit line to the source line through the transistor TR.sub.i,j and the corresponding select transistor ST. This current corresponds to a flow of electrons HE shown on FIG. 12, in the opposite direction to the current. This flow of electrons contains high kinetic energy electrons (hot electrons) that bypass the doped region n3 (cold region). Some of these electrons are injected into the floating gate at an injection point HI, causing the programming of the transistor TR.sub.i,j, and the programming of the erase transistor TE.sub.i,j that does not play any role in the programming process here. However, the transistor TR.sub.i1,j of the twin cell receives the voltage CGV.sub.i1,j that is equal to 0V, such that it does not undergo any spurious programming process, nor any of the other read transistors of the memory array, which receive only zero voltages.

(66) Reading of a Memory Cell Via the Read Transistor TR.sub.i,j

(67) A method for reading the memory cell C.sub.i,j via the read transistor TR.sub.i,j, is described by Table 4 in the Annex.

(68) FIGS. 13 and 14 show this reading method. FIG. 13 is the wiring diagram in FIG. 2 in which the voltage values contained in Table 4 have been entered. FIG. 14 is a cross-section of the transistors TR.sub.i,j, TR.sub.i1,j identical to that of FIG. 4, in which the voltage values contained in Table 4 have been entered.

(69) The transistor TR.sub.i,j receives the positive voltage CGV.sub.i, here 2 to 3V, that is lower than the threshold voltage of the programmed transistor but greater than the threshold voltage of the erased transistor. If the transistor TR.sub.i,j is in the erased state, i.e., if it has a threshold voltage Vt lower than the voltage CGV.sub.i, the conducting channel CH1 appears in the substrate PW, beneath the gate stack FG/CGr. The select transistor ST associated with the transistor TR.sub.i,j receives the positive select voltage SV, here 3V, on its embedded vertical gate CSG, and is in the on state, the vertical conducting channel CH2 appearing opposite the embedded gate CSG. As the bit line RBL.sub.j is taken to the positive voltage RBLV, here 1V, and the source line SL is coupled to the ground (0V), the transistor TR.sub.i,j is passed through by a read current Ir that circulates from the bit line to the source line. However, this current Ir is zero if the transistor TR.sub.i,j is in the programmed state, i.e., if it has a threshold voltage greater than the voltage CGV.sub.i. A current amplifier (not represented) connected to the bit line RBL.sub.j enables the presence or absence of the current Ir to be detected, and the erased or programmed state of the transistor TR.sub.i,j can thus be deduced, to which a logical value, 0 or 1, is allocated by convention.

(70) The transistor TR.sub.i1,j of the twin memory cell receives the negative voltage CGV.sub.i1, here 2V. This transistor, if it is in the erased state, can have a threshold voltage close to zero. The application of a negative gate control voltage ensures that it remains in the off state. Indeed, as this transistor is connected to the same bit line RBL.sub.j as the transistor TR.sub.i,j being read, rendering it conducting could corrupt the reading of the transistor TR.sub.i,j.

(71) FIGS. 15 to 22 show steps of a method for manufacturing the memory cells C.sub.i,j, C.sub.i1,j described above. FIG. 15 shows a preliminary step of forming in the substrate PW three isolating trenches STI0, ST1, ST2 of STI type (Shallow Trench Isolation) that delimit two strips of substrate S1, S2 in which the memory cells will be produced. This step is preceded by a step of implanting in the substrate the embedded layer n0 forming a source plane (not shown on the figure) or of implanting several source lines. A source plane is generally preferred to multiple source lines if it is provided to erase the memory cells by hot-electron injection.

(72) During a step shown on FIG. 16, a conducting trench is formed transversally to the strips S1, S2, by etching the substrate, depositing the dielectric layer D0 (not shown) and depositing a polysilicon layer P0 and etching the latter. The trench is intended to form both the word line WL.sub.i1,i and the embedded vertical control gate of the select transistors ST of the memory cells.

(73) During a step shown on FIG. 17, the strip of substrate S2 is doped by implanting N-type dopants, the strip of substrate S1 being masked during this operation. This step makes it possible to produce the conducting region IS that will extend beneath the floating gate of the erase transistors TE.sub.i,j, TE.sub.i1,j.

(74) During a step shown on FIG. 18, the tunnel dielectric layer D1 described above is deposited on the substrate PW, then a strip of polysilicon P1, intended to form floating gates, is deposited on the strips of substrate S1 and S2.

(75) During a step shown on FIG. 19, the dielectric layer D2 is deposited on the substrate PW, then a polysilicon layer P2 is deposited on the layer D2. The layer P2 is then etched with the layer D2 as well as with the layer P1 to form the control gate lines CGL.sub.i, CGL.sub.i1, and, beneath the latter, the common floating gates CFG, resulting from the simultaneous etching of the layer P1.

(76) During a step shown on FIG. 20, the strips of substrate S1, S2 are doped by implanting dopants self-aligned with the control gate lines CGL.sub.i, CGL.sub.i1 and with the word line WL.sub.i1,i, the strip of substrate S2 thus being doped a second time. This step generates the source S and drain D regions of the transistors TR.sub.i,j, TR.sub.i1,j, TE.sub.i,j, TE.sub.i1,j, and the drain regions of the select transistors ST.

(77) During a step shown on FIG. 21, the dielectric layer D3 is deposited on the substrate and orifices are made in the layer D3, then are metallized to form the contacts C1. Contacts C1 extend above the drain regions D of the transistors TR.sub.i,j, TR.sub.i1,j and others above the drain regions D of the transistors TE.sub.i,j, TE.sub.i1,j.

(78) During a step shown on FIG. 22, a metal layer M1 (metal 1) is deposited on the substrate, then is etched to obtain two conducting strips that form the bit lines RBL.sub.j and EBL.sub.j, the former being arranged on the contacts C1 produced above the drain regions D of the transistors TR.sub.i,j, TR.sub.i1,j and the latter arranged on the contacts produced above the drain regions D of the transistors TE.sub.i,j, TE.sub.i1,j.

(79) FIG. 23 is identical to FIG. 22 and shows the surface area occupied in width W and in length L by each memory cell C.sub.i,j, C.sub.i1,j, the assembly forming a basic brick 20 of the memory array, containing two twin dual cells, the repetition of which enables a memory array MA1 of variable size chosen according to the intended application to be designed. The contacts C1 of the memory cell C.sub.i,j are in this case shared with a memory cell adjacent to this memory cell (not represented), and the same is true concerning the contacts C1 of the memory cell C.sub.i1,j. Thus, only half of the surface area occupied by each contact C1 is considered to be part of the basic brick 20.

(80) Although these memory cells C.sub.i,j, C.sub.i1,j have a surface area that is twice those shown on FIG. 1, those skilled in the art will note that the semiconductor surface area they occupy barely differs from that occupied by conventional memory cells having planar-type select transistors that are not shared, due to the fact that the embedded vertical select gates considerably reduce their surface area and even more to the fact that they are shared.

(81) Furthermore, according to one embodiment of the disclosure, a memory array according to the present disclosure may comprise a first memory area produced from memory cells as described on FIG. 1, forming a page-erasable mass memory, and a second memory area produced from memory cells according to the present disclosure, forming a bit- or word-erasable data memory, offering a finer erasing granularity than the mass memory and more suited to certain applications.

(82) FIG. 24 is a cross-section of the memory cell C.sub.i,j according to a section plane AA shown on FIG. 23 and perpendicular to the section plane of FIGS. 3 and 4, showing together the transistors TR.sub.i,j, TE.sub.i,j and their common floating gate FGT. This figure also shows that it is possible to further reduce the width W of the memory cell by reducing the width of the central isolating trench STI0 that separates the transistors TR.sub.i,j, TE.sub.i,j, this isolating trench not needing to have the isolation width usually chosen for trenches STI1, STI2 that separate neighboring memory cells, since the transistors TR.sub.i,j, TE.sub.i,j are electrically coupled.

(83) FIG. 25 is the wiring diagram of a memory MEM1 comprising the memory array MA1 according to the present disclosure, only the cells C.sub.i,j, C.sub.i1,j being represented. The memory comprises a control circuit CCT1, a word line decoder RD1, a column decoder CD1, as many sense amplifiers SA as the number of bits of a word DTR to be read in the memory, for example an eight-bit word B0-B7, and programming latches BLT1 to apply voltages to the bit lines RBL.sub.j or EBL.sub.j according to a word DTW to be written in the memory, for example an eight-bit word B0-B7.

(84) The word line decoder RD1 controls the voltages applied to the control gate lines CGL.sub.i, CGL.sub.i1 and to the word line WL.sub.i1,i according to a most significant address A(n1)-A(x) of a word, or line address. The decoder CD1, in combination with the latches BLT1, controls the voltages applied to the bit lines RBL.sub.j, EBL.sub.j according to a least significant address A(x1)-A(0) of the word, or column address, the line and column addresses forming together the address A(n1)-A0 of a word to be read or to be written in the memory array. In read mode, the decoder CD1 couples the sense amplifiers SA to the bit lines RBL.sub.j coupled to the memory cells that must be read, and the sense amplifiers supply the word DTR.

(85) The circuit CCT1 comprises for example a central unit CPU, a voltage generator VGEN, and address and data registers. It executes read or write commands, controls the decoders, supplies the voltages for the read and write operations (erasing-programming), provides the decoders with the most significant and least significant addresses, and may execute a program for refreshing the memory cells.

(86) Although the improvement that has just been described was initially designed to be applied to a memory cell structure of the type represented in FIG. 1, it will be understood by those skilled in the art that some embodiments of this improvement may be applied to other types of memory cells.

(87) As an example, FIG. 26 represents one embodiment of this improvement applied to memory cells without any select transistor. The memory array MA1 represented comprises memory cells C.sub.i,j, C.sub.i1,j each comprising a floating-gate transistor TR.sub.i,j, respectively TR.sub.i1,j and a floating-gate transistor TE.sub.i,j, respectively TE.sub.i1,j, of the same structure as those described above. The transistor TR.sub.i,j has a drain terminal connected to the bit line RBL.sub.j, a control gate CGr connected to the word line WL.sub.i, and a source terminal directly connected to the source line SL. The transistor TE.sub.i,j comprises a drain terminal connected to the bit line EBL.sub.j, a control gate CGr connected to the word line WL.sub.i, and a non-connected source terminal. As above, the floating gate FGr of the transistor TR.sub.i,j is electrically coupled to the floating gate FGe of the transistor TE.sub.i,j and the latter comprises the conducting region IS opposite its floating gate, enabling the memory cell to be erased. The memory cell C.sub.i1,j has an identical structure and the description above applies by replacing the index i with the index i1.

(88) Other alternatives could be provided, for example by removing the source terminal of the transistors TE.sub.i,j, TE.sub.i1,j in the embodiment in FIG. 26 or in the embodiment in FIG. 2, or by removing the select transistors ST associated with the transistors TE.sub.i,j, TE.sub.i1,j in the embodiment in FIG. 2.

(89) FIG. 27 is the wiring diagram of a memory array MA2 comprising two memory cells C.sub.i,j, C.sub.i,j+1 according to a second improvement of the memory array and memory cell structure in FIG. 1, this improvement being implemented here in combination with the improvement previously described in connection with FIG. 2.

(90) The memory cells are read- and write-accessible via a first bit line RBL.sub.j, a second bit line RBL.sub.A, a third bit line EBL.sub.j,j+1, a word line WL.sub.i and two control gate lines CGL1.sub.i, CGL2.sub.i. The memory cell C.sub.i,j belongs to a physical page P.sub.i of the memory array and the memory cell belongs to an adjacent physical page P.sub.i1. The pages P.sub.i, P.sub.i1 may comprise various other memory cells and the memory array MA1 may comprise various other pages.

(91) In accordance with the previous improvement, the memory cell C.sub.i,j comprises two floating-gate transistors TR.sub.i,j, TE.sub.i,j the floating gates FGr, FGe of which are interconnected, the floating-gate transistor TR.sub.i,j being dedicated to reading the transistor memory cell and the floating-gate transistor TE.sub.i,j being dedicated to erasing the memory cell. As above, the floating gates FGr, FGe may be formed by a same conducting element CFG and each transistor TR.sub.i,j, TE.sub.i,j comprises a conducting region IS that extends opposite its floating gate through a tunnel oxide layer.

(92) The transistor TR.sub.i,j has a control gate CGr connected to the control gate line CGL1.sub.i, a drain terminal D connected to the bit line RBL.sub.j and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL. The floating-gate transistor TE.sub.i,j has a control gate CGe connected to the control gate line CGL1.sub.i, a drain terminal D connected to the bit line EBL.sub.j,j+1 and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL.

(93) The memory cell C.sub.i,j+1 has the same structure as the memory cell C.sub.i,j and comprises two floating-gate transistors TR.sub.i,j+1, TE.sub.i,j+1 the floating gates FGr, FGe of which are interconnected or formed by a same conducting element CFG. The transistor TR.sub.i,j+1 has a control gate CGr connected to the control gate line CGL2.sub.i, a drain terminal D connected to the bit line RBL.sub.j+1 and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL. The floating-gate transistor TE.sub.i,j+1 has a control gate CGe connected to the control gate line CGL1.sub.i, a drain terminal D connected to the bit line EBL.sub.j,j+1 and a source terminal S connected to the drain terminal D of a select transistor ST the source terminal S of which is coupled to a source line SL.

(94) The select transistors ST associated with the floating-gate transistors TR.sub.i,j, TR.sub.i,j+1 have a common embedded vertical control gate CSG. Similarly, the select transistors ST associated with the floating-gate transistors TE.sub.i,j, TE.sub.i,j+1 have a common embedded vertical control gate CSG.

(95) The memory array MA2 thus differs from the memory array MA1 in FIG. 2 in that the transistors TR.sub.i,j, TR.sub.i,j+1 of the twin memory cells C.sub.i,j, C.sub.i,j+1 are connected to different bit lines RBL.sub.j, RBL.sub.j+1. As will be seen below, these two bit lines enable a method for reading the memory cells to be implemented that does not require, when reading a memory cell, a negative voltage to be applied to the control gate line CGL1.sub.i or CGL2.sub.i of the twin memory cell.

(96) It will first be noted that adding an extra bit line in a structure of two twin memory cells as represented in FIG. 1, involves increasing the surface area of the pair of memory cells, considered as basic brick of a memory array, because the latter does not enable two bit lines to be received. On the other hand, a structure of two twin dual memory cells of the type represented in FIG. 2 enables the two bit lines RBL.sub.j, RBL.sub.j+1 dedicated to reading the memory cells to be provided in addition to the bit line EBL.sub.j,j+1 dedicated to erasing the memory cells, without increasing their surface area. This will be shown in connection with FIGS. 28 to 32, that show an alternative of the manufacturing method previously described for manufacturing a pair of memory cells forming a basic brick of the memory array, this alternative making it possible to produce the two bit lines RBL.sub.j, RBL.sub.j+1 instead of the bit line RBL.sub.j without increasing the surface area of the pair of memory cells.

(97) The initial steps of the manufacturing method, described above in connection with FIGS. 15 to 21, are not modified. The step in FIG. 22 of manufacturing the bit lines RBL.sub.j, EBL.sub.j, is replaced with the step shown on FIG. 28.

(98) During the step in FIG. 28, a metal layer M1 (metal 1) is deposited on the substrate, then etched to obtain firstly a conducting strip that forms here the bit line EBL.sub.j,j+1 (previously referred to as EBL.sub.j) and secondly two conducting rectangles parallel to the bit line EBL.sub.j,j+1, that form two bit line sections P1(RBL.sub.j), P1(RBL.sub.j+1). These two bit line sections extend above the contacts C1 that have been produced above the drain regions D of the transistors TR.sub.i,j, TR.sub.i,j+1 during the step shown on FIG. 21.

(99) During a step shown on FIG. 29, a dielectric layer D4 is deposited on the substrate, and orifices are made in the layer D4 above the bit line sections P1(RBL.sub.j), P1(RBL.sub.+1), and are then metallized to form the contacts C2.

(100) During a step shown on FIG. 30, a metal layer M2 (metal 2) is deposited on the substrate, then etched to obtain two other conducting rectangles forming two bit line sections P2(RBL.sub.j), P2(RBL.sub.j+1) perpendicular to the sections P1(RBL.sub.j), P1(RBL.sub.j+1) and which extend above the contacts C2.

(101) During a step shown on FIG. 31, a dielectric layer D5 is deposited on the substrate, and orifices are made in the layer D5 above the bit line sections P2(RBL.sub.j), P2(RBL.sub.j+1), and are then metallized to form the contacts C3.

(102) During a step shown on FIG. 32, a metal layer M3 (metal 3) is deposited on the substrate, then etched to obtain two conducting strips that form the bit lines RBL.sub.j and RBL.sub.j+1, the former being arranged on the contacts C3 coupled to the drain region D of the transistor TR.sub.i,j, and the latter arranged on the contacts C3 coupled to the drain region D of the transistor TR.sub.i,j+1. As shown in FIG. 32, the bit lines RBL.sub.j and RBL.sub.j+1 are parallel to the bit line EBL.sub.j,j+1, that is situated two metal levels below them, and the assembly fits into the template of the cells C.sub.i,j, C.sub.i,j+1 without requiring any increase in their surface area.

(103) The memory cells are programmed and erased as described above. They are, however, read through the bit lines RBL.sub.j, RBL.sub.j+1 in a manner that is going to be described.

(104) Reading of a Memory Cell Via a Bit Line RBL.sub.j or RBL.sub.j+1

(105) A method for reading the memory cell C.sub.i,j in FIG. 27 via the read transistor TR.sub.i,j and the bit line RBL.sub.j is described by Table 5 in the Annex.

(106) FIG. 33 is a wiring diagram identical to that in FIG. 27 in which the voltage values contained in Table 5 have been entered. The transistor TR.sub.i,j receives on its control gate the positive voltage CGV1.sub.i, here 2 to 3V, and becomes on if it is in the erased state. The select transistor ST associated with the transistor TR.sub.i,j receives the positive select voltage SV on its control gate, here 3V, and is in the on state. As the bit line RBL.sub.j is taken to the positive voltage RBLV.sub.j, here 1V, and the source line SL is coupled to the ground (0V), the transistor TR.sub.i,j is passed through by a read current Ir that circulates from the bit line to the source line. The transistor TR.sub.i,j+1 of the twin memory cell receives the zero voltage CGV2.sub.i. This transistor, if it is in the erased state, can have a threshold voltage close to zero, or even negative, and switch to the on state. Indeed, the bit line RBL.sub.j+1 is not connected to any sense amplifier during the reading of the transistor TR.sub.i,j and the transistor TR.sub.i,j+1 is not read. Thus, even in the absence of a negative voltage on the control gate line CGL2.sub.i, the transistor TR.sub.i,j+1 cannot corrupt the reading of the transistor TR.sub.i,j, and vice-versa when reading the transistor TR.sub.i,j+1.

(107) FIG. 34 is the wiring diagram of a memory MEM2 comprising a memory array MA2 according to the present disclosure, only the cells C.sub.i,j, C.sub.i,j+1 being represented. The memory comprises a control circuit CCT2, a word line decoder RD2, a column decoder CD2, sense amplifiers SA and programming latches BLT2.

(108) The word line decoder RD2 controls the voltages applied to the control gate lines CGL1.sub.i, CGL2.sub.i and to the word line WL.sub.i according to a most significant address A(n1)-A(x) of a word (line address). The decoder CD2, in combination with the latches BLT1, controls the voltages applied to the bit lines RBL.sub.j, RBL.sub.j+1, EBL.sub.j,j+1 according to the column address A(x1)-A(0) of the word. In read mode, the decoder CD2 couples the sense amplifiers SA to the bit lines RBL.sub.j connected to the memory cells that must be read, and the sense amplifiers supply a word DTR read in the memory, for example of 8 bits B0-B7. The circuit CCT2 comprises, like the circuit CCT1 previously described, a central unit CPU, a voltage generator VGEN, and address and data registers. It executes read or write commands, controls the decoders, supplies the voltages for the read and write operations (erasing-programming), provides the most significant and least significant addresses, and may execute a program for refreshing the memory cells.

(109) According to one embodiment, the word line decoder RD2 is configured to be able to distinctly control the voltages applied to the twin control gate lines CGL1.sub.i, CGL2.sub.i, which here have the same most significant address A(n1)-A(x). This distinct control of the voltages can be reserved for the erasing operations, to apply a positive voltage to these memory cells situated on a twin page of the one containing the memory cell(s) being erased (Cf FIGS. 6 and 7). However, in read mode, the decoder may apply the same voltage to the twin control gate lines CGL1.sub.i, CGL2.sub.i or even to all the control gate lines of the memory array to limit the logic gate switches and thus limit the current consumption of the memory, because the memory cells are read-selected by means of the word lines WL.

(110) In such an embodiment, the decoder RD2 receives, in addition to the most significant address A(n1)-A(x) of a word, the least significant bit A(0) of the least significant address A(x1)-A(0) of the word. The decoder RD2 also receives from the circuit CCT2 an information signal EPR that indicates to it whether the address decoding to be done occurs in the context of reading, erasing or programming memory cells. If the decoding occurs in the context of erasing, the decoder RD2 differentiates the two control gate lines CGL1.sub.i, CGL2.sub.i according to the bit A(0). In other words, the decoder RD2 selects the control gate line CGL1.sub.i if the bit line RBL.sub.j is designated by the full address received by the memory, or selects the control gate line CGL2.sub.i if the bit line RBL.sub.j+1 is designated by the full address received by the memory. In one equivalent alternative, the decoder may receive a signal from the column decoder CD2, indicating to it which of the two control gate lines must be selected. Those skilled in the art may naturally provide other embodiments of the decoder, aiming for example to distinctly control the voltages applied to the twin control gate lines CGL1.sub.i, CGL2.sub.i in reading, programming and erasing mode.

(111) Although the second improvement that has just been described was initially designed to be applied to a memory cell structure according to the first improvement, as shown on FIG. 2, it will be understood by those skilled in the art that some embodiments of this second improvement may be applied to other types of memory cells.

(112) As an example, FIG. 35 shows an example of application of the second improvement to the memory cell structure represented in FIG. 1, and shows a memory array MAT comprising four memory cells D.sub.i,j, D.sub.i,j+1, D.sub.i,j+1, D.sub.i,j+3 of the same structure and the same arrangement as the cells M.sub.i,j, M.sub.i1,j, M.sub.i,j+1, M.sub.i1,j+1 in FIG. 1, but considered as being part of the same logic page, i.e., having the same most significant address. The memory cells D.sub.i,j, D.sub.i,j+1 are thus twin memory cells and share the same select gate CSG. The memory cells D.sub.i,j+2, D.sub.i,j+3 are twin memory cells and share the same select gate CSG. The control gates of the floating-gate transistors T.sub.i,j, T.sub.i,j+2 of the memory cells D.sub.i,j, D.sub.i,j+2 are connected to the control gate line CGL1.sub.i and the control gates of the floating-gate transistors T.sub.i,j+1, T.sub.i,j+3 of the memory cells D.sub.i,j+1, D.sub.i,j+3 are connected to the control gate line CGL2.sub.i. The drain terminals of the twin memory cells D.sub.i,j, D.sub.i j+1, instead of being connected to the same bit line, are connected to different bit lines BL.sub.j, BL.sub.j+1. Similarly, the drain terminals of the twin memory cells D.sub.i,j+2, D.sub.i,j+3, instead of being connected to the same bit line, are connected to different bit lines BL.sub.j+2, BL.sub.j+3.

Annex

(113) TABLE-US-00001 TABLE 1 Fowler Nordheim erasing of C.sub.i, j via TE.sub.i, j, FIGS. 5 and 6 Ref. Description Sign Example CGV.sub.i Erase voltage applied to the control gate CGL.sub.i of negative 8 V the transistors TR.sub.i, j, TE.sub.i, j of the memory cell C.sub.i, j (erase-selected memory cell) via the control gate line CGL.sub.i CGV.sub.i1 Erase-inhibit voltage applied to the control gate positive 3 V CGL.sub.i1 of the transistors TR.sub.i1, j, TE.sub.i1, j of the memory cell C.sub.i1, j (twin memory cell not erase- selected) via the control gate line CGL.sub.i EBLV Erase voltage applied to the bit line EBL.sub.j positive 6 V RBLV Voltage applied to the bit line RBL.sub.j HZ* SV Select voltage applied to the word line WL.sub.i1, j 0 V common to the twin memory cells C.sub.i1, j, C.sub.i, j SPV Source line voltage applied to all the source lines 0 V SL (or to the source plane) VB Electric potential of the substrate PW 0 V CGV* Default voltage applied to all the other control gate positive 3 V lines CGL EBLV* Default voltage applied to the non-selected bit lines 0 V EBL RBLV* Default voltage applied to a non-selected bit line 0 V RBL (for example RBL.sub.j+1) SV* Voltage applied to the non-selected word lines WL 0 V *High impedance, i.e., line disconnected from the rest of the circuit

(114) TABLE-US-00002 TABLE 2 Fowler Nordheim programming of C.sub.i, j via TE.sub.i, j, FIGS. 8 and 9 Ref. Description Sign Example CGV.sub.i Voltage applied to the control gate CGL.sub.i of the positive 14 V transistors TR.sub.i, j, TE.sub.i, j of the memory cell C.sub.i, j (program-selected memory cell) via the control gate line CGL.sub.i CGV.sub.i1 Voltage applied to the control gate CGL.sub.i1 of the positive 3 V transistors TR.sub.i1, j, TE.sub.i1, j of the memory cell C.sub.i1, j (twin memory cell not program-selected) via the control gate line CGL.sub.i EBLV Voltage applied to the bit line EBL.sub.j 0 V RBLV Voltage applied to the bit line RBL.sub.j HZ SV Select voltage applied to the word line WL.sub.i1, i 0 V common to the twin memory cells C.sub.i1, j, C.sub.i, j SPV Source line voltage applied to all the source lines 0 V SL (or to the source plane) VB Electric potential of the substrate PW 0 V CGV* Voltage applied to all the other control gate lines positive 3 V CGL EBLV* Voltage applied to the non-selected bit lines EBL 6 V RBLV* Voltage applied to the non-selected bit lines RBL HZ SV* Voltage applied to the non-selected word lines WL 0 V

(115) TABLE-US-00003 TABLE 3 Programming of C.sub.i, j by injection, via TR.sub.i, j, FIGS. 11 and 12 Ref. Description Sign Example CGV.sub.i Voltage applied to the control gate CGL.sub.i of the positive 10 V transistors TR.sub.i, j, TE.sub.i, j of the memory cell C.sub.i, j (program-selected memory cell) via the control gate line CGL.sub.i CGV.sub.i1 Voltage applied to the control gate CGL.sub.i1 of the 0 V transistors TR.sub.i1, j, TE.sub.i1, j of the memory cell C.sub.i1, j (twin memory cell not program-selected) via the control gate line CGL.sub.i EBLV Voltage applied to the bit line EBL.sub.j 0 V or more RBLV Voltage applied to the bit line RBL.sub.j positive 4 V SV Select voltage applied to the word line WL.sub.i1, i positive 1-2 V common to the twin memory cells C.sub.i1, j, C.sub.i, j SPV Source line voltage applied to all the source lines 0 V SL (or to the source plane) VB Electric potential of the substrate PW 0 V CGV* Voltage applied to all the other control gate lines 0 V CGL EBLV* Voltage applied to the non-selected bit lines EBL 0 V RBLV* Voltage applied to the non-selected bit lines RBL 0 V SV* Voltage applied to the non-selected word lines WL 0 V

(116) TABLE-US-00004 TABLE 4 Reading of C.sub.i, j via TR.sub.i, j, FIG. 13 and 14 Ref. Description Sign Example CGV.sub.i Voltage applied to the control gate CGL.sub.i of the positive 2-3 V transistors TR.sub.i, j, TE.sub.i, j of the memory cell C.sub.i, j (read- selected memory cell) via the control gate line CGL.sub.i CGV.sub.i1 Voltage applied to the control gate CGL.sub.i1 of the negative 2 V transistors TR.sub.i1, j, TE.sub.i1, j of the memory cell C.sub.i1, j (twin memory cell not read-selected) via the control gate line CGL.sub.i EBLV Voltage applied to the bit line EBL.sub.j 0 V RBLV Voltage applied to the bit line RBL.sub.j positive 1 V SV Select voltage applied to the word line WL.sub.i1, i positive 3 V common to the twin memory cells C.sub.i1, j, C.sub.i, j SPV Source line voltage applied to all the source lines SL 0 V (or to the source plane) VB Electric potential of the substrate PW 0 V CGV* Voltage applied to all the other control gate lines 0 V CGL EBLV* Voltage applied to the non-selected bit lines EBL 0 V RBLV* Voltage applied to the non-selected bit lines RBL 0 V SV* Voltage applied to the non-selected word lines WL 0 V

(117) TABLE-US-00005 TABLE 5 Reading of C.sub.i, j via TR.sub.i, j and RBL.sub.j, FIG. 33 Ref. Description Sign Example CGV1.sub.i Voltage applied to the control gate CGL1.sub.i of the positive 2-3 V transistors TR.sub.i, j, TE.sub.i, j of the memory cell C.sub.i, j (read- selected memory cell) via the control gate line CGL1.sub.i CGV2.sub.i Voltage applied to the control gate CGL2.sub.i of the 0 V transistors TR.sub.i, j+1, TE.sub.i, j+1 of the memory cell C.sub.i, j+1 (twin memory cell not read-selected) via the control gate line CGL2.sub.i EBLV Voltage applied to the bit line EBL.sub.j, j+1 0 V RBLV.sub.j Voltage applied to the selected bit line RBL.sub.j of the positive 1 V pair of memory cells RBLV.sub.j+1 Voltage applied to the non-selected bit line RBL.sub.j+1 0 V of the pair of memory cells SV Select voltage applied to the word line WL.sub.i positive 3 V common to the twin memory cells C.sub.i, j+1, C.sub.i, j SPV Source line voltage applied to all the source lines 0 V SL (or to the source plane) VB Electric potential of the substrate PW 0 V CGV* Voltage applied to all the other control gate lines 0 V CGL EBLV* Voltage applied to the non-selected bit lines EBL 0 V RBLV* Voltage applied to the non-selected bit lines RBL 0 V SV* Voltage applied to the non-selected word lines WL 0 V

(118) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.