Abstract
A polynucleotide sequencer comprising an integrated and multiplexed network of patch clamp capacitive integrator-differentiator amplifiers with small feedback capacitors using pseudo-resistors.
Claims
1. A patch clamp amplifier, comprising: an integrating operational amplifier having a first inverting input for receiving current from a nanopore sensor, said integrating operational amplifier further having a first non-inverting input and a first output; a feedback capacitor connecting said first output to said first inverting input; a feedback impedance in parallel with said feedback capacitor; a differentiator operational amplifier having a second inverting input, a second non-inverting input, and a second output; a first input capacitor connecting said second inverting input to said first output; a first input impedance in parallel with said first input capacitor; a second input capacitor connecting said second non-inverting input to said first non-inverting input; a second input impedance in parallel with said second input capacitor; a first resistor connecting said second output to said second inverting input; and a second resistor connecting said second non-inverting input to ground; wherein said feedback impedance is provided by a pseudo-resistor or an on-chip poly resistor.
2. The patch clamp amplifier of claim 1, wherein said first input capacitor and said second input capacitor have the same capacitance.
3. The patch clamp amplifier of claim 1, wherein said first non-inverting input of said integrating amplifier receives a command voltage.
4. The patch clamp amplifier of claim 1, wherein said patch clamp amplifier is a transimpedance amplifier.
5. The patch clamp amplifier of claim 4, wherein said transimpedance amplifier is a capacitive feedback transimpedance amplifier configured as an integrator-differentiator, wherein a first stage (AMP1, C.sub.F, Z.sub.1) is an integrator and a second stage (AMP2, C.sub.1, R.sub.2, Z.sub.2) is a differentiator, and wherein Z.sub.1 and Z.sub.2 are high impedance paths configured to set DC bias.
6. The patch clamp amplifier of claim 5 wherein each of Z.sub.1 and Z.sub.2 is an on-chip poly resistor.
7. The patch clamp amplifier of claim 6 wherein both the length and the width of the on-chip poly resistor is between 1m to 10m.
8. The patch clamp amplifier of claim 5 wherein Z.sub.1 and Z.sub.2 each has an impedance in the order of tens of M or G.
9. The patch clamp amplifier of claim 5 wherein each of Z.sub.1 and Z.sub.2 is a pseudo resistor.
10. The patch clamp amplifier of claim 9 wherein each of Z.sub.1 and Z.sub.2 comprises a linear resistance comprising an NMOS or PMOS transistor.
11. The patch clamp amplifier of claim 8 wherein Z.sub.1 and Z.sub.2 each has an impedance in the order of tens of M or G wherefore the patch clamp amplifier's total gain may be calculated as thereby enabling the patch clamp amplifier to achieve a wide bandwidth.
12. The patch clamp amplifier of claim 1 wherein said feedback impedance is provided by an on-chip poly resistor.
13. The patch clamp amplifier of claim 1 wherein said feedback impedance is provided by a pseudo resistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The advantages and features of the present invention will become better understood with reference to the following detailed description and claims when taken in conjunction with the accompanying drawings, in which like elements are identified with like symbols, and in which:
(2) FIG. 1 illustrates exemplified components of a nucleotide sequencer;
(3) FIG. 2 presents a process performed by the nucleotide sequencer to sequence nucleotides;
(4) FIG. 3 illustrates an example of a measuring device of the nucleotide sequence, wherein the measuring device uses a nanopore technique;
(5) FIG. 4 presents a process that may be implemented by the measuring device to measure ionic current caused by the movement of the nucleotide;
(6) FIG. 5 illustrates a schematic depiction of a resistive feedback amplifier;
(7) FIG. 6 illustrates a capacitive feedback amplifier that incorporate an integrator-differentiator configuration;
(8) FIG. 7 presents a process that may be performed by the amplifying device to amplify the ionic current received from the measuring device using the capacitive feedback amplifier in the integrator-differentiator configuration;
(9) FIG. 8 presents a process that may be performed by the amplifying device to amplify the ionic current received from the measuring device using the capacitive feedback amplifier in the integrator-differentiator configuration and a multiplexer;
(10) FIG. 9 illustrates a multiplexing network suitable for multi-nanopore sensing based on the capacitive feedback amplifier shown in FIG. 6;
(11) FIG. 10 presents a top-down view of a semiconductor chip that incorporates the multiplexing network shown in FIG. 9;
(12) FIG. 11 illustrates a cross-sectional view of a typical pad, ESD network, and amplifier;
(13) FIG. 12 illustrates a cross-sectional structure of a pad, ESD network, and amplifier for use in the semiconductor chip shown in FIG. 4;
(14) FIG. 13 presents a board-level configuration for multi-nanopore sensing using a multiplexing patch-clamp network chip as shown in FIG. 4;
(15) FIG. 14 presents a process that may be performed by the amplifying device to amplify the ionic current received from the measuring device using the resistive feedback amplifier in the integrator-differentiator configuration and a multiplexer; and
(16) FIG. 15 illustrates a multiplexing multi-nanopore sensing using resistive-feedback transimpedance patch clamp amplifiers.
DETAILED DESCRIPTION
(17) The presently disclosed subject matter now will be described more fully hereinafter with reference to the accompanying drawings in which one embodiment is shown. However, it should be understood that this invention may take many different forms and thus should not be construed as being limited to the embodiment set forth herein.
(18) All documents and references referred to in this disclosure are hereby incorporated by reference for all purposes. In the figures like numbers refer to like elements throughout. Additionally, the terms a and an herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.
(19) International application Dual Pore Device (WO 2013/012881) is hereby incorporated by reference in its entirety for all purposes. Additionally, the terms a and an herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.
(20) Several embodiments of the nucleotide sequencer are described herein with reference to FIGS. 1 to 15. These embodiments of the nucleotide sequencer provide space-efficient, high throughput amplifiers suitable to be implemented on a high density semiconductor die. The high-density semiconductor die may be suitable for use on a circuit board having an array of nanopore sensors. For example, these embodiments of the nucleotide sequencer are suitable to be implemented as a patch clamp.
(21) As shown in FIG. 1, various embodiments of the nucleotide sequencer 100 include a measuring device 101, an amplifying device 102, and an analyzing device 103. In some embodiments, the measuring device 101 manipulates a molecule as described below. The measuring device 101 may measure the ionic current produced by the molecule sample 104. The amplifying device 102 amplifies the ionic current measured by the measuring device 101 and outputs voltage signals that are representative of the ionic current measured. The analyzing device 103 may perform analysis on the voltage signals, and displays results of the analysis 105.
(22) FIG. 2 illustrates a process 200 that may be preformed by a nucleotide sequencer to sequence a nucleotide. In step 201, the nucleotide sequencer begins by loading a sample molecule into a measuring device. In one embodiment of the nucleotide sequencer, the measuring device comprises a nanopore or an array of nanopores. Examples of the molecule include but not limited to: a double-stranded DNA, single stranded DNA, double-stranded RNA, single-stranded RNA, or DNA-RNA hybrid. In step 202, a first voltage and a second voltage is applied to the measuring device. In step 203, the voltages applied to the measuring device cause the molecule to move through the measuring device due to an electromagnetic field generated. Next, in step 204, the nanopore or nanopore array measures the ionic current generated by the movement of the molecule as it passes the nanopores. In step 205, the amplifying device of the nucleotide sequencer amplifies the measured ionic current and outputs a voltage value that is representative of the measured ionic current in step 206. Lastly, the amplifying device may send the data that represents the measured currents to a computing device for analysis in step 207. In one embodiment, the computing device sequences the nucleotides based on the data that is received from the amplifying device.
(23) FIG. 3 shows an example of a measuring device 300. The measuring device comprises an upper chamber 301, a middle chamber 302, and a lower chamber 303. The upper chamber is connected to the middle chamber through a nanopore 309, and the middle chamber 302 is connected to the lower chamber 303 through another nanopore 310. The upper 301 and the lower chambers 302 and 303 are configured to have voltages 304 and 306 applied to them. In some embodiments, a patch clamp or a voltage clamp applies voltages 304 and 306 to the upper and the lower chambers 301 and 303. The middle chamber is grounded 305 with respect to both the upper and the lower chamber 301 and 303. The applied voltages 304 and 306 generate forces 307 and 308, and molecules 311 and 312 move in response to the attraction of the forces.
(24) FIG. 4 represents a process 400 through which the measuring device of the nucleotide sequencer takes to measure and output the ionic current caused by the molecule. In step 401, the sample molecule is loaded into the upper chamber of the device. In step 402, a voltage is applied between the upper chamber and the middle chamber. In step 403, another voltage is applied between the lower chamber and the middle chamber. In some embodiments, the voltage applied to the lower chamber and the upper chamber is of a different magnitude. In some embodiments, the voltage of the lower chamber is higher than the voltage of the upper chamber. In other embodiments, the voltage of the upper chamber is higher than the voltage of the lower chamber. In various embodiments, the voltage of one chamber (e.g. upper or lower) is twice the voltage of the other chamber (e.g. upper or lower). In various embodiments, the voltage may be less than twice. In various embodiments, the upper or lower chambers may be both positively charged. In various embodiments, the upper or the lower chambers may be both negatively charged. The voltages can be reset in order to bring out desired pattern of movement of the molecules or calibrated based on a known sample results. As the molecule passes the pores in steps 404 and 405, ionic current measurements are taken in step 406. In one embodiment, a patch clamp sets the voltages and measures the ionic current. In another embodiment, a voltage clamp sets the voltages and measures the ionic current. Lastly, in step 407, the measuring device passes data collected to an amplifying device for amplifying.
(25) Several embodiments are directed to reducing the size of the elements of the amplifying device to enable high-throughput multi-nanopore sensing. Reducing the size of the elements of the amplifying device enables more elements to be placed on a die. For example, a die may have a dimension of 100 m100 m; however, the specific dimensions provided are not meant to be limiting and implementations need not have equal size dimensions.
(26) In one embodiment of the nucleotide sequencer, a capacitive feedback transimpedance amplifier is used. FIG. 6 shows an example of such an amplifier 600. The amplifier 600 includes a feedback capacitor C.sub.F 607 in a parallel configuration with a high impendence Z.sub.1 617 between an inverting input 605 and an output 609 of an Op Amp 601. The output 609 of the Op Amp 601 is applied to the inverting input 612 of Op Amp 602 via balancing components comprised of a capacitor C.sub.1 608 and shunting high impedance Z.sub.2 618. Capacitor C.sub.1 608 and the shunting high impedance Z.sub.2 618 are parallel to one another. The non-inverting input 613 of Op Amp 602 is connected to the non-inverting input 606 of Op Amp 601 by a capacitor C.sub.1 611 and shunting high impedance Z.sub.2 619 (the same as applied to the inverting input). An output 614 of Op Amp 602 is connected to the inverting input 612 of Op Amp 602 with a resistor R.sub.2 610. In addition, a ground contact resistance R.sub.2 615 is connected to the non-inverting input 613 of Op Amp 602. A command voltage V.sub.CMD 604 is applied to the non-inverting input 605 of Op Amp 601. An ionic current 603 measured by a nanopore sensor is applied to the inverting input 605 of Op Amp 601.
(27) The capacitive feedback transimpedance amplifier in FIG. 6 is implemented in an integrator-differentiator configuration. The integrating portion of the amplifier includes the Op Amp 28, the feedback capacitor C.sub.F 24, and the shunting impedance Z.sub.1 26. The differentiating portion of the amplifier includes the Op Amp 36, the capacitor C.sub.1 30, the impedance Z.sub.2 32, and the resistor R.sub.2 34 is the differentiator. Here, Z.sub.1 26 and Z.sub.2 32 are high impedance paths used to set DC bias. The gain of the integrator-differentiator amplifier is:
(28)
(29) In one embodiment, the amplifier is implemented with impedances Z.sub.1 and Z.sub.2 that have large impedance (for example, if Z.sub.1 and Z.sub.2 each has an impedance of 10M, then each of 1/Z.sub.1 and 1/Z.sub.2 is 0.0000001, which is negligible in most cases; however, Z.sub.1 and Z.sub.2 need not to be in that order of magnitude to realize the present embodiment) then the values of 1/Z.sub.1 and 1/Z.sub.2 approach close to zero. Therefore, the gain of the amplifier becomes:
(30)
(31) The above equation shows that the pole in the denominator and the zero in the numerator cancel. This enables the amplifier of FIG. 4 to achieve a wide bandwidth.
(32) In one example, on-chip poly resistors (with resistance in the order of tens of M or G) can be used to realize the high impedance of Z.sub.1 617 and Z.sub.2 618. In various embodiments, on-chip poly resistors may be a plurality resistors formed on the semiconductor die, and they may be used to implement high impedance. The length and width of an on-chip poly resistor is approximately in the 1 m to 10 m orders of magnitude. In another examples, reset switches are used in place of Z.sub.1 617 and Z.sub.2 618. If reset switches are used, then means to reduce glitch noises from periodic resetting of the reset switches should be used. In yet another example, pseudo resistors are used to realize high impedance for Z.sub.1 617 and Z.sub.2 618. Pseudo resistors are linear resistances employing NMOS or PMOS transistor in a linear region for the purposes of setting DC paths and reducing the amplifier size. See, for example, R. R. Harrison and C. Charles, A low-power low-noise CMOS amplifier for neural recording applications, IEEE Journal of Solid-State Circuits, 38: 958-965, June 2003 and G. Ferrari, F. Gozzini, A. Molari and M. Sampietro, Transimpedance amplifier for high sensitivity current measurements on nanodevices, IEEE J. of Solid-State Circuits, vol. 44, no. 5, pp. 1609-1616, May 2009.
(33) The input-referred noise current of the capacitive feedback transimpedance amplifier 600 shown in FIG. 6 is directly proportional to C.sub.F. (See., B. Sakmann and E. Neher, Single-channel recording, Plenum Press, New York, 1995.) Reducing C.sub.F 607 can not only minimize the integrator area (the headstage) but also achieves a desired low input-referred noise current. Embodiments of the nucleotide sequencer overcome the noise problem caused by resistive feedback transimpedance amplifiers shown in FIG. 5.
(34) In one embodiment, the amplifying unit of the nucleotide sequencer uses the capacitive feedback transimpedance amplifier with the integrator-differentiator configuration to amplifying the measured ionic current outputted from the measuring device. FIG. 7 represents a process 700 that amplify the measured ionic current using the amplifying device. In step 701, the integrating portion of the capacitive feedback transimpedance amplifier receives an output ionic current from the measuring device. The measuring device could include an array of nanopore sensors. Then, in step 702, the output from the integrating portion is sent to the differentiating portion of the capacitive feedback transimpedance amplifier. In one approach, an individual differentiating portion is connected to an individual integrating portion. In another approach, multiple integrating portions are connected to one differentiating portion through the use of a multiplexer as discussed below. Given that the amplifier comprises of a transimpedance feedback, the resulting signal is a voltage value instead of a current value. In step 703, the output(s) from the differentiating portion(s) are buffered. In step 704, a digital to analog converter (ADC) converts the analog signal of the buffered output from the differentiating portion of the capacitive feedback transimpedance amplifier to digital signals. In step 705, the digital signal is related to a computing device for analysis. The computing device can be any device with a process. Examples of the computing device include, but not limited to, a smart phone, tablet, personal computer, and laptop. The digital signal can be related to the computing device through a universal serial bus (USB) module, a wireless network, or any other wireless or wireless connection.
(35) In one embodiment, a multiplexer is used to connect a plurality integrating portions of the capacitive feedback transimpedance amplifier to one differentiating portion. In one embodiment, the multiplexer is an analog time division multiplexer. FIG. 8 represents a process 800 that the amplifying device with a multiplexer implementation takes to amplify the ionic current. In step 801, the integrating portion of the capacitive feedback transimpedance amplifier receives an output ionic current from the measuring device. The measuring device could include an array of nanopore sensors. Then, in step 802, the outputs or output signals from the integrating portions are sent to a multiplexer. In step 803, the multiplexer arranges the outputs from the integrating portions so that the multiplexer will send one output at a time to the differentiating portion every clock cycle. Given that the amplifier comprises of a transimpedance feedback, the resulting signal is a voltage value instead of a current value. In step 804, a voltage value is output from the differentiating portion. In step 805, the outputs from the differentiating portion are buffered. In step 806, a digital to analog converter (ADC) converts the analog signal of the buffered output from the differentiating portion of the capacitive feedback transimpedance amplifier to digital signals. In step 807, the digital signal is related to a computing device for analysis. The computing device can be any device with a process. Examples of the computing device include, but not limited to, a smart phone, tablet, personal computer, and laptop. The digital signal can be related to the computing device through a universal serial bus (USB) module, a wireless network, or any other wireless or wireless connection.
(36) FIG. 9 illustrates an N-integrator capacitive feedback multiplexed configuration based on capacitive feedback transimpedance amplifier with the integrator-differentiator configuration 900. In this example, each of N-number of nanopore sensors 903 are connected to an inverting input 906 of each of N-number of integrating portions 904. An analog multiplexer 901 receives the outputs 908 of each of the N-number of integrating portions 904. Each integrating portions 904 includes a feedback capacitor C.sub.F 905 and a high impedance Z.sub.1 905. In various embodiments each nanopore sensor 903 shares a ground of the analog multiplexer 901, but reference may be made to the ground line 1306 of FIG. 13. Each nanopore 903 cis chamber is connected to one and only one integrating portion 904 while all trans chambers and the analog multiplexer 901 share the same ground.
(37) Still referring to FIG. 9, all integrating portions 904 are turned on when a command voltage (VCMD) is provided on a DC biasing line 919 from a Multiplexing, Sampling Clock Generator, and Command voltage biasing block 902 (hereinafter M-SC-CV block 90). As discussed above, C.sub.F 905 has a capacitance in the picoFarad range to increase the gain while decreasing noise.
(38) Also in FIG. 9, the analog multiplexer 901 selects one of the outputs of the integrating portion 908 and connects that selected output to a capacitor 913 which in turn connects to the inverting input 909. The analog multiplexer applies the selected output to a differentiating portion comprising of a capacitor 913, a differentiator Op Amp 910, and a feedback resistor R.sub.2 912. The non-inverting input 922 of the differentiator Op Amp 910 is grounded 923. The output 924 of the differentiating portion 910 is applied to the non-inverting input 915 of a unity gain buffer Op Amp 911. The output of the buffer Op Amp 911 is applied to an analog to digital converter (ADC) 916 whose output 914 is made available via a USB interfacing module or a wireless module 917.
(39) The differentiating portion 910 processes the outputs 908 of all N-number integrating portions 904 via the analog multiplexer 901. The selected analog multiplexer 901 channel is controlled by signals applied on buss 919 by the M-SC-CV block 902. The analog multiplexer 901 is controlled in accord with a system clock 918 of the M-SC-CV block 902, which is made available on a pad. Only one channel of the analog multiplexer 901 is activated per system clock cycle. The analog multiplexer 901 may take the outputs 908 of the N-number integrating portions and output a signal which combines the N-number integrating portions 904. The M-SC-CV block is connected to the non-inverting inputs of the integrating portions 904 via line 920. Finally the operations of the ADC 916 are also controlled by the M-SC-CV block 902 via a line 925 to avoid signal glitches, induced noise, and/or to synchronize system operations.
(40) FIG. 10 presents a top-view layout of an NM chip that implements the capacitive feedback transimpedance amplifier with a multiplexer shown in FIG. 6 (note: pads are not illustrated for clarity) along 4 sides. The configuration of FIG. 10 arranges N-by-M integrator Op Amp 1006 array 1001 in the center of a chip 1000. The functional blocks 1002, 1003, and 1004 are located around the chip periphery, the functional blocks include a row decoder 1002, command voltage bias circuitry 1003, multiplexer, differentiator, ADC, and encoder block 1004, and column decoder 1005. Pad sizes and locations are however critical to an efficient layout. For example, if 100 Op Amp array 1001 are integrated on the chip, at least 100 pads may be required to access the nanopore array. In that case 25 pads would be located on each side (assuming a 2525 configuration). If each pad is 100 m100 m with a pitch of 200 m, 25 pads would occupy 5 mm on each side. Thus the chip would be more than 5 mm5 mm. As other functional blocks 1002, 1003, 1004, and 1005 are needed and have their own inputs and outputs the number of pads needed increases, which in turn increases the size of the chip. In practice the pad dimensions end up controlling chip density. Therefore, in one embodiment, system may implement the area-efficient pad technique taught by L. Luh, J. Chroma, and J. Draper, Area-efficient area pad design for high pin-count chips, in Proc. IEEE Ninth Great Lakes Symp. VLSI, pp. 78-81, March 1999. That area-efficient pad technique is used for high pin-count chips.
(41) FIG. 11 illustrates a cross-sectional structure having a pad 1100 comprised of a top metal layer 1101, a 5th metal layer 1102, a fourth metal layer 1103, a third metal layer 1104, a second metal layer 1105 and a first metal layer 1106. That cross-sectional structure also includes an ESD network 1110 and an amplifier 1107. Because the amplifier 1107 is located in the center of the chip, the amplifier 1107 is connected to the pad 1100 and ESD 1110 through the rather long first metal line 1108. In FIG. 11 it should be understood that the pad 1100 and the ESD 1110 network are placed at the peripherals of the chip.
(42) To increase chip density, rather than use the cross-sectional structure shown in FIG. 11, one approach implements the cross-sectional structure illustrated in FIG. 12. As shown in FIG. 12 the cross-sectional structure has a pad 1200 comprised of a top metal layer 1201, a 5th metal layer 1202, a fourth metal layer 1203, a third metal layer 1204, a second metal layer 1205 and a first metal layer 1206. However, the first metal layer 1201 is relatively short. This is achieved by integrating the ESD network and an integrator amplifier as an ESD+Amplifier network 1206 that is placed under the pad 1200 in the center of the chip. This enables a reduced chip size and/or a higher density. Flip-chip bonding can be used to connect the chip to a multi-nanopore array which is located on a printed-circuit board (PCB).
(43) FIG. 13 present a board-level configuration for multi-nanopore sensing using the inventive multiplexing technique in an integrated NM array multiplexing chip 1304 and an NM nanopore sensor array 1307 made of nanopore sensors 1308. The N-by-M nanopore sensor array 1307 has NM cis chambers but only one trans chamber that is directly connected to the integrated NM array multiplexing chip 1304 by a common ground line 1306. If the trans reservoir is placed in the top-right corner (beside 1, M chamber), the distance between the trans reservoir and the N, 1 chamber may cause a parasitic resistance. That makes the ground 1309 of the N, 1 chamber different than the ground of the trans reservoir. To reduce the deleterious effects of the parasitic resistance FIG. 13 incorporates a mesh-type trans-reservoir that is connected to the multiplexing chip ground through multiple metal lines 1305. This reduces the line parasitic resistance and normalizes the grounds to a common value.
(44) In FIG. 13, the integrated NM array multiplexing chip 1304 outputs digital bit streams that are fed to a wireless module 1302 and to a USB interfacing module 1303. Of course, other types of interfaces could be used. The wireless module 1302 wirelessly transmits data into a smart phone, tablet PC, or other receiving device. The USB interfacing module 1303 beneficially can be applied to a personal computer through a USB port.
(45) The overall goal is to realize 1,000 or more patch clamp amplifiers on the NM array multiplexing chip 1304. However, it is also possible to simply use resistive-feedback amplifiers similar to that shown in FIG. 5 for multi-channel nanopore sensing. In that case, as previously noted the number of amplifier integrated onto a chip is limited by a size of the feedback resistor R.sub.F. FIG. 15 illustrates that case.
(46) In various embodiments, the amplifying unit of the nucleotide sequencer uses the resistive feedback transimpedance amplifier with the integrator-differentiator configuration to amplifying the measured ionic current that is output from the measuring device. In various embodiments, the resistive feedback transimpedance amplifier is implemented with a pseudo-resistor. FIG. 14 represents a process 1400 through which the measured ionic current is amplified with the amplifying device using resistive feedback and a multiplexer. In step 1401, the integrating portion of the resistive feedback transimpedance amplifier receives an output ionic current from the measuring device. The measuring device could include an array of nanopore sensors. Then, in step 1402, the outputs from the integrating portions are sent to a multiplexer. In step 1403, the multiplexer arranges the outputs from the integrating portions such that it will send one output at a time to the differentiating portion every clock cycle. In step 1404, the differentiating portion outputs an resulting voltage value. Given that the amplifier comprises of a transimpedance feedback, the resulting signal is a voltage value instead of a current value. In step 1405, the output(s) from the differentiating portion(s) are buffered. In step 1406, a digital to analog converter (ADC) converts the analog signal of the buffered output from the differentiating portion of the resistive feedback transimpedance amplifier to digital signals. In step 1407, the digital signal is related to a computing device for analysis. The computing device can be any device with a process. Examples of the computing device include but not limited to a smart phone, tablet, personal computer, and laptop. The digital signal can be related to the computing device through a universal serial bus (USB) module, a wireless network, or any other wireless or wireless connection.
(47) FIG. 15 illustrates the use of an analog multiplexer 1501 and a shared difference Op Amp amplifier 1510 with resistive feedback integrator Op Amps 1504 in a manner that still enables a reduction in overall dimensions, which enables more amplifiers per chip. FIG. 15 shows an N-integrator resistive feedback multiplexed configuration 1500 that is based on resistive feedback transimpedance amplifying with integrator-differentiator configuration as shown in FIG. 5. In this example, each of N-number of nanopore sensors 1503 are connected to an inverting input 1506 of each of N-number of integrator Op Amps 1504. Each integrating portion 1504 includes a feedback resistor R.sub.F 1505. Not shown for clarity is that each nanopore sensor 1503 shares the same ground as the analog multiplexer 1501. Each nanopore cis chamber is connected to one and only one integrator Op Amp 1504 while all trans chambers and the analog multiplexer 1501 share the same ground.
(48) Still referring to FIG. 15, all integrator Op Amps 1504 are turned on by a command voltage (VCMD) provided on a DC biasing line 1520 from a Multiplexing, Sampling Clock Generator, and Command voltage biasing block 1502 (herein after M-SC-CV block 520). R.sub.F 1505 is chosen to have a high values in the tens of MOhm or GOhm range. Smaller feedback resistors R.sub.F 1505 enable more Op Amps 1504 but at the cost of gain.
(49) Referring to FIG. 15, the analog multiplexer 1501 selects one of the outputs 1508 of the integrating portions 1504 and connects that selected output to a resistor R.sub.1 1509, which applies the selected output to a gain amplifier Op Amp 1510 and to a feedback resistor R.sub.2 1512. The output 1513 of the gain amplifier Op Amp 1510 is applied to the non-inverting input 1515 of a unity gain buffer Op Amp 1511. The output of 1514 the buffer Op Amp 1511 is applied to an analog to digital converter 1516 whose output is made available on a pad 1517. The pad 1517 might connect to a USB interface module or a wireless module or some other type of output.
(50) The gain amplifier Op Amp 1510 is shared by all integrator Op-Amps 1540 via the analog multiplexer 1510 and gain controls are used to adjust the actual value of R.sub.2 1512. The selected analog multiplexer 1501 channel is controlled by signals applied on buss 1519 by the M-SC-CV block 1520. The analog multiplexer 1501 is controlled in accord with a system clock of the M-SC-CV block 1502, which is made available on a pad 1518. Only one channel of the analog multiplexer 1501 is activated per system clock cycle. Finally, the operation of the analog-to-digital converter (ADC) 1516 is also controlled by the M-SC-CV block 1502 via a line 1521 to avoid signal glitches, induced noise, and/or to synchronize system operations.
(51) Comparing FIG. 15 with FIG. 9, in FIG. 15 the feedback capacitors C.sub.F 905 and C.sub.1 913 of FIG. 8 are replaced with resistors R.sub.F 1501 and R.sub.1 1509. Since the feedback resistors R.sub.F are large, tens of MOhms or Giga ohms, the number of amplification channel is restricted. Using pseudo resistors enable the number of channels to be increased. As shown, the multiplexing electronics in FIG. 15 can be adopted to incorporate the same techniques which previously described for the multiplexing electronics using integrator-differentiator architecture.
(52) Amplifier compensation is important. One approach to compensation is found in J. Kim, K. D. Pedrotti and W. B. Dunbar, On-chip patch-clamp sensor for solid-state nanopore applications, Electronics Letters, vol. 47, no. 15, pp. 844-846, July 2011. That compensation technique reduces and avoids transient delays caused by input parasitic capacitances that occur when the command voltages used for DNA motion control during nanopore sensing change. Such compensation techniques can increase the number of amplification channels on a given size chip. Other compensation techniques are also known, see for example B. Sakmann and E. Neher, Single-channel recording, Plenum Press, New York, 1995 and P. Weerakoon, and et al., An integrated patch-clamp potentiostat with electrode compensation, IEEE Trans. on biomedical circuit and system, vol. 3, April 2009. However, those teaching use rather complex structures that occupy a fair amount of chip area. This tends to limit the number of amplification channel on the chip. Thus, the teachings of J. Kim, K. D. Pedrotti and W. B. Dunbar show compensation technique in the multiplexing electronics.
(53) Therefore, it is to be understood that while the figures and the above description illustrate the present invention, they are exemplary only. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously many modifications and variations are possible in light of the above teaching. Therefore, the present invention is to be limited only by the appended claims.
