Abstract
An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.
Claims
1. A chopper stabilized square cell receiving a first signal, a second signal and a clock signal, and having a first output signal and a second output signal, comprising: a first square cell; a second square cell, wherein the first and second square cells each receive an input signal and provide an output signal; an input switch circuit operated by the clock signal to provide the first signal and the second signal in an alternating manner to the first square cell and the second square cell, such that when the first signal is provided as the input signal to the first square cell, the second signal is provided as the input signal to the second square cell and when the first signal is provided as the input signal to the second square cell, the second signal is provided as input signal to the first square cell; and an output switch circuit operated by the clock signal to provide the output signal of the first square cell and the output signal of the second square cell in an alternating manner as the first output signal and the second output signal, such that when the output signal of the first square cell is provided as the first output signal, the output signal of the second square cell is provided as the second output signal and when the output signal of the first square cell is provided as the second output signal, the output signal of the second square cell is provided as the first output signal.
2. The chopper-stabilized square cell of claim 1, further comprising a difference circuit receiving the first and second output signals to provide an output signal representing a difference between the first and second output signals.
3. The chopper-stabilized square cell of claim 2, further comprising a low pass filter operating on the output signal of the difference circuit.
4. The chopper-stabilized square cell of claim 1, further comprising a first high pass filter operating on the first output signal and a second high pass filter operating on the second output signal.
5. The chopper-stabilized square cell of claim 1, wherein the input switch circuit comprises a first switch and a second switch.
6. The chopper-stabilized square cell of claim 1, wherein the clock signal comprises a sinusoidal signal.
7. The chopper-stabilized square cell of claim 1, wherein the clock signal comprises a square wave.
8. The chopper-stabilized square cell of claim 1, wherein the input switch circuit and the output switch circuit operate by different phases of the clock signal.
9. The chopper-stabilized square cell of claim 1, wherein the second signal comprises a DC reference signal.
10. The chopper-stabilized square cell of claim 1, wherein the second signal comprises a signal of a predetermined waveform and power.
11. The chopper-stabilized square cell of claim 1, wherein the clock signal has a frequency lower than frequencies of the first signal.
12. The chopper-stabilized square cell of claim 1, wherein the clock signal has a frequency lower than a bandwidth of the first signal.
13. The chopper-stabilized square cell of claim 1, wherein a center frequency of the first signal is an integral multiple of a frequency of the clock signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 shows an RMS-DC converter 100 which extends its dynamic range by placing variable gain amplifier (VGA) 102 at the input terminal of square cell 107.
(2) FIG. 2 shows RMS power detector 200, in which low frequency feedback is used in conjunction with square cells 207a and 207b.
(3) FIG. 3 illustrates chopper-stabilized square cell 300, in accordance with one embodiment of the present invention.
(4) FIGS. 4(a) to 4(h) show the waveforms of various signals in chopper-stabilized square cell 300 of FIG. 3, when reference signal 302 is the ground reference (i.e., zero volts).
(5) FIGS. 5(a) to 5(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 0 Hz.
(6) FIGS. 6(a) to 6(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 20 MHz.
(7) FIGS. 7(a) and 7(b) show the output spectra of the output signal of switch 305a, when chopper clock signal 310 is a square wave and when chopper clock signal 310 is sinusoidal, respectively.
(8) FIGS. 8(a) and 8(b) show the spectra of the input signal of switch 305a without a DC blocking capacitor and with the DC blocking capacitor, respectively.
(9) FIGS. 9(a) to 9(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 1 MHz.
(10) FIG. 10 illustrate the output spectra of the output signal of square cell 307a for both a 1 MHz chopper clock frequency (dark) and a 20 MHz chopper clock frequency (light).
(11) FIG. 11 shows the response of square cell 307a for a 1-tone and 9-tone input signal (same average power) at chopper frequencies of 1 MHz and 20 MHz.
(12) FIG. 12 illustrates the effectiveness of the choppers in eliminating DC offset from the square cell transfer function.
(13) FIGS. 13(a) and 13(b) show current and voltage switches, respectively, that are suitable for implementing any of switches 308a, 308b, 305a and 305b.
(14) FIGS. 14(a) and 14(b) show square cell topologies that are suitable for use in the chopped square cell driven single-ended and differentially, respectively.
(15) FIG. 15 shows RMS-DC converter 400 based on the chopper stabilized square cells, in accordance with one embodiment of the present invention.
(16) FIG. 16 shows variable gain amplifier 500 suitable for implementing variable gain amplifier 404.
(17) FIG. 17 shows the transfer function of RMS-DC converter 400, plotted as the voltage of output signal 412 versus RMS power of input signal 411.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(18) FIG. 3 illustrates chopper-stabilized square cell 300, in accordance with one embodiment of the present invention. As shown in FIG. 3, chopper-stabilized square cell 300 includes input signal 301 and reference signal 302, which are each selectively provided by either switches 308a or 308b to square cell 307a or square cell 307b, depending on the state of switches 308a and 308b. At any given time, if switch 308a is set to receive input signal 301, switch 308b is set to receive reference signal 302. Alternatively, if switch 308a is set to receive reference signal 302, switch 308b is set to receive input signal 301. As each square cell has internal offsets that add to either the input signal or the output signal, these offsets are represented by adders 303a and 303b that add offsets X.sub.OS1 and X.sub.OS2 to the signals provided to square cells 307a and 307b, respectively, and adders 304a and 304b that add offsets Y.sub.OS1 and Y.sub.OS2 to the output signals of square cells 307a and 307b, respectively. The output offset-adjusted output signals of square cells 307a and 307b are provided by switches 305a and 305b to difference circuit 309, which provides their difference as output signal 306 for chopper-stabilized square cell 300. The offset components X.sub.OS1, X.sub.OS2 and Y.sub.OS1, Y.sub.OS2 are uncorrelated and are each often large relative to output signal 306. Chopper-stabilized square cell 300 represents a balanced square cell that has an RF input and a reference input and which achieves a zero output signal for a zero input signal. Square cells that do not apply chopping according to the present invention have a limited dynamic range that is typically 20-30 dB.
(19) Each of switches 305a, 305b, 308a and 308b may be implemented as voltage switches (e.g. using MOS-transistors in triode), or as current switches (e.g., using bipolar or MOS differential pairs). Current switches may provide a higher bandwidth, but typically require an input amplifier to convert a high-frequency input voltage into an input current. FIGS. 13(a) and 13(b) show current and voltage switches, respectively, that are suitable for implementing any of switches 308a, 308b, 305a and 305b. FIGS. 14(a) and 14(b) illustrate, respectively, single-ended and differential square cells suitable for implementing square cells 307a and 307b. The chopper operation allows a simplification of the square cell topology (i.e., the DC reference current needed to achieve zero output current at zero input voltage is not required).
(20) Chopping is a technique that reduces offset in amplifiers, for example. In chopping, the input signal is typically up-converted before amplification to an intermediate frequency (IF) that is higher than the highest frequency in the input signal, and then down-converted back to the original frequency. Any DC offset introduced in the amplifier is up-converted by the same operation that realizes the down-conversion of the amplified input signal. High-frequency ripple caused by the up-converted offset are eliminated by low-pass filtering. Up-conversion and down-conversion can be achieved simply changing the polarity of the input signal in accordance with the chopper frequency. In a square cell, this approach does not work, as the squaring operation rectifies the input signaleliminating the polarity inversionsand thus produces an output signal component at DC, where the offset to be eliminated also resides. In order to achieve an output signal component at IF, rather than at DC, the square cell input signal is switched on and off at the chopper frequency.
(21) The input chopper of FIG. 3, i.e., switches 308a and 308b, alternates the RF input signal and input reference signal between square cells 307a and 307b. Under this arrangement, when square cell 307a receives RF input signal 301, square cell 307b receives the reference signal 302, and when square cell 307b receives RF input signal 301, square cell 307a receives the reference signal 302. FIGS. 4(a) to 4(h) illustrate the waveforms of various signals in the square cell 300 of FIG. 3. FIG. 4(a) shows RF input signal 301. For simplicity, reference signal 302 is set equal to zero volts (i.e., ground reference) in FIG. 4. Chopper clock signal 310 with controls switches 308a, 308b, 305a and 305b is shown in FIG. 4(b). The output signals of switches 308a and 308b are shown in FIGS. 4(c) and 4(d), respectively. FIGS. 4(e) and 4(f) show the signals at switches 305a and 305b, respectively, after the squaring operations square cells 307a and 307b and including the offsets. FIG. 4(g) shows the difference between the input signals applied to switches 305a and 305b respectively. FIG. 4(h) shows the output signal of difference circuit 309. The difference of the output signals of square cells 307a and 307b has a component that is proportional to the squared result of RF input signal 301, modulated on chopper clock signal 310 (i.e. at a non-zero IF), while the offset introduced by square cells 307a and 307b are located at DC. Thus, after the second chopper (i.e., switches 305a and 305b), the squared signal is down-converted to DC, while the offsets are up-converted by the chopper clock. There are, therefore, two different ways to eliminate the offset. The first way passes a difference of the square cell output signalsprior to the second chopper operationthrough a high-pass filter, eliminating the DC offsets while preserving the up-converted signal components. The second way passes an output signal of the second chopper circuit through a low pass filter, thereby suppressing the up-converted offset while passing the down-converted output signal. These approaches may be combined to achieve better offset suppression.
(22) The output signal of the input chopper (i.e., switches 308a and 308b) may contain a component at the chopper frequency that is not proportional to the input signal due to, for example, charge injection in the input switches, or a DC component in the input signal of the chopper. Such components are down-converted by the second chopper (i.e., switches 305a and 305b) and introduce a dynamic offset in the output signal that compromises the dynamic range of the chopper-stabilized square cell. These components may be reduced, for example, by ensuring that the input signal is AC coupled to the input square cell. Alternatively, these components may also be reduced by choosing a chopper frequency that is much lower than the input signal frequency. Under this second way, the direct feed-through can then be eliminated using a high-pass filter of the chopper output signal, thereby suppressing the signal at the chopper frequency, but passing signals within the input frequency plus or minus the chopper frequency. This approach may be implemented in power detectors. A third approach to reducing these components at output terminals of the first choppers (e.g., switches 308a and 308b) is to choose a chopper frequency that is as low as possible, so as to minimize charge injection effects.
(23) A duty cycle different from 50% can cause a residual offset component in the output signal of the chopper-stabilized square cell; if the chopper clock signal has a DC component, not all DC offset components are up-converted to the chopper frequency by the output chopper. A divide-by-2 circuit can provide an effective solution to maintain the 50% duty cycle.
(24) Clock signals with a finite slew-rate may cause the chopper switches to pass slowly through their linear operating region, thus allowing DC offsets to pass through the switches during a portion of the clock cycle. This effect can be eliminated by applying non-overlapping clocks to the output switches (i.e., break-before-make), which ensures that no DC path to the output exists at any instant during the clock cycle. The switches may be controlled at the same frequency, but a phase difference may exist between the control signals applied to the input switches and the control signal applied to the output switchdifferent combinations of clock signals can be applied to both switches, as illustrated in the article, Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers, by Godoy et al., published in the IEEE Journal of Solid Slate Circuits, vol. 43, No. 10, October 2008, pp. 2311-2321.
(25) Simulations based on idealized Verilog models of the square cells and switches have been used to validate the relationships derived previously. In these simulations, which cover chopper frequencies at 0 Hz, 20 MHz and 1 MHz, the input signal frequency was chosen to be an integer multiple of the simulated chopper frequency (e.g., the input signal frequency is selected to be f.sub.in=100 MHz), except for the case where the chopper frequency is 0 Hz. However, it should be noted that an integer relationship is not required between the chopper frequency and the input frequency for correct chopped square cell operation. The input signal has also a selected bandwidth of 8 MHz. The equivalent input offset in square cell 307a was chosen to be 10 mV, and zero mV in square cell 307b. An output offset current of 10 A was added at output terminal of square cell 307a. The DC offset component in the input signal to the second chopper (i.e., switch 305a) is suppressed by a DC blocking capacitor. The conversion gains of square cells 307a and 307b are each 300 A/V.sup.2 are terminated into 10 k.
(26) FIGS. 5(a) to 5(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 0 Hz. FIG. 5(a) show the spectrum of RF input signal 301. FIG. 5(b) show the spectrum of the output signal of switch 308a; at f.sub.chop=0 Hz, this spectrum is the same as the spectrum for RF input signal 301 shown in FIG. 5(a). FIG. 5(c) shows the spectrum of input signal X.sub.1 at the input terminal of square cell 307a, which includes input offset X.sub.OS1 represented by an impulse at 0 Hz. FIG. 5(d) shows the spectrum of the output signal at the output terminal of square cell 307a, which represent the convolution of the spectra of RF input signal 301 and input offset X.sub.OS1 with itself. As expected, this spectrum has peaks around f=0 (desired component), f=f.sub.RF (cross-term between signal and offset) and f=2f.sub.RF (double frequency term due to the squaring operation). FIG. 5(e) show the spectrum of the output signal at square cell 307a, including an additional output current offset Y.sub.OS1, which adds an impulse at f=0 that cannot be separated from the input signal. FIG. 5(f) shows the spectrum of the output signal at the output terminal of switch 305a; at f.sub.chop=0 Hz, this spectrum is the same as the spectrum in FIG. 5(e). FIG. 5(g) shows the spectrum of output signal 305, after low-pass filtering. This reference simulation shows that the output DC offset Y.sub.OS1 only contributes at DC, while the equivalent input offset X.sub.OS1 also has a contribution around at f.sub.RF (the frequency of RF input signal 301) due to cross-terms.
(27) FIGS. 6(a) to 6(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 20 MHz, which is much higher than the bandwidth of RF input signal 301. FIG. 6(a) show the spectrum of RF input signal 301. FIG. 6(b) show the spectrum of the output signal of switch 308a. FIG. 6(c) shows the spectrum of input signal X.sub.1 at the input terminal of square cell 307a, which includes input offset X.sub.OS1 represented by an impulse at 0 Hz. FIG. 6(c) shows a spectrum that contains side-bands at .sub.in.sub.C, where .sub.i is the center frequency of RF input signal 301 (100 MHz) and .sub.c is the chopper frequency (20 MHz). Since a square wave was used for the chopper, only odd harmonics are present. Because the choppers are turned on and off (rather than the output signal polarity being changed), the DC component in the output signal of the input choppers provides the component at the input signal frequency (100 MHz). Table 1 summarizes the various components of the spectrum of FIG. 6(c):
(28) TABLE-US-00001 TABLE 1 Lower side-band Upper side-band Chopper Signal Harmonics frequency (MHz) frequency (MHz) 0 100 100 1 80 120 3 40 160 5 0 200 7 40 240 2n + 1 f.sub.RF (2n + 1)f.sub.chop f.sub.RF + (2n + 1)f.sub.chop
(29) FIG. 6(d) shows the spectrum of the output signal at the output terminal of square cell 307a, which represent the convolution of the spectra of RF input signal 301 and input offset X.sub.OS1 with itself and each other before output DC offset Y.sub.OS1 is added. The side-bands of the signal components are twice as wide as the input spectrum shown in FIG. 6(c), due to the squaring operation in square cell 307a, and are centered at the odd harmonics of the chopper frequency. Table 2 summarizes the various side band components in the output spectrum of square cells 307a and 307b depicted in FIG. 6(d), relative to the components found when no chopping is applied (0 Hz). Without chopping, the square cell output spectrum would have components at 0 Hz and at 2 the input frequency (2f.sub.RF) of the
(30) TABLE-US-00002 TABLE 2 Chopper Signal Side bands of Side bands of Component Harmonics Component at f = 0 (MHz) at f = 2 f.sub.RF (MHz) 1 20 180 220 3 60 140 260 5 100 100 300 7 140 60 340 9 180 20 380 2n + 1 (2n + 1)f.sub.chop 2f.sub.RF 2f.sub.RF + (2n + 1)f.sub.chop (2n + 1)f.sub.chop
(31) The signal components are located at the odd harmonics of the chopper frequency, thus separated by 2*fchop=40 MHz. In this particular case, the two signal side-bandsone that would be located at 0 Hz without chopping and the other at the second harmonic of RF input signal 301align, because their separation of 2*f.sub.RF=200 MHz is an integer multiple of the side-band separation 2*fchop=40 MHz.
(32) The side-bands corresponding to the cross-terms between RF input signal 301 and input offset X.sub.OS1 are located at the odd harmonics of the chopper frequency, centered at the center frequency of RF input signal 301, as shown in Table 3. The side-bands are copies of the spectrum of RF input signal 301, scaled by the magnitude of output offset Y.sub.OS1.
(33) TABLE-US-00003 TABLE 3 Lower side-band Upper side-band Chopper Signal Harmonics frequency (MHz) frequency (MHz) 1 80 120 3 40 160 5 0 200 7 40 240 2n + 1 f.sub.RF (2n + 1)f.sub.chop f.sub.RF + (2n + 1)f.sub.chop
(34) In this simulation, the center frequency of RF input signal, the cross-product of RF input signal 301 and input offset X.sub.OS1 coincide with the even harmonics of the chopper frequency. It is thus desirable that the center frequency of RF input signal 301 is considerably higher than the chopper frequency; this will significantly reduce the magnitude of any cross-product terms that land at the primary signal component (at fchop=20 MHz).
(35) FIG. 6(e) show the spectrum of the output signal at square cell 307a, including an additional output current offset Y.sub.OS1. FIG. 6(f) shows the spectrum of the output signal at the output terminal of switch 305a. Ideally, the signal spectrum of FIG. 6(f) only has components at DC and not at higher harmonics of RF input signal 301. However, if the chopper signal is not ideally square, some higher harmonic components would remain present. Table 4 shows the signal components of the output signal at switch 305a:
(36) TABLE-US-00004 TABLE 4 Chopper Signal Side bands of Component Side bands of Component Harmonics at f = 0 (MHz) at f = 2 f.sub.RF (MHz) 0 0 200 200 2 40 160 240 4 80 120 280 6 120 80 320 8 160 40 360 10 200 0 400 2n 2nf.sub.chop 2f.sub.RF 2nf.sub.chop 2f.sub.RF + 2nf.sub.chop
(37) FIG. 6(g) shows the spectrum of output signal 305, after low-pass filtering. FIGS. 7(a) and 7(b) show the output spectra of the output signal of switch 305a, when chopper clock signal 310 is a square wave and when chopper clock signal 310 is sinusoidal, respectively; the higher harmonics of RF input signal 301 diminish when the chopper signal approaches a square wave. As shown in FIG. 7(b), a strong signal side band around the second harmonic of the chopper frequency is present (only 3 dB below the side-band at DC) in the sinusoidal case. As shown in FIG. 7(a), the side band around the second harmonic of the chopper frequency (40 MHz) is largely suppressed (by almost 68 dB) in the square wave case.
(38) As explained above, the DC offset component in the input signal to the second chopper (i.e., switch 305a) is suppressed by a DC blocking capacitor. FIGS. 8(a) and 8(b) show the spectra of the input signal of switch 305a without a DC blocking capacitor and with the DC blocking capacitor, respectively. As shown in FIG. 8(a) the offsets cause large spikes at the harmonics of the chopper frequency, resulting in significant ripples. The DC blocking capacitor helps to reduce these ripples.
(39) FIGS. 9(a) to 9(g) show the spectra of various signals obtained by simulation of chopper-stabilized square cell 300 of FIG. 3 at a chopper frequency of 1 MHz. FIG. 9(a) show the spectrum of RF input signal 301. FIG. 9(b) show the spectrum of the output signal of switch 308a. FIG. 9(c) shows the spectrum of input signal X.sub.1 at the input terminal of square cell 307a, which includes input offset X.sub.OS1 represented by an impulse at 0 Hz. As shown in FIG. 9(c), the side-bands of chopped RF input signal 301 are aliasing with RF input signal 301, resulting inon a logarithmic scalean almost triangular shaped input spectrum. FIG. 9(d) shows the spectrum of the output signal at the output terminal of square cell 307a. As shown in FIG. 9(d), a copy of the output signal is seen centered at f=100 MHz, which is shifted to DC by the second chopper operation (i.e., by the actions of switches 305a and 305b).
(40) FIG. 9(e) show the spectrum of the output signal at square cell 307a, including an additional output current offset Y.sub.OS1, which adds an impulse at f=0. FIG. 9(f) shows the spectrum of the output signal at the output terminal of switch 305a. FIG. 9(g) shows the spectrum of output signal 305, after low-pass filtering.
(41) FIG. 10 illustrates the output spectra of the output signal of square cell 307a for both a 1 MHz chopper clock frequency (dark) and a 20 MHz chopper clock frequency (light). In both cases the same signal spectrum is reproduced around DC. With a 1 MHz clock, more side bands are visible in the same bandwidth as with the 20 MHz clock (in fact, 20 times as many).
(42) FIG. 11 shows the response of square cell 307a for a 1-tone and 9-tone input signal (same average power) at chopper frequencies of 1 MHz and 20 MHz. The responses are virtually the same, despite the very different frequency spectra, as seen from corresponding FIGS. 6(a) to 6(g) and 9(a) to 9(g).
(43) FIG. 12 illustrates the effectiveness of the choppers in eliminating DC offset from the square cell transfer function. An input offset voltage of 5 mV and output offset current of 10 A was inserted in a Verilog-A model of a chopper-stabilized square cell. When the chopper is turned off (light), the offsets completely saturate the square cell output, leaving virtually no useful square cell dynamic range. With the chopper is turned on (dark), the offset is completely removed from the output signal.
(44) FIG. 15 shows RMS-DC converter 400 based on the chopper stabilized square cells, in accordance with one embodiment of the present invention. As shown in FIG. 15, square cells 403a and 403b are chopped by switch networks 402 and 405 based on the principles described above with respect to chopper-stabilized square cell 300 of FIG. 3. In FIG. 15, RMS-DC converter 400's output signal 412 is provided to feedback circuit 407, which provides control signal 413 to reference input terminal of chopper-stabilized square cell 403a at switch network 402. Control signal 413 performs the same function as input reference signal 302 of FIG. 3. Control signal 413 may be a DC or AC signal derived from output signal 412. As shown in FIG. 15, feedback circuit 407 may provide control signal 414, which controls the gain of a variable gain amplifier 404 in the forward path. The inclusion of a variable gain amplifier 404 is not required, but helps to maintain a substantially constant loop-gain in RMS-DC converter 400 over the full operating power range. FIG. 16 shows variable gain amplifier 500 suitable for implementing variable gain amplifier 404. In steady state, the average output signal of square cells 403a and 403b are equal, such that the overall transfer from RMS input signal 411 to DC output signal 412 approaches the inverse of the transfer function of feedback circuit 407. FIG. 17 shows the transfer function of RMS-DC converter 400, plotted as the voltage of output signal 412 versus RMS power of input signal 411.
(45) The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.
