Method for determining an optimal voltage pulse for programming a flash memory cell

Abstract

A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

Claims

1. A method for determining an optimal voltage pulse for programming a NOR-type flash memory cell comprising a floating gate, a control gate and a drain, said optimal voltage pulse, to be applied to the control gate of the memory cell, being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, the method comprising: providing a set of parameters including a programming window target value and a drain current target value of the memory cell; dynamically measuring a drain current of the memory cell when a rectangular-shaped voltage pulse is applied to the control gate; providing a transistor equivalent to the memory cell and comprising a gate electrode and a drain electrode, such that the a drain current of the transistor is equal to the drain current of the memory cell when the gate electrode of the transistor is brought to a potential equal to the a potential of the floating gate of the memory cell; dynamically measuring the drain current of the transistor as a function of the potential of the gate electrode of the transistor; determining the potential of the floating gate during the rectangular-shaped voltage pulse, from the measurement of the drain current of the memory cell and the measurement of the drain current of the transistor; determining, respectively from the drain current target value, the potential of the floating gate during the rectangular-shaped voltage pulse and from the programming window target value, the initial voltage level, a slope of the voltage ramp and the programming duration, such that the drain current of the memory cell during the optimal voltage pulse is substantially equal to the drain current target value; and wherein the drain of the memory cell is brought, during the measurement of the drain current of the memory cell, to a constant potential identical to that of the drain electrode of the transistor during the measurement of the drain current of the transistor.

2. The method according to claim 1, wherein the initial voltage level is determined from the measurement of the drain current of the memory cell at a start of the rectangular-shaped voltage pulse, by measuring the value of the potential applied to the control gate of the memory cell for which the drain current is equal to the drain current target value of the memory cell.

3. The method according to claim 1, wherein the slope of the voltage ramp is determined from the derivative of the potential of the floating gate, when the potential of the floating gate reaches a floating gate potential target value corresponding to the drain current target value.

4. The method according to claim 1, wherein the programming duration is determined from the programming window target value and from the slope of the voltage ramp.

5. The method according to claim 4, wherein the programming duration is calculated using the following relationship:
t.sub.pulse=PW.sub.TG/S where PW.sub.TG is the programming window target value and S is the slope of the voltage ramp.

6. The method according to claim 1, wherein the transistor equivalent to the memory cell to program is comprised of a test flash memory cell, of identical geometry to the flash memory cell to program, having a floating gate and a control gate in short-circuit.

7. A non-transitory computer program product comprising instructions for implementing a method according to claim 1, when executed by a computer.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other characteristics and advantages of the invention will become clear from the description that is given thereof below, for indicative purposes and in no way limiting, with reference to the appended figures, among which:

(2) FIG. 1, described previously, represents a flash memory cell according to the prior art;

(3) FIG. 2, described previously, represents the drain current and the gate voltage of the cell of FIG. 1 as a function of time, during a conventional programming of this cell;

(4) FIG. 3 represents a voltage pulse allowing to program the flash memory cell in an optimal manner;

(5) FIG. 4 represents the flash memory cell of FIG. 1 and a transistor equivalent to this flash memory cell;

(6) FIGS. 5A to 5C represent the steps of a method for determining an optimal voltage pulse according to the invention, allowing to determine the potential of the floating gate of the flash memory cell during conventional programming;

(7) FIG. 6 represents a step allowing to determine the initial voltage level of the pulse of FIG. 3, according to a preferential embodiment of the method according to the invention;

(8) FIGS. 7A and 7B represent steps allowing to determine the slope of the ramp in the pulse of FIG. 3, according to the preferential embodiment of the method according to the invention;

(9) FIG. 8 is an exemplary embodiment of the determining method according to the invention, showing three optimal voltage pulses and the drain current of the memory cell when these pulses serve to program the flash memory cell;

(10) FIG. 9 is an abacus representing the compromise between the performances of the flash memory cell, in terms of electrical consumption, drain current and programming window.

(11) For greater clarity, identical or similar elements are marked by identical reference signs in all of the figures. Furthermore, in some of the figures, the currents and electrical potentials are expressed in arbitrary units (a.u.).

DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

(12) In the description that follows, a unit EEPROM-Flash memory (i.e. of a capacity of 1 bit) of NOR type is called flash memory cell. This cell may be embedded in a test circuit, to develop and qualify EEPROM-Flash technology, or constitute the base of a flash memory circuit. A flash memory circuit, or memory array, includes a plurality of these memory cells arranged in lines and columns. NOR-type EEPROM-Flash memory circuits today equip numerous electronic devices, for example mobile telephones, for storing all types of information, in particular programs.

(13) As described previously (FIG. 1), a flash memory cell is provided with a transistor including a control gate, a floating gate, drain and source regions formed in a semiconductor substrate. The control gate, the drain, the source and the substrate constitute control electrodes, noted respectively G, D, S and B. These electrodes allow to bias the transistor to carry out programming (or writing), erasing or reading operations of the memory cell. The potential of an electrode or the current passing through an electrode will be noted hereafter by the appropriate symbol of the potential or the current (V or I), followed by the letter designating the electrode. For example, Vg designates the potential of the control gate G and Id designates the current in the drain electrode D.

(14) In this flash memory cell, the potential V.sub.FG(t) of the floating gate over time depends on the polarizations Vg(t) and Vd(t) of the transistorrespectively on the control gate G and on the drain Dand the charge of electrons Q.sub.FG(t) in the floating gate. It is written:

(15) $\begin{array}{cc}{V}_{\mathrm{FG}}\left(t\right)={}_G.Math.\mathrm{Vg}\left(t\right)+{}_D.Math.\mathrm{Vd}\left(t\right)+\frac{Q_{\mathrm{FG}}\left(t\right)}{C_{\mathrm{tot}}}& \left(1\right)\end{array}$

(16) In the above relation, .sub.G and .sub.D are respectively the coupling factors of the control gate and drain (fixed by the architecture of the cell), and C.sub.tot is the total capacitance of the cell.

(17) Thus, when the cell is normally programmed at a constant potential Vd(t) (Vd(t)=Vd.sub.PROG) and at a constant potential Vg(t), the evolution of the potential V.sub.FG(t) of the floating gate only depends on the charge of electrons Q.sub.FG(t) in the floating gate. The reduction in this charge (or its increase in absolute value, the charge Q.sub.FG(t) being negative) during the programming thus causes a reduction in the potential V.sub.FG(t) of the floating gate. This explains on the one hand the increase in the threshold voltage of the floating gate transistor and on the other hand the reduction in the drain current Id(t), when a rectangular gate pulse is applied to the gate electrode (FIG. 2).

(18) Rather than applying a rectangular gate pulse, it is wished to apply to the control gate of the memory cell a voltage pulse allowing to maintain constant programming efficiency during the entire programming duration, in other words constant drain Id(t) and gate Ig(t) currents during programming. A constant drain current Id(t) implies a constant potential V.sub.FG(t) of the floating gate. The following equation (drawn from the preceding relationship (1)) ensues:

(19) $\begin{array}{cc}\frac{V_{\mathrm{FG}}\left(t\right)}{t}=0={}_G.Math.\frac{\mathrm{Vg}\left(t\right)}{t}+\frac{1}{C_{\mathrm{tot}}}\frac{Q_{\mathrm{FG}}\left(t\right)}{t}\mathrm{hence}\text{:}\frac{\mathrm{Vg}\left(t\right)}{t}=-\frac{1}{{}_G.Math.C_{\mathrm{tot}}}.Math.\frac{Q_{\mathrm{FG}}\left(t\right)}{t}=-\frac{\mathrm{Ig}\left(t\right)}{{}_G.Math.C_{\mathrm{tot}}}=\mathrm{cte}& \left(2\right)\end{array}$

(20) It thus appears that a linear increase of the potential Vg(t) during programming is necessary to ensure constant programming efficiency.

(21) FIG. 3 shows the shape of the gate pulse 30 enabling this optimal programming of the flash memory cell. The pulse 30 includes, from a non-zero initial voltage level Vg.sub.start a ramp 31 of positive slope S. The duration of the pulse 30, noted t.sub.pulse, is the programming duration and corresponds to the time period t where the potential Vg is non-zero, that is to say to the duration of the ramp 31.

(22) This shape of gate pulse allows to compensate the reduction in charge Q.sub.FG in the floating gate linked to the trapping of electrons, during the programming of the memory cell. In fact, by progressively increasing the potential Vg(t) applied to the control gate of the memory cell, the value of the parameter .sub.G.Math.Vg(t) is increased in the potential relationship V.sub.FG(t) (relationship (1)).

(23) Determining the optimal gate pulse 30 to program the flash memory cell consists in determining the slope S of the ramp, the initial voltage level Vg.sub.start and the duration of the pulse t.sub.pulse, fixing as objective reaching a target value of the programming window, noted PW.sub.TG, and the drain current target value Id.sub.TG (that is to say the value at which it is wished to maintain the drain current Id(t)). At least one of these parameters, the slope S, requires determining beforehand the potential V.sub.FG(t) of the floating gate during conventional programming. Conventional programming is taken to mean programming by means of a rectangular-shaped gate pulse.

(24) The determination of the potential V.sub.FG(t) is based on the use of a transistor equivalent to the memory cell of which it is wished to optimize the programming.

(25) FIG. 4 schematically represents this equivalent transistor 40 (also called TREQ), at the sides of the flash memory cell 10 of FIG. 1. Like the memory cell 10, the transistor 40 includes a gate electrode G and a drain electrode D. The transistor 40 is configured such that its drain current Id.sub.TREQ is equal to the drain current Id of the memory cell 10, when the gate electrode G of the transistor 40 is brought to a potential Vg.sub.TREQ equal to the potential of the floating gate V.sub.FG of the memory cell 10 and when the drain electrode D of the transistor 40 is brought to the same potential as the drain of the cell 10 (Vd=Vd.sub.TREQ=Vd.sub.PROG).

(26) The equivalent transistor 40 is, preferably, comprised of a test flash memory cell, of identical geometry to the flash memory cell 10, and in which the floating gate and the control gate are in short-circuit. The floating gate and the control gate of this reference cell thus form the gate electrode G of the equivalent transistor 40.

(27) FIGS. 5A to 5C represent three steps F1 to F3 of a method for determining the optimal gate pulse 30 of FIG. 3, taking account of the programming parameters PW.sub.TG and Id.sub.TG. These steps F1 to F3 aim to determine, using the equivalent transistor 40, the potential V.sub.FG(t) of the floating gate during conventional programming of the memory cell 10.

(28) At step F1 of FIG. 5A, the drain current Id of the flash memory cell 10 is measured dynamically, while a rectangular voltage pulse 20 is applied to the gate electrode of the cell (potential Vg(t)). The drain of the memory cell is brought to a potential Vd.sub.PROG, for example equal to 4 V, at least during the entire duration of the pulse 20. This measurement is carried out preferably using a PIV (Pulsed I-V system) or FMU (Fast Measurement Unit) appliance, by plotting for example a point every 10 ns. The FMU model B1530 marketed by the firm Keysight Technologies or the PIV model 4225-RPM marketed by the firm Keithley Instruments may be cited as examples.

(29) Besides, in F2, the drain current Id.sub.TREQ of the equivalent transistor 40 is measured as a function of its gate potential Vg.sub.TREQ. This measurement is also carried out in a dynamic manner, and preferably in the same conditions as the measurement of step F1 (same appliance, same sampling duration, etc.). Moreover, the drain D of the transistor 40 is brought to the same potential Vd.sub.PROG=4 V as previously.

(30) Since the two measurements are independent, step F1 and step F2 may be carried out in any order.

(31) Step F3 represented in FIG. 5C consists in determining the potential of the floating gate V.sub.FG(t) during the gate pulse 20, from the measurement F1 of the drain current Id(t) of the memory cell 10 (FIG. 5A) and the characteristic Id.sub.TREQ(Vg.sub.TREQ) of the transistor measured at step F2 (FIG. 5B). To do so, it is possible to determine the drain current Id(t=t.sub.i) corresponding to a given time t.sub.i on the plot of FIG. 5A, reporting this current on the characteristic Id.sub.TREQ Vg.sub.TREQ of FIG. 5B and deducing therefrom the corresponding potential Vg.sub.TREQ. Knowing that the current Id of the flash memory cell 10 is equal to the current Id.sub.TREQ of the transistor 40 if and only if the potential V.sub.FG of the floating gate is equal to the gate potential Vg.sub.TREQ of the transistor (FIG. 4), this enables to obtain the value of the floating gate potential V.sub.FG at time t.sub.i (V.sub.FG(t=t.sub.i)). By repeating these operations for several time values t, the curve V.sub.FG(t) representing the floating gate potential as a function of time is reconstructed point by point.

(32) In other words, the characteristic Id.sub.TREQ(Vg.sub.TREQ) of FIG. 5B allows to establish the link between the drain current Id(t) of the memory cell 10 and the potential V.sub.FG(t) of the floating gate.

(33) Finally, during a final step of the method, the characteristics of the optimal gate pulse 30 are determined, namely the gate potential Vg.sub.start at the start of the ramp 31, the slope S of the ramp 31 and the duration of the pulse t.sub.pulse, such that the drain current Id of the flash memory cell during optimal programming reaches the target value Id.sub.TG and that the programming window of the cell is equal to the target value PW.sub.TG.

(34) In a preferential embodiment of the determining method, this final step is broken down into three sub-steps, of which two are represented by FIGS. 6 and 7, each of these sub-steps aiming to determine one of these characteristics.

(35) The initial voltage level Vg.sub.start is the value of the potential Vg to apply to the control gate of the memory cell at the start of programming, i.e. in the absence or almost absence of electrical charges in the floating gate, in order to obtain a drain current Id equal to the target value Id.sub.TG. It is thus advisable to establish the link between the drain current Id and the potential Vg when the cell is in the erased state.

(36) This link is given directly by the measurement F1 of the drain current Id(t) of the flash memory cell, when the memory cell is programmed in a conventional manner (FIG. 5A). Thus, at step F41 of FIG. 6, the initial voltage level Vg.sub.start is advantageously determined from the measurement of the drain current Id(t) at the start of the rectangular gate pulse 20, by notting the value of the gate potential Vg for which the drain current Id is equal to the drain current target value Id.sub.TG.

(37) FIG. 6 is a graph representing both the drain current Id(t) and the gate potential Vg(t) (like FIG. 5A), during a time period corresponding to the start of the rectangular pulse 20 (this period being marked by a frame 50 in dotted lines in FIG. 5A).

(38) This graph allows to determine simply the initial voltage level Vg.sub.start of the optimal pulse 30. The drain current target value Id.sub.TG is firstly reported on this graph, to determine the instant t of conventional programming where the drain current Id of the floating gate is equal to the target value Id.sub.TG. Then, the gate potential Vg at this same instant is determined, it is equal to the initial voltage level Vg.sub.start.

(39) As indicated previously, the slope S of the optimal gate pulse 30 (FIG. 3) allows to compensate the reduction in the charge Q.sub.FG in the floating gate which occurs during conventional programming, in order that the drain current Id is maintained at the target value Id.sub.TG. The slope S being the time derivative of the gate potential Vg(t), its expression is directly given by the equation (2):

(40) $S=\frac{\mathrm{Vg}\left(t\right)}{t}=-\frac{\mathrm{Ig}\left(t\right)}{{}_G.Math.C_{\mathrm{tot}}}=-\frac{{\mathrm{Ig}}_{\mathrm{TG}}}{{}_G.Math.C_{\mathrm{tot}}}$

(41) where Ig.sub.TG is the value which the gate current Ig takes during the programming of the memory cell (Ig(t)=cte=Ig.sub.TG), this value being called hereafter gate current target value.

(42) The gate current Ig(t) during conventional programming is written:

(43) $\mathrm{Ig}\left(t\right)=C_{\mathrm{tot}}.Math.\frac{V_{\mathrm{FG}}\left(t\right)}{t}$

(44) The gate current target value Ig.sub.TG is thus equal to the total capacitance C.sub.tot of the memory cell multiplied by the derivative of the potential of the floating gate V.sub.FG(t), at an instant t of conventional programming where the potential of the floating gate V.sub.FG(t) reaches a value V.sub.FG-TGknown as floating gate potential target valuecorresponding to the drain current target value Id.sub.TG.

(45) The expression of the slope S then becomes:

(46) $S=-\frac{{\mathrm{Ig}}_{\mathrm{TG}}}{{}_G.Math.C_{\mathrm{tot}}}=-\frac{1}{{}_G}\frac{V_{\mathrm{FG}}\left(t\right)}{t}{|}_{t=t_{V_{\mathrm{FG}}\left(t\right)=V_{\mathrm{FG}-\mathrm{TG}}}}$

(47) Thus, in the preferential embodiment of the determining method, the slope S may be determined simply and rapidly from the derivative of the potential of the floating gate V.sub.FG(t) when this is equal to the target value V.sub.FG-TG, either by calculation using the above equation, or graphically by means of the plot of the floating gate potential V.sub.FG(t).

(48) FIG. 7A represents, during a step F42 of the method, a manner for determining this target value V.sub.FG-TG of the floating gate potential. As a reminder, when the drain current Id.sub.TREQ of the equivalent transistor 40 is equal to the drain current Id of the memory cell 10, this means that the control gate of the transistor and the floating gate of the memory cell are at the same potential (cf. FIG. 4). To determine the target value V.sub.FG-TG, it thus suffices to note on the characteristic Id.sub.TREQ(Vg.sub.TREQ) of FIG. 5B the potential Vg.sub.TREQ for which Id.sub.TREQ=Id.sub.TG is obtained.

(49) FIG. 7B represents a step F43 of the method in which the slope S is determined graphically from the plot of the floating gate potential V.sub.FG(t) obtained at step F3 (FIG. 5C). Firstly the point of the curve V.sub.FG(t) having for y-axis the target value V.sub.FG-TG is determined, then the slope of the curve V.sub.FG(t) at this point is measured to deduce therefrom the slope S (by dividing the slope of the curve V.sub.FG(t) by .sub.G).

(50) The duration t.sub.pulse of the optimal pulse 30, in other words the programming duration, influences directly the programming window of the memory cell. The duration t.sub.pulse is thus determined from the programming window target value PW.sub.TG.

(51) The programming window target value PW.sub.TG is given by the following relationship:

(52) ${\mathrm{PW}}_{\mathrm{TG}}=\mathrm{PW}\left(t=t_{\mathrm{pulse}}\right)=\frac{-Q_{\mathrm{FG}}\left(t=t_{\mathrm{pulse}}\right)}{{}_G.Math.C_{\mathrm{tot}}}=\frac{-{}_{t_{\mathrm{pulse}}}^{}\mathrm{Ig}\left(t\right).Math.t}{{}_G.Math.\mathrm{Ctot}}$

(53) Since the gate current Ig(t) is assumed constant during the entire programming duration t.sub.pulse (Ig(t)=cte=Ig.sub.TG), the preceding equation is simplified in the form:

(54) ${\mathrm{PW}}_{\mathrm{TG}}=\frac{-t_{\mathrm{pulse}}.{\mathrm{Ig}}_{\mathrm{TG}}}{{}_G.Math.C_{\mathrm{tot}}}$

(55) The duration t.sub.pulse of the optimal pulse is thus equal to:

(56) $t_{\mathrm{pulse}}=\frac{-{\mathrm{PW}}_{\mathrm{TG}}.Math.{}_G.Math.C_{\mathrm{tot}}}{{\mathrm{Ig}}_{\mathrm{TG}}}=\frac{{\mathrm{PW}}_{\mathrm{TG}}}{S}$

(57) Thus, a simple and rapid way of determining the duration t.sub.pulse consists in calculating the ratio between the programming window target value PW.sub.TG and the slope S of the voltage ramp, the latter having been thus determined previously at step F43.

(58) FIG. 8 represents, as an example, three optimal gate pulses P1, P2 and P3 determined thanks to this method according to the invention, as well as the plots of the drain current Id of the flash memory cell during the application of these pulses. As a comparison, the rectangular gate pulse 20 conventionally used to program the flash memory cell and the corresponding drain current Id is represented, i.e. identical curves (at least as regards the shape) to those of FIG. 2.

(59) The pulses P1, P2 and P3 have been determined for one programming window target value PW.sub.TG equal to 6 V and for three drain current target values: respectively Id.sub.TG1, Id.sub.TG2 and Id.sub.TG3 (with Id.sub.TG1<Id.sub.TG2<Id.sub.TG3).

(60) The plots of the drain current Id show that, for each optimal pulse P1 to P3, the drain current Id (full line) is substantially constant, unlike the drain current caused by a rectangular pulse 20 (dotted lines). Constant programming efficiency is thus obtained thanks to these optimal pulses. Moreover, the drain current target value Id.sub.TG is practically reached for each optimal pulse P1 to P3. The difference between the drain current Id(t) and the corresponding target value Id.sub.TG observed in these examples can be attributed to the variations in performances from one memory cell to the next (due to the variability of the manufacturing method). These variations here concern the programmed memory cell and the equivalent transistor having served in the determination of the optimal pulses P1-P3, itself comprised of a flash memory cell. The difference between the target value Id.sub.TG and the real value of the drain current Id(t) is less than 10 A. The method for determination is thus satisfactory in terms of precision.

(61) As may be seen in FIG. 8, the initial voltage level Vg.sub.start varies from one optimal pulse to the next, according to the value of the targeted drain current Id.sub.TG. In fact, the higher the desired drain current, the higher the initial bias of the floating gate transistor. In the same way, the slope of the ramp increases with the target value Id.sub.TG, because a strong drain current has a tendency to reduce more rapidly than a weak drain current. On the other hand, the memory cell is indeed written more rapidly with a strong drain current, for example equal to Id.sub.TG3, than with a weak drain current, for example equal to Id.sub.TG1. It is thus normal, for a same programming window target value, that the pulse P3 has a shorter duration than the pulse P1.

(62) Certain of the steps of the method above, in particular step F3 and the step that follows it, may be executed by a software. This software determines, from measurements of drain current on the flash memory cell (step F1) and on the equivalent transistor (step F2), the optimal gate pulse which satisfies the programming parameters Id.sub.TG and PW.sub.TG entered by the user in the software. Thanks to this software, it is possible to simulate rapidly a large number of optimal pulses, using the same measurements of drain current on the cell and on the equivalent transistor. A single operation of conventional programming of the memory cell is thus necessary. The software is, preferably, installed on a computer connected to the PIV or FMU measurement appliance. Thus, the computer executes a program which controls the measurement appliance for carrying out dynamic current measurements, recovers the measurement data, and compiles these data, for example by means of a processor, to determine the optimal voltage pulse.

(63) FIG. 9 is an abacus of performances of a flash memory cell established thanks to the determining method according to the invention. It represents the energy Ec consumed by the memory cell during its programming as a function of the drain current target value Id.sub.TG (in general the value of the drain current not to exceed), and for several programming window target values PW.sub.TG. Each point of this abacus is obtained by determining the optimal pulse corresponding to a given pairing {Id.sub.TG; PW.sub.TG}, then by calculating the energy consumed Ec by the memory cell when it is programmed with this pulse. The energy consumed Ec is calculated by determining the integral of the drain current Id(t) multiplied by the drain potential Vd(t) of the cell over the entire pulse duration t.sub.pulse.

(64) This type of abacus thus represents the compromise between the programming window PW.sub.TG, the energy consumption Ec and the maximum drain current Id.sub.TG of the memory cell. It enables flash memory manufacturers to choose the optimal gate pulse, as a function of the specifications to comply with. Each curve of the abacus delimits a forbidden operating zone (below the curve) and an authorized operating zone (above the curve). For example, if the manufacturer desires a programming window PW.sub.TG of at least 6 V and a consumed energy Ec not exceeding 1 nJ, the maximum drain current Id.sub.TG cannot be lower than the value Id.sub.TGmin. The manufacturer must choose an optimal pulse for which the compromise PW.sub.TG/Ec/Id.sub.TG belongs to the hatched zone 90 in FIG. 9.