SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 m or more.

Claims

1. A semiconductor device comprising: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 m or more.

2. The semiconductor device of claim 1, further comprising a solder joining the semiconductor element to the plating, wherein the plating includes a lower layer film and an upper layer film formed on the lower layer film, the lower layer film has higher rigidity than the upper layer film, and the upper layer film has higher wettability with respect to the solder than the lower layer film.

3. The semiconductor device of claim 1, wherein the plating includes first and second platings arranged side by side, the semiconductor element includes first and second semiconductor elements joined to the first and second platings respectively, the first semiconductor element is thinner than the second semiconductor element, and the first plating is thicker than the second plating.

4. The semiconductor device of claim 1, wherein a thickness of the plating changes directly below the semiconductor element.

5. The semiconductor device of claim 1, wherein a groove is provided in a periphery of the semiconductor element or in part of the periphery on a top surface of the aluminum pattern.

6. The semiconductor device of claim 1, wherein the surface of the aluminum pattern is subjected to total or partial work hardening.

7. The semiconductor device of claim 1, wherein the semiconductor element is formed of a wide band gap semiconductor.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.

[0011] FIG. 2 is a diagram illustrating results of measuring hardness of plating.

[0012] FIG. 3 is a diagram illustrating plastic deformation of the aluminum pattern having a conventional plating thickness.

[0013] FIG. 4 is a diagram illustrating plastic deformation of the aluminum pattern having a plating thickness of 10 m.

[0014] FIG. 5 is a diagram illustrating a cumulative defect rate vs a power cycle number.

[0015] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

[0016] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention.

[0017] FIG. 8 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention.

[0018] FIG. 9 and FIG. 10 are cross-sectional views illustrating modifications of the semiconductor device according to the fourth embodiment of the present invention.

[0019] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention.

[0020] FIG. 12 and FIG. 13 are top views illustrating a partially enlarged view of the semiconductor device according to the fifth embodiment of the present invention.

[0021] FIGS. 14 to 17 are cross-sectional views illustrating modifications of the semiconductor device according to the fifth embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

[0022] A semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

First Embodiment

[0023] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention. An aluminum pattern 2 made of a pure aluminum or alloy aluminum material is formed on an insulating substrate 1. Platings 3a and 3b are formed on a surface of the aluminum pattern 2. The platings 3a and 3b are arranged side by side. The platings 3a and 3b are nickel platings and have a thickness of 10 m or more.

[0024] Semiconductor elements 4a and 4b are joined to the platings 3a and 3b respectively via solder 5. An electrode 6 is joined to top surfaces of the semiconductor elements 4a and 4b via solder 7. The solder 5 and the solder 7 may be of the same composition or different compositions. An electrode 8 is joined to the aluminum pattern 2. The whole this part is sealed with a sealing material 9 such as resin.

[0025] FIG. 2 is a diagram illustrating results of measuring hardness of plating. Table I also shows the measurement results. Indentation depths are expressed in numerical values of an apparatus laser detector.

TABLE-US-00001 TABLE 1 Test Length of Indentation Hardness Sample load diagonal (m) depth (m) (HV) Specification 1 50 g 40 7 58.2 Specification 2 50 g 39 7.5 60.0 Specification 3 50 g 36.5 6.7 67.3 Specification 4 50 g 25 4 155.6

[0026] When the plating thickness is assumed to be 10 m, no superiority is observed in a degree of adhesion to the aluminum pattern compared to a case where the plating thickness is 5 m and both cases correspond to a fracture mode of the plated part. Moreover, Vickers hardness of the plating surface depends on physical properties of nickel and is not affected by the thickness, and therefore even when the plating thickness is set to 10 m, no superiority is observed. On the other hand, when the plating thickness is assumed to be 10 m, apparent Vickers hardness including the aluminum pattern becomes approximately 2.5 times. Therefore, it is considered that deformation of plating and deformation of the aluminum pattern can be suppressed by increasing the plating thickness.

[0027] FIG. 3 is a diagram illustrating plastic deformation of the aluminum pattern having a conventional plating thickness. FIG. 4 is a diagram illustrating plastic deformation of the aluminum pattern having a plating thickness of 10 m. Both are analysis results of simulation of plastic deformation five power cycles later. By setting the plating thickness to 10 m it is possible to suppress plastic deformation of the aluminum pattern and move a maximum point from a central part to an outside of the semiconductor element. Furthermore, plastic deformation of the plating itself is suppressed and propagation of deformation of the aluminum pattern to the semiconductor element is suppressed.

[0028] FIG. 5 is a diagram illustrating a cumulative defect rate vs a power cycle number. It is observed that a power cycle life improves when the plating thickness is 10 m compared to when the plating thickness is 4 m.

[0029] As described above, in the present embodiment, the thicknesses of the platings 3a and 3b are assumed to be 10 m or more. This makes it less likely for the semiconductor elements 4a and 4b to be affected by the aluminum pattern 2 deformed due to thermal stress. Therefore, it is possible to prevent characteristic variations due to the deformation of the semiconductor elements 4a and 4b and improve reliability (power cycle life) against destruction of the semiconductor elements 4a and 4b.

[0030] The surface of the aluminum pattern 2 is preferably subjected to total or partial work hardening through shot peening or the like. This suppresses the deformation of the aluminum pattern 2 itself, and can thereby amplify the effect of the platings 3a and 3b.

Second Embodiment

[0031] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention. In the present embodiment, the plating 3a is a multilayered film including a lower layer film 10a and an upper layer film 11a formed on the lower layer film 10a. Similarly, the plating 3b is a multilayered film including a lower layer film 10b and an upper layer film 11b formed on the lower layer film 10b. The lower layer films 10a and 10b are made of nickel or the like which has higher rigidity and less likely to become deformed than the upper layer films 11a and 11b. The upper layer films 11a and 11b are made of gold or the like having higher wettability with respect to the solder 5 than the lower layer films 10a and 10b. This makes it possible to keep strength, improve reliability while improving wettability of the solder 5 and reducing voids as well, and thereby also improve assemblability.

Third Embodiment

[0032] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention. In the present embodiment, a semiconductor element 4a is thinner than a semiconductor element 4b. Thus, the plating 3a is made to be thicker than the plating 3b. In this way, when the semiconductor elements 4a and 4b having different thicknesses such as an IGBT and a diode are mounted, it is possible to cause the top surfaces of the semiconductor elements 4a and 4b to have the same height without adjusting the thickness of the solder 5. This makes joining of electrodes to the semiconductor elements 4a and 4b easier and improves assemblability. Moreover, since the thickness of the solder 5 can be made uniform, it is possible to prevent erroneous mounting and reduce a unit price by purchasing products with the same specification.

Fourth Embodiment

[0033] FIG. 8 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention. In the present embodiment, the thicknesses of the platings 3a and 3b also change directly below the semiconductor elements 4a and 4b. This makes it possible to increase the thicknesses of the platings 3a and 3b directly below central parts of the semiconductor elements 4a and 4b where deformation increases to thereby suppress the deformation of the semiconductor elements 4a and 4b. Moreover, since the thickness of the solder 5 at those locations can be reduced, thermal resistance decreases.

[0034] FIG. 9 and FIG. 10 are cross-sectional views illustrating modifications of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 9, the thicknesses of the platings 3a and 3b directly below peripheral parts of the semiconductor elements 4a and 4b may be increased or as shown in FIG. 10, the thicknesses of the platings 3a and 3b directly below central parts and peripheral parts of the semiconductor elements 4a and 4b may be increased. Furthermore, locations where thicknesses are to be increased may be changed for each semiconductor element such as directly below a central part of an IGBT, directly below a peripheral part of the diode.

Fifth Embodiment

[0035] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention. FIG. 12 and FIG. 13 are top views illustrating a partially enlarged view of the semiconductor device according to the fifth embodiment of the present invention. A groove 12 is provided around each of the semiconductor elements 4a and 4b on the top surface of the aluminum pattern 2. As shown in FIG. 12, the groove 12 may be provided in the entire periphery of each of the semiconductor elements 4a and 4b or as shown in FIG. 13, the grooves 12 may be provided in parts of the periphery. In this way, the groove 12 can suppress deformation from outside the groove 12 of the aluminum pattern 2. Furthermore, the groove 12 can suppress a solder flow and also improve assemblability. Adhesiveness of the sealing material 9 can also be improved.

[0036] FIGS. 14 to 17 are cross-sectional views illustrating modifications of the semiconductor device according to the fifth embodiment of the present invention. According to FIG. 1, the cross sectional shape of the groove 12 is rectangular or square, but without being limited to this, similar effects can also be obtained if the cross sectional shape is trapezoidal as shown in FIG. 14 and FIG. 15, triangular as shown in FIG. 16 or semicircular as shown in FIG. 17.

[0037] Note that the semiconductor elements 4a and 4b are not limited to those formed of silicon, but may also be formed of a wide band gap semiconductor having a wider band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, nitride gallium-based material or diamond. This prevents deformation of the semiconductor element even when the semiconductor elements 4a and 4b become hot and makes it possible to secure high reliability. Furthermore, since a high withstand voltage and a high maximum allowable current density are obtained, the system can be downsized. Using the downsized semiconductor elements 4a and 4b also allows a semiconductor device into which the semiconductor elements 4a and 4b are assembled to be downsized. Furthermore, since the semiconductor elements 4a and 4b exhibit high heat resistance, it is possible to downsize radiator fins of a heat sink and substitute a water cooling system by an air cooling system, which allows the semiconductor device to be further downsized. Furthermore, since the semiconductor elements 4a and 4b have less power loss and exhibit high efficiency, the semiconductor device can achieve higher efficiency. Both the semiconductor elements 4a and 4b are preferably formed of wide band gap semiconductors, but either one may be formed of a wide band gap semiconductor and it is still possible to obtain the effects described in the present embodiment.

[0038] Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

[0039] The entire disclosure of Japanese Patent Application No. 2015-201381, filed on Oct. 9, 2015 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, is incorporated herein by reference in its entirety.