METHOD FOR FORMING WAFER

Abstract

This invention provides a method for forming a wafer comprising forming a silicon substrate, and then performing rapid thermal annealing to the substrate to form a passivation layer. The passivation layer reduces the surface roughness of the silicon substrate. During the formation of a gate oxide layer or an interface, deuterium can diffuse from the substrate and combine with dangling bonds of the interface to form a stable structure, thereby carrier penetration can be prevented and device properties can be enhanced.

Claims

1. A method for forming a wafer comprising: providing a silicon substrate, performing rapid thermal annealing to the silicon substrate to form a passivation layer, wherein the rapid thermal annealing comprises using a gas containing deuterium.

2. The method of claim 1, wherein the rapid thermal annealing is performed under a temperature of 1200 C.-1380 C.

3. The method of claim 1, wherein the gas used in the rapid thermal annealing is a mixture of deuterium and hydrogen.

4. The method of claim 3, wherein the deuterium is 1%-100% of the gas.

5. The method of claim 1, wherein the gas used in the rapid thermal annealing is a mixture of deuterium and oxygen.

6. The method of claim 5, wherein the deuterium is 1%-100% of the gas.

7. The method of claim 1, wherein the gas used in the rapid thermal annealing is deuterium.

8. The method of claim 1, wherein the silicon substrate is formed by the steps comprising: forming an silicon ingot, slicing, surface grinding, polishing, edge profiling and cleaning the silicon ingot, and forming the silicon substrate.

9. The method of claim 1, wherein the silicon substrate is monocrystalline silicon.

10. The method of claim 8, wherein the silicon substrate is formed by Czochralski (CZ) method.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 shows one embodiment of the method for forming the wafer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Although the following with reference to the accompanying drawings of the method of the present invention is further described in more detail, there is shown a preferred embodiment of the present invention. A person having ordinary skills in the art may modify the invention described herein while still achieving the advantageous effects of the present invention. Thus, these embodiments should be understood as broad teaching one skilled in the art, and not as a limitation of the present invention.

[0023] For purpose of clarity, not all features of an actual embodiment are described. It may not describe the well-known functions as well as structures in detail to avoid confusion caused by unnecessary details. It should be considered that, in the developments of any actual embodiment, a large number of practice details must be made to achieve the specific goals of the developer, for example, according to the requirements or the constraints of the system or the commercials, one embodiment is changed to another. In addition, it should be considered that such a development effort might be complex and time-consuming, but for a person having ordinary skills in the art is merely routine work.

[0024] In the following paragraphs, the accompanying drawings are referred to describe the present invention more specifically by way of example. The advantages and the features of the present invention are more apparent according to the following description and claims. It should be noted that the drawings are in a simplified form with non-precise ratio for the purpose of assistance to conveniently and clearly explain an embodiment of the present invention.

[0025] In one embodiment, referring to FIG. 1, the method for forming the wafer comprises the following steps:

S100: providing a silicon substrate,
S200: performing rapid thermal annealing to the silicon substrate to form a passivation layer, and the rapid thermal annealing comprising using a gas containing deuterium.

[0026] In one embodiment, the silicon substrate can be formed by the following steps. First, an silicon ingot is formed and polished to a desired size such as the size of wafer. Then the steps including slicing, surface grinding, polishing, edge profiling and cleaning are applied to form the silicon substrate. In the present embodiment, the silicon substrate is monocrystalline silicon formed by Czochralski (CZ) method.

[0027] In S200, the rapid thermal annealing is performed to the silicon substrate to form a passivation layer. The formation of the passivation layer is able to reduce the surface roughness of the silicon substrate and enhance the properties of the silicon substrate.

[0028] In one embodiment, the temperature of the rapid thermal annealing can be between 1200 C.-1380 C., such as 1300 C.

[0029] In one embodiment, the gas used in the rapid thermal annealing is a mixture of deuterium and hydrogen. The deuterium is 1%-100% of the gas mixture, which can be adjusted according to different process requirements.

[0030] In one embodiment, a mixture of deuterium and oxygen can be applied. The deuterium is 1%-100% of the gas mixture, which can be adjusted according to different process requirements.

[0031] In one embodiment, the pure deuterium can be applied to the rapid thermal annealing.

[0032] While deuterium is applied to the rapid thermal annealing, deuterium is able to be temporarily stored in the gap of the silicon substrate because of the small size of the deuterium atom. In the following process for forming the gate oxide layer, the stored deuterium atoms can combine to dangling bonds of the gate oxide layer to form stable chemical bonds. Accordingly, the redundant dangling bonds can be eliminated, and the properties of the gate oxide layer can be enhanced thereby. Moreover, the deuterium atoms not only combine to the dangling bonds of the gate oxide layer but also the dangling bonds of other layers of the semiconductor device. The formed chemical bond from deuterium is more stable than that from other elements such as hydrogen atom.

[0033] According to the above, in the examples of the method of the present application, the rapid thermal annealing is performed to the silicon substrate to form a passivation layer after formation of the silicon substrate. The passivation layer is able to reduce the surface roughness of the silicon substrate. During the formation of the gate oxide layer or the interface, deuterium can diffuse from the substrate and combine with dangling bonds of the interface to form a stable structure, thereby the carrier penetration can be prevented and the device properties can be enhanced.

[0034] Realizations of the above method have been described in the context of particular embodiments. These embodiments are meant to be illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. These and other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the claims that follow.