VACUUM TUBE NONVOLATILE MEMORY AND THE METHOD FOR MAKING THE SAME

Abstract

The present invention provides a vacuum tube nonvolatile memory and the method of manufacturing it. The vacuum tube nonvolatile memory comprises oxide-nitride-oxide composite structure as gate dielectric layer, wherein the nitride layer can trap charges and provide better insulating block capability between the gate and vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provides with excellent gate controllability and negligible gate leakage current due to adoption of the gate insulator.

Claims

1. A vacuum tube nonvolatile memory, comprising: a substrate; a dielectric layer on said substrate; a gate, a source and a drain on said dielectric layer, said source and said drain located at one side of said gate respectively; wherein said gate comprises a vacuum area to expose the sidewalls of said source and said drain; wherein a gate dielectric layer surrounds said vacuum area of said gate; and wherein said gate dielectric layer comprises oxide-nitride-oxide composite layers.

2. The vacuum tube nonvolatile memory according to claim 1, wherein said source and said drain comprises convex shape towards said vacuum area.

3. The vacuum tube nonvolatile memory according to claim 1, further comprising sidewalls located on the side surfaces of said gate.

4. The vacuum tube nonvolatile memory according to claim 1, wherein said dielectric layer comprises a trench, and said gate formed inside said trench.

5. A method of forming a vacuum tube nonvolatile memory, comprising the steps of: providing a substrate; forming a dielectric layer and a sacrificial layer on said substrate; patterning said dielectric layer and said sacrificial layer to form an H shape bridge; etching away said dielectric layer under said H shape bridge; forming a gate dielectric layer on said sacrificial layer and said H shape bridge, wherein said gate dielectric layer comprises oxide-nitride-oxide composite layers; forming a gate on said dielectric layer, wherein said gate surrounded said H shape bridge; etching away said sacrificial layer and said H shape bridge to form a vacuum area inside said gate, wherein said gate dielectric layer exposed in said vacuum area; forming sidewalls on the surface of said gate; and forming a source and a drain areas at one side of said gate respectively.

6. The method of claim 5, further comprising a step of annealing said H shape bridge to make it a rounded shape after forming said H shape bridge.

7. The method of claim 6, wherein said annealing is operated at a He, H.sub.2 Ar or N.sub.2 atmosphere.

8. The method of claim 6, wherein said annealing is operated at a temperature range of 6001000 C.

9. The method of claim 5, wherein a pressure of said vacuum area is in a range of 0.150 torr.

10. The method of claim 5, wherein said etching away said sacrificial layer and said H shape bridge comprises the steps of: etching away said gate dielectric layer on said sacrificial layer to expose said sacrificial layer; etching away exposed sacrificial layer to expose sidewalls of said H shape bridge; selectively wet etching said H shape bridge inside said gate.

11. The method of claim 10, wherein etching away exposed sacrificial layer is performed by dry etching.

12. The method of claim 5, further comprising a step of oxidizing or nitrodizing said gate with O.sub.2, N.sub.2O or NH.sub.3 plasma or ALD deposition of Al.sub.2O.sub.3 or AN on said gate after etching said H shape bridge.

13. The method of claim 5, wherein said source and said drain are a material selected from the group consisting of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond and the combination thereof.

14. The method of claim 5, further comprising a step of annealing said source and said drain.

15. The method of claim 14, wherein said annealing is operated at a H.sub.2 or N.sub.2 atmosphere.

16. The method of claim 15, wherein said annealing is operated at a temperature range of 6001000 C.

17. The method of claim 5, wherein said sacrificial layer is a material selected from the group consisting of Al, Ge, Si, Cr, Mo, W, Fe, Co, Cu, Ga, In, and Ti.

18. The method of claim 5, wherein said oxide-nitride-oxide composite layers comprises silicon dioxide-silicon nitride-silicon dioxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Exemplary embodiments will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

[0039] FIG. 1 is a schematic diagram showing a conventional vacuum tube structure;

[0040] FIG. 2 illustrates an example cross-sectional view of a vacuum tube nonvolatile memory according to an example embodiment of the present invention;

[0041] FIG. 3 is a cross-sectional view along the A-A direction according to one embodiment of the present invention;

[0042] FIG. 4 is a cross-sectional view along the B-B direction according to one embodiment of the present invention;

[0043] FIG. 5 is a flow chart of a fabrication method of a vacuum tube nonvolatile memory according to one embodiment of the present invention; and

[0044] FIGS. 6-15 are cross-sectional views showing process stages of manufacturing a vacuum tube nonvolatile memory according to one embodiment of the present invention.

DETAILED DESCRIPTION

[0045] The following detailed description in conjunction with the drawings of a vacuum tube nonvolatile memory and fabrication method thereof of the present invention represents the preferred embodiments. It should be understood that the skilled in the art can modify the present invention described herein to achieve advantageous effect of the present invention. Therefore, the following description should be understood as well known for the skilled in the art, but should not be considered as a limitation to the present invention.

[0046] For purpose of clarity, not all features of an actual embodiment are described. It may not describe the well-known functions as well as structures in detail to avoid confusion caused by unnecessary details. It should be considered that, in the developments of any actual embodiment, a large number of practice details must be made to achieve the specific goals of the developer, for example, according to the requirements or the constraints of the system or the commercials, one embodiment is changed to another. In addition, it should be considered that such a development effort might be complex and time-consuming, but for a person having ordinary skills in the art is merely routine work.

[0047] In the following paragraphs, the accompanying drawings are referred to describe the present invention more specifically by way of example. The advantages and the features of the present invention are more apparent according to the following description and claims. It should be noted that the drawings are in a simplified form with non-precise ratio for the purpose of assistance to conveniently and clearly explain an embodiment of the present invention.

[0048] Reference is now made to FIGS. 2-4, which illustrate an example cross-sectional view of a vacuum tube nonvolatile memory according to an example embodiment of the present invention. The vacuum tube nonvolatile memory includes a substrate 10, a dielectric layer 20, a gate dielectric layer, a gate 50, and source/drain 70. As shown in the Figures, the dielectric layer 20 is on the substrate 10, the source/drain region 70 is on the dielectric layer 20, and the source/drain region 70 located on each side of the gate 50 respectively. The gate 50 comprises a vacuum region 52 to expose the sidewalls of the source/drain region 70. A gate dielectric layer is formed surrounding the vacuum area 52, and the gate dielectric layer comprises oxide-nitride-oxide composite layers 41/42/43 in this embodiment.

[0049] In one embodiment, the vacuum field effect transistor nonvolatile memory further comprises sidewalls 60 located on the side surfaces of the gate 50. The source/drain region 70 comprises convex shape towards the vacuum region 52, in particular, the source/drain region 70 has curve convex shape towards the vacuum region 52. The dielectric layer 20 comprises a trench, and the gate 50 is formed inside the trench.

[0050] Please refer to FIG. 5, it illustrates a flow chart of manufacturing a vacuum tube nonvolatile memory according to an example embodiment of the present invention. The method includes the steps of:

[0051] S100: providing a substrate;

[0052] S200: forming a dielectric layer and a sacrificial layer on the substrate;

[0053] S300: patterning the dielectric layer and the sacrificial layer to form an H shape bridge;

[0054] S400: etching away the dielectric layer under the H shape bridge;

[0055] S500: forming a gate dielectric layer on the sacrificial layer and the H shape bridge, wherein the gate dielectric layer comprises oxide-nitride-oxide composite layers;

[0056] S600: forming a gate on the dielectric layer, wherein the gate surrounded the H shape bridge;

[0057] S700: etching away the sacrificial layer and the H shape bridge to form a vacuum area inside the gate, wherein the gate dielectric layer in the vacuum area exposed;

[0058] S800: forming sidewalls on the surface of the gate; and

[0059] S900: forming a source and a drain area on each side of the gate respectively.

[0060] In particular, please refer to the following FIGS. 6-15 for the manufacturing process details. Now, refer to FIG. 6, it illustrates the cross-sectional view after the first step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. A dielectric layer 20 and a sacrificial layer 30 are sequentially formed on a substrate 10. In one embodiment, the substrate 10. can be a silicon wafer, a silicon on insulator (SOI) substrate or the like. The dielectric layer 20 is silicon dioxide, and the sacrificial layer 30 can be aluminum (Al), poly Si, Ge, Cr, Mo, W, Fe, Co, Cu, Ga, In, Ti, preferably is Al.

[0061] Next, refer to FIG. 7, it illustrates the cross-sectional view after the second step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The dielectric layer 20 and sacrificial layer 30 are patterned to form an H shape bridge. The H shape bridge can be referred as fin shape structure as well. The patterning can be achieved by conventional silicon patterning technology such as photolithography.

[0062] Next, refer to FIG. 8, it illustrates the cross-sectional view after the third step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The dielectric layer 20 under the H shape bridge 31 etched away to let the H shape bridge 31 overhanging above the remaining dielectric layer 20.

[0063] Next, refer to FIG. 9, it illustrates the cross-sectional view after the fourth step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The H shape bridge 31 annealed to turn the cuboid shaped bridge 31 into a cylindrical nanowire as shown in the Figure. The step can improve the reliability of the vacuum tube nonvolatile memory since it can reduce the stress of the H shape bridge 31. In one embodiment, the anneal process is performed in the environment such as He, N2, Ar or H.sub.2 in the temperature range of 6001000 C., preferably in 800 C.

[0064] Next, refer to FIG. 10, it illustrates the cross-sectional view after the fifth step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. A gate dielectric layer is formed on the H shape bridge 31 and sacrificial layer 30. In one embodiment, the gate dielectric layer is oxide-nitride-oxide (ONO) composite layers 41/42/43 deposited by CVD, PVD, ALD techniques.

[0065] Next, refer to FIG. 11, it illustrates the cross-sectional view after the sixth step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. A gate layer 50 is formed on the dielectric layer 20, the gate layer surrounded the H shape bridge 31. In one embodiment, the gate layer is a metal gate layer deposited by CVD, MOCVD, PVD techniques. The gate patterning can be achieved by conventional silicon patterning technology such as photolithography and dry etching.

[0066] Next, refer to FIG. 12, it illustrates the cross-sectional view after the seventh step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The sacrificial layer 30 and the H shape bridge 31 are removed. In one embodiment, the gate dielectric layer on the sacrificial layer 30 are etching away first, followed by etching away the sacrificial layer 30 to expose the dielectric layer 20 on both sides of the gate 50, and finally the H shape bridge 31 is removed as well to form a vacuum area inside said gate 50 as shown in FIG. 13. In one embodiment, the sacrificial layer etching can be achieved by conventional silicon patterning technology such as photolithography and dry etching, while the H shape bridge is removed by selectively wet etching.

[0067] Next, refer to FIG. 14, it illustrates the cross-sectional view after the ninth step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The gate 50 performed thermal or ALD processes to form sidewalls 60 on the surface of the gate. In one embodiment, the thermal process is an oxidation process in the O.sub.2 environment to form Al.sub.2O.sub.3 as sidewalls on the gate surface. In another embodiment, the thermal process is a nitridation process in the N.sub.2O, or NH.sub.3 environment to form AlN as sidewalls on the gate surface.

[0068] Next, a source and a drain areas 70 are formed on each side of the gate 50 respectively as previously shown in FIG. 2. In one embodiment, the source and drain 70 is metal, and the metal materials include Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or the combination of these materials. In one embodiment, the gate layer is a metal gate layer s deposited by CVD, MOCVD, PVD techniques. The source and drain areas 70 can be deposited by CVD, or PVD techniques. The vacuum area 52 is formed by sealing the gate 50 and source and drain areas 70. In one embodiment, the pressure in the vacuum area 52 is in the range of 0.1 torr50 torr.

[0069] Finally, refer to FIG. 15, it illustrates the cross-sectional view after the tenth step of manufacturing the vacuum tube nonvolatile memory according to an example embodiment of the present invention. The source and drain areas 70 performed thermal treatment processes a H.sub.2 or N.sub.2 environment to form a convex shape towards the vacuum region 52 as shown in FIG. 3 to enhance the performance of the vacuum tube nonvolatile memory. In one embodiment, the thermal treatment process is performed in the temperature range of 6001000 C.

[0070] According to the description above, the present invention disclosed a vacuum tube nonvolatile memory and the method of manufacturing it. The field effect transistor nonvolatile memory is a Metal-ONO-Vacuum Field Effect Transistor Charge Trap Nonvolatile Memory using standard silicon semiconductor processing. The source and drain were separated and replaced by low electron affinity conducting material, with the curvature of the tip controlled by the thermal reflow of the source metal material. An ONO gate dielectric with a nitride charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provides with excellent gate controllability and negligible gate leakage current due to adoption of the gate insulator.

[0071] While various embodiments in accordance with the disclosed principles been described above, it should be understood that they are presented by way of example only, and are not limiting. Thus, the breadth and scope of exemplary embodiment(s) should not be limited by any of the above-described embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.

[0072] Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically, a description of a technology in the Background is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Furthermore, any reference in this disclosure to invention in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings herein.