Semiconductor device

Abstract

The present invention concerns semiconductor devices comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2. Replacing a stack by only one or two 2-dimensional layer(s) of MoS.sub.2, MoSe.sub.2, WS.sub.2, or WSe.sub.2, MoTe.sub.2 or WTe.sub.2 provides an enhanced electrostatic control, low power dissipation, direct band gap and tunability.

Claims

1. A semiconductor device comprising: a source electrode; a drain electrode; a semiconducting layer consisting of a single 2-dimensional layer made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2; a gate electrode, wherein said gate electrode extends over said source electrode and said drain electrode; and a dielectric layer placed between said semiconducting layer and said gate electrode, wherein said dielectric layer is configured to form a protective layer on said semiconducting layer.

2. Semiconductor device according to claim 1 devoid of a top gate electrode and a top dielectric layer.

3. Sensor based on a semiconductor device according to claim 2.

4. Semiconductor device according to claim 1 comprising a second gate electrode.

5. Semiconductor device according to claim 4 wherein said second gate electrode is embedded within an oxide layer.

6. Semiconductor device according to claim 1, wherein said semiconducting layer is a nanosized layer.

7. Semiconductor device according to claim 6 wherein said semiconducting layer is between 0.5 and 1.5 nm thick.

8. Semiconductor device according to claim 1, wherein at least one of said electrodes is made of graphene.

9. Semiconductor device according to claim 1, wherein said dielectric layer is made of HfO.sub.2.

10. Transistor comprising a semiconductor device according to claim 1.

11. Digital inverter comprising a semiconductor device according to claim 1.

12. A semiconductor device comprising: a source electrode; a drain electrode; a first gate electrode; a second gate electrode; a semiconducting layer consisting of a single 2-dimensional layer made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, and WSe.sub.2; and a dielectric layer placed between said semiconducting layer and said first gate electrode; and dielectric later being configured to protect said semiconducting layer.

13. A semiconductor device according to claim 12 wherein said first gate electrode is extending over said source electrode and said drain electrode.

14. A semiconductor device according to claim 12 wherein said first gate electrode is embedded within said dielectric layer.

15. A sensor based on the semiconductor device according to claim 12.

16. A semiconductor device according to claim 12 wherein said second gate electrode is embedded within an oxide layer.

17. A semiconductor device according to claim 12, wherein said semiconducting layer is a nanosized layer.

18. A semiconductor device according to claim 17 wherein said semiconducting layer is between 0.5 and 1.5 nm thick.

19. A semiconductor device according to claim 12, wherein at least one of said electrodes is made of graphene.

20. A semiconductor device according to claim 12, wherein said dielectric layer is made of HfO.sub.2.

21. A transistor comprising the semiconductor device according to claim 12.

22. A digital inverter comprising the semiconductor device according to claim 12.

23. A semiconductor device comprising: a source electrode; a drain electrode; a semiconducting layer comprising two or fewer 2-dimensional layers made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2; a gate electrode, wherein said gate electrode extends over said source electrode and said drain electrode; a dielectric layer placed between said semiconducting layer and said gate electrode, wherein said dielectric layer is configured to form a protective layer on said semiconducting layer; and a second gate electrode, wherein said second gate electrode is embedded within an oxide layer.

24. Semiconductor device according to claim 23, wherein at least one of said electrodes is made of graphene and wherein said dielectric layer is made of HfO.sub.2.

25. A semiconductor device comprising: a source electrode; a drain electrode; a semiconducting layer consisting of a single 2-dimensional layer made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2; a gate electrode, wherein said gate electrode is embedded within a dielectric layer; and said dielectric layer placed between said semiconducting layer and said gate electrode, wherein said dielectric layer is configured to form a protective layer on said semiconducting layer.

26. The semiconductor device of claim 25, wherein the device is devoid of a top gate electrode and a top dielectric layer.

27. A sensor based on a semiconductor device according to claim 25.

28. The semiconductor device of claim 25, further comprising a second gate electrode.

29. The semiconductor device of claim 25, wherein said second gate electrode is embedded within an oxide layer.

30. A semiconductor device comprising: a source electrode; a drain electrode; a gate electrode; a semiconducting layer consisting of a single 2-dimensional layer made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, and WSe.sub.2; and a dielectric layer placed between said semiconducting layer and said gate electrode, wherein said dielectric layer is made of a high dielectric constant dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

(2) FIG. 1A depicts a schematic non-limitative representation of a single0layer MoS.sub.2 transistor according to the invention.

(3) FIG. 1B illustrates the structure of a single two-dimensional layer of MoS.sub.2.

(4) FIG. 2A depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(5) FIG. 2B depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(6) FIG. 2C depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(7) FIG. 2D depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(8) FIG. 2E depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(9) FIG. 2F depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(10) FIG. 2G depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(11) FIG. 2H depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(12) FIG. 2I depicts a semiconductor device in accordance with an embodiment of the present disclosure.

(13) FIG. 3 illustrates a structure and AFM imaging of monolayer MoS.sub.2 in accordance with an embodiment of the present disclosure.

(14) FIG. 4 depicts fabrication of transistors in accordance with an embodiment of the present disclosure.

(15) FIG. 5 depicts a cross-sectional view of a structure of monolayer MoS.sub.2 FET in accordance with an embodiment of the present disclosure.

(16) FIG. 6 depicts local gate control of a transistor in accordance with an embodiment of the present disclosure.

(17) FIG. 7 depicts an integrated circuit based on an embodiment of the present disclosure.

(18) FIG. 8 depicts electrical characterization of an integrated circuit based on an embodiment of the present disclosure.

(19) FIG. 9 depicts characteristics of an integrated MoS.sub.2 inverter in accordance with an embodiment of the present disclosure.

(20) FIG. 10 depicts a demonstration of a NOR gate logic circuit based on an embodiment of the present disclosure.

GENERAL DESCRIPTION OF INVENTION

(21) The invention concerns a semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, MoTe.sub.2 or WTe.sub.2.

(22) Preferred embodiments of the invention are defined in the dependent claims.

(23) Replacing a stack by only one or two 2-dimensional layers of MoS.sub.2, MoSe.sub.2, WS.sub.2, or WSe.sub.2, MoTe.sub.2, WTe.sub.2 provides an enhanced electrostatic control, low power dissipation, direct band gap and tunability. It was shown in Example 1 that a transistor based on a single layer of MoS.sub.2 has a room-temperature on/off ratio of 10.sup.8 and an off-state current of 25 fA/m. This is because the single 2-dimensional layer has a higher band gap than stacks of 2-dimensional layers and because the gate can more efficiently control conduction due to small thickness of the semiconducting material and result in smaller power consumption. Stacks based on dichalcogenide materials described in patent application US2007/181938A1 have a room-temperature on/off ratio on the order of 10 because of the relatively high thickness of the semiconducting material. Such low on/off ratio implies high power consumption in the off state of the transistor. Using a double 2-dimensional layer retains the advantage of a thin material with the additional benefit that the band gap can be tuned with the application of the external electric field. These advantages are no longer present in structures containing 3 or more 2-dimensional layers.

(24) The advantages of using single or double 2-dimensional layers over using stacks of 2-dimensional layers are not obvious to those familiar with the art. A previously shown example (Novoselov et al., Two-dimensional atomic crystals, PNAS 102, 10451 (2005).) does not exhibit turn-off but only shows a linear dependence of conductivity on bottom gate voltage. Such devices cannot be used as field effect transistors. Mak et al. (Mak et al., Atomically Thin MoS.sub.2: A New Direct-Gap Semiconductor, Phys. Rev. Lett. 105, 136805 (2010)) also shows a device that does not turn-off, shows a current modulation by a factor of 100, requiring 160 volts change on the gate electrode which is not practical in devices. All these examples of prior art do invite the use of single 2-dimensional layers in transistor and do not show that using single 2-dimensional layers has advantages over using stacks of 2-dimensional layers.

(25) FIG. 1A is a schematic non-limitative representation of a single-layer MoS.sub.2 transistor according to the invention.

(26) FIG. 1B illustrates the structure of a single two-dimensional layer of MoS.sub.2.

(27) Alternatively the single MoS.sub.2 layer may be replaced a layer made of MoSe.sub.2, WS.sub.2, or WSe.sub.2, MoTe.sub.2, WTe.sub.2. Two 2-dimensional layers may also be used.

(28) Source, drain and top gate electrodes may be made of any electrical conductor, including graphene.

(29) The dielectric layer may be made of any electrically insulating material, including boron-nitride and single-layer boron nitride.

(30) In one embodiment of the invention a bottom dielectric layer may be used, such a layer being made of any electrically insulating material, including boron-nitride and single-layer boron nitride.

(31) The bottom dielectric layer may be omitted if using an electrically insulating substrate.

(32) Substrate may be made of any suitable flat material, solid or flexible; at least: glass, sapphire, kapton, polyimide.

DETAILED DESCRIPTION OF THE INVENTION

(33) The invention will be better understood below, in particular with the use of some non-limiting examples.

(34) The semiconductor device according to the invention may be manufactured by one of the following processes: a) Liquid phase exfoliationthis is the method developed by the Oxford-Trinity college collaboration (Coleman et al., Two-Dimensional Nanosheets Produced by Liquid Exfoliation of Layered Materials, Science 331, 568 (2011). It consists of suspending particles of the material in organic solvents, agitating using solvents using ultrasound and purifying using centrifugation. These solvents can then be sprayed over surfaces or deposited on substrates using the Langmuir-Blodgett technique (Divigalpitiya et al., Thin oriented films of molybdenum disulphide, Thin Solid Films 186, 177 (1990)). This may be the method of choice for applications in cheap, bendable electronics. b) Molecular beam epitaxyelements (Mo and Se for example) are simultaneously evaporated in ultrahigh vacuum onto heated substrates. High quality, continuous films can be grown on large areas (cmcm or larger). (Ueno et al., Epitaxial-Growth of Transition-Metal Dichalcogenides on Cleaved Faces of Mica, Journal of Vacuum Science & Technology A 8, 68 (1990)). c) Chemical vapour transporteither elements (Mo, Se, Te, S, W) or powders (for example MoSe.sub.2) are sublimated in closed ampoules with a warmer and a colder region. Crystals deposit and grow in the colder part of the tube (Enomoto et al., Van der Waals growth of thin TaS.sub.2 on layered substrates by chemical vapor transport technique, Jpn. J. Appl. Phys. 43, L123 (2004)). d) Chemical vapour depositionmixture of gasses flow past a heated catalyst surface. A chemical reaction occurs on the surface, resulting in film growth (Boscher et al., Atmospheric Pressure CVD of Molybdenum Diselenide Films on Glass, Chemical Vapor Deposition 12, 692 (2006)).

(35) In addition to the basic structure shown on FIG. 1A the semiconductor device according to the present invention may be made according to other geometries.

(36) Some non-limitative examples of such geometries are presented in FIGS. 2A to 2I wherein:

(37) FIG. 2A shows a top gate electrode which extends over the other electrodes.

(38) The device of FIG. 2B has no top gate electrode or top oxide. It can be used as a chemical, biological or pH sensor.

(39) In the device of FIG. 2C the top gate electrode is embedded in gate oxide.

(40) The device of FIG. 2D comprises two transistors connected in series (logic inverter).

(41) The device of FIG. 2E comprises three transistors connected in series (logic NOR).

(42) In the device of FIG. 2F the gate oxide is replaced with a ferroelectric material (non-volatile memory).

(43) The device of FIG. 2G shows an additional buried gate electrode, a better electrostatic control and tenability of the band gap in the case where two 2-dimensional layers are used as a semiconducting material.

(44) The device of FIG. 2H contains a buried gate electrode, has no top gate or top oxide and can therefore be used as a sensor.

(45) The device of FIG. 2I has two transistors in series and a junction with n and p-type doping. It can be used as LED.

(46) FIG. 3 shows the structure and AFM imaging of monolayer MoS.sub.2. a Three-dimensional representation of the structure of MoS2. Single layers, 6.5 thick can be extracted using scotch-tape based micromechanical cleavage. b Atomic force microscope image of a single layer of MoS2 deposited on Si substrate with a 270 nm thick oxide layer. c Cross-section plot along the red line in part b.

(47) FIG. 4 shows the fabrication of MoS.sub.2 monolayer transistors. a Optical image of a single layer of MoS.sub.2 with a thickness of 6.5 deposited on top of a Si substrate with a 270 nm thick SiO.sub.2 layer. b Optical image of a device based on the flake shown on figure a. The device consists of two field effect transistors connected in series and defined by three Au leads that serve as source and drain electrodes for the two transistors. Monolayer MoS.sub.2 is covered by 30 nm of ALD deposited HfO.sub.2 that acts both as a gate dielectric and a mobility booster. The scale bars in a and b are 10 m long. c Three-dimensional schematic view of one of the transistors shown on figure b.

(48) FIG. 5 shows characterization of MoS.sub.2 monolayer transistors. a Cross-sectional view of the structure of monolayer MoS.sub.2 FET together with electrical connections used to characterize the device. Single layer of MoS.sub.2 6.5 thick is deposited on degenerately doped Si substrate with 270 nm thick SiO.sub.2. The substrate acts a back gate. One of the gold electrodes acts as drain while the other, source electrode is grounded. The monolayer is separated from the top gate by 30 nm of ALD-grown HfO.sub.2. The top gate width for device is 4 m while the top gate length, source-gate and gate-drain spacing is 500 nm. b Room temperature transfer characteristic for the FET with 10 mV applied bias voltage V.sub.ds. Back gate voltage V.sub.bg is applied to the substrate and the top gate is disconnected. The inset shows an I.sub.ds-V.sub.ds curve acquired for V.sub.bg values of 0.1 and 5 V.

(49) FIG. 6 shows local gate control of the MoS.sub.2 monolayer transistor. a I.sub.ds-V.sub.tg curve recorded for a bias voltages ranging from 10 mV to 500 mV. Measurements are performed at room temperature with the back gate grounded. Top gate width is 4 m while the top gate length is 500 nm. The device can be completely turned off by changing the top gate bias from 2 to 4 V. For V.sub.ds=10 mV, the I.sub.On/I.sub.Off ratio is >110.sup.6. For V.sub.ds=500 mV, the I.sub.On/I.sub.Off ratio is >110.sup.8 in the measured range while the subthreshold swing S=74 mV/dec. Top and bottom gate leakage is negligible (Fig. S3 in supplementary materials). Inset shows I.sub.ds-V.sub.tg for values of V.sub.bg=10,5,0,5 and 10 V. b I.sub.ds-V.sub.ds curves recorded for different values of the top gate voltage V.sub.tg. The linear dependence of the current on bias voltage for small voltages indicates that the Au contacts are ohmic.

(50) FIG. 7 shows an integrated circuit based on single-layer MoS.sub.2 (not to scale). (a) Single-layer MoS.sub.2 is deposited on top of a Si chip covered with 270 nm thick SiO.sub.2. The integrated circuit is composed of two transistors defined by a neighboring pair of leads and controlled by local gates with HfO.sub.2 gate dielectric. (b) Cross-sectional view of the structure of a monolayer MoS.sub.2 integrated circuit together with electrical connections used to characterize the device. One of the gold electrodes acts as drain while the other, source electrode is grounded. The monolayer is separated from the top gate by 30 nm of ALD-grown HfO.sub.2. The top gate width for device is 4.7 m, top gate length is 1.3 m and lead spacing is 1.6 m. The substrate can act as a back gate but is kept grounded during the measurement.

(51) FIG. 8 shows electrical characterization of the integrated circuit based on monolayer MoS.sub.2. (a) Optical image of a monolayer MoS.sub.2 deposited on top of a Si substrate with a 270 nm thick SiO.sub.2 layer. (b) Integrated circuit based on the flake shown in (a). The device consists of three Au electrical leads that can act as source, drain and output terminals and two local gates. The scale bars in (a) and (b) are 10 m long. (c) Drain-source current I.sub.ds through the MoS.sub.2 monolayer transistor on the left side of the integrated circuit shown on b, measured as a function of the top gate voltage V.sub.tg. The MoS.sub.2 transistor shows gating response typical of FETs with n-type conducting channels. Inset shows the drain-source current I.sub.ds as a function of back gate voltage V.sub.bg for drain-source voltage V.sub.ds values of 100 mV, 200 mV and 500 mV. (d) Drain-source current I.sub.ds as a function of drain-source voltage for different values of V.sub.tg. The current through the device changes by over six orders of magnitude when the top gate voltage is swept in the 4V to +4V range.

(52) FIG. 9 shows characteristics of the integrated MoS.sub.2 inverter. (a) Output voltage as a function of the input voltage. Schematic drawing of the electronic circuit and the truth table for the NOT logic operation (Inset). (b) The dependence of the inverter gain (negative value of dV.sub.out/dV.sub.in) on the input voltage. The maximal voltage gain above 4 indicates that our inverter is suitable for integration in arrays of logic devices.

(53) FIG. 10 shows the demonstration of a NOR-gate logic circuit based on single-layer MoS.sub.2 transistors. The circuit is formed by connecting two monolayer MoS.sub.2 transistors in parallel and using an external 1 MOhm resistor as a load (left inset). The output voltage V.sub.out is shown for four different combinations on input states (1,0), (1,1), (0,1) and (0,0). The output is at the high state only if both inputs are in the low state (truth table in the inset). All logic operations can be expressed as combinations of NOR operations.

(54) Two detailed non-limitative examples according to the present invention are presented in the following chapters.

Example 1

Transistor Based on a Single 2-Dimensional Layer of MoS2

(55) Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene,.sup.1,2 both because of its rich physics.sup.3-5 and its high mobility..sup.6 However, pristine graphene does not have a band gap, which is required for many applications including transistors,.sup.7 and engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films.sup.8-13 or requires high voltages..sup.14,15 While single layers of MoS.sub.2 have a large intrinsic bandgap of 1.8 eV.sup.16, previously reported mobilities in the 0.5-3 cm.sup.2/Vs range.sup.17 are too low for practical devices. Here we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS.sub.2 mobility of at least 200 cm.sup.2/Vs, similar to that of graphene nanoribbons, and demonstrate transistors with room temperature current on/off ratios of 10.sup.8 and ultralow stand-by power dissipation. Because monolayer MoS.sub.2 has a direct bandgap.sup.16,18 it can be used to construct inter-band tunnel FETs.sup.19, which offer lower power consumption than classical transistors. Monolayer MoS.sub.2 could also complement graphene in applications that require thin transparent semiconductorsfor example in optoelectronics and energy harvesting.

(56) MoS.sub.2 is a typical example from the layered transition metal dichalcogenide family of materials. Crystals of MoS.sub.2 are composed of vertically stacked, weakly interacting layers held together via van der Waals interaction, FIG. 3a. Single layers, 6.5 thick (FIGS. 3b and 3c), can be extracted by means of scotch tape.sup.17,23 or lithium-based intercalation..sup.24,25 Large-area thin films can also be prepared using MoS.sub.2 suspensions. Bulk MoS.sub.2 is semiconducting with an indirect band gap of 1.2 eV,.sup.26 while single-layer MoS.sub.2 is a direct gap semiconductor.sup.16,18 with a band gap of 1.8 eV..sup.16 MoS.sub.2 nanotubes.sup.27 and nanowires.sup.28 also show the influence of quantum-mechanical confinement in their electronic and optical properties. Other features that could make MoS.sub.2 interesting for nanoelectronic applications include the absence of dangling bonds and thermal stability up to 1100 C.

(57) Single-layer MoS.sub.2 could also be interesting as a semiconducting analogue of graphene that does not have a band gap in its pristine form. Band gaps up to 400 meV have been introduced by quantum mechanical confinement in patterned.sup.20 or exfoliated graphene nanoribbons.sup.9 but always at the price of significant mobility reduction (200 cm.sup.2/Vs for a 150 meV band gap),.sup.9,10 loss of coherence.sup.11 or increased off-state currents due to edge roughness..sup.12 Band gaps were also induced by applying a perpendicular electric field in bilayer graphene,.sup.14,21 but the highest reported optical gap here is 250 meV, requiring application of voltage exceeding 100V..sup.14 This makes it very difficult to build logic circuits based on graphene that would operate at room temperature with low stand-by power dissipation. In fact, any potential replacement of silicon in CMOS-like digital logic devices is desired to have a current on/off ratio.sup.7 I.sub.on/I.sub.off between 10.sup.4 and 10.sup.7 and a band gap exceeding 400 meV..sup.22

(58) The starting point for the fabrication of our transistors is scotch-tape based micromechanical exfoliation.sup.1,17 of single-layer MoS.sub.2. MoS.sub.2 monolayers are transferred to degenerately doped Si substrates covered with 270 nm thick SiO.sub.2, FIG. 4a. We have previously found that this oxide thickness is optimal for optical detection of single-layer MoS.sub.2 and established the correlation between contrast and thickness as measured by atomic force microscopy..sup.29 Electrical contacts are first fabricated using electron beam lithography followed by deposition of 50 nm thick Au electrodes. The device is then annealed at 200 C. in order to remove resist residue.sup.30 and decrease contact resistance (please refer to the supplementary material for more details). At this point our single-layer devices show typical mobility in the 0.1-10 cm.sup.2V/s range, similar to previously reported values for single-layers.sup.17 and thin crystals containing more than 10 layers of MoS.sub.2..sup.31 This is lower than the previously reported phonon-scattering limited room temperature mobility in the 200-500 cm.sup.2/Vs range for bulk MoS.sub.2..sup.32 Encouraged by recent theoretical predictions of mobility improvement by dielectric screening.sup.33 and its successful application to graphene,.sup.34 we proceed by atomic layer deposition of 30 nm HfO.sub.2 as a high- gate dielectric for the local top gate and mobility booster in order to realize the full potential of single-layer MoS.sub.2. We chose HfO.sub.2 because of its high dielectric constant of 25, band gap of 5.7 eV and the fact that it is commonly used as a gate dielectric both by the research community and major microprocessor manufacturers..sup.35,36 The resulting structure, composed of two field-effect transistors connected in series is shown on FIG. 4b with the schematic depiction of the device shown on FIG. 4c. The top gate width for our device is 4 m while the top gate length, source-gate and gate-drain spacing is 500 nm.

(59) We perform electrical characterization of our device at room temperature using a semiconductor parameter analyzer and shielded probe station with voltage sources connected in the configuration depicted on FIG. 5a. We first characterize our MoS.sub.2 transistors with 6.5 thick conductive channels by applying a drain-source bias V.sub.ds to a pair of Au electrodes and gate voltage V.sub.bg to the degenerately doped Si substrate while leaving the top gate electrically floating..sup.37 The gating characteristics of the left-most transistor shown on FIG. 4b is presented on FIG. 5b and is typical of FET devices with an n-type channel. We concentrate on this device in the remainder of the manuscript. Characterization details for other devices and fabrication batches are available in the supplementary material. All the MoS.sub.2 transistors we have fabricated, regardless of the number of layers or contacting material, show behavior typical of FET devices with n-type channels. Repeated V.sub.bg sweeps on the same device do not show significant variation, while keeping all the voltages constant results in constant I.sub.ds, indicating that the top gate is not likely to accumulate charge during measurements. We estimate that a constant surface charge n4.610.sup.12 cm.sup.2 trapped on the top gate would shift the threshold voltage by 1V but not change the slope of the I.sub.ds-V.sub.bg curve on FIG. 5b used for estimating channel mobility. The source current versus source bias characteristics, FIG. 5b inset, is linear in the 50 mV range of voltages, indicating that our Au contacts are ohmic.

(60) The on-resistance of our transistor is 27 k for V.sub.ds=10 mV and V.sub.bg=10 V with the gate width of 4 m and bottom gate length of 1.5 m. We have noticed that the device resistance can increase during storage at ambient conditions for a period of two months. This could be attributed to absorption of oxygen and/or water from the environment and could be mitigated by device encapsulation.

(61) From the data presented on FIG. 5b we can extract the low-field field effect mobility of 217 cm.sup.2/Vs using the expression =[dI.sub.ds/dV.sub.bs][L/(WC.sub.iV.sub.ds)] where L=1.5 m is the channel length, W=4 m channel width and C.sub.i=1.310.sup.4 F/m.sup.2 is the capacitance between the channel and the back gate per unit area (C.sub.i=.sub.0.sub.r/d; .sub.r=3.9; d=270 nm). Note that this value represents the lower limit because of contact resistance. As our device displays ohmic I.sub.ds-V.sub.ds behavior, FIG. 5b inset, we exclude the possibility that our field-effect behavior is dominated by Schottky barriers at the contacts.

(62) Even though the room-temperature value of phonon-scattering limited.sup.32 mobility for bulk MoS.sub.2 is in the 200-500 cm.sup.2/Vs range, exfoliation of single layers onto SiO.sub.2 results in a decrease of mobility down to the 0.1-10 cm.sup.2V/s range. The improvement of the mobility with the deposition of a high- dielectric could be due to suppression of Coulomb scattering due to the high- dielectric environment.sup.33 and modification of phonon dispersion.sup.38 in MoS.sub.2 monolayers. Extensive future theoretical work including calculation of phonon dispersion relation in single-layer MoS.sub.2, calculation of scattering rates on phonons and charge impurities would be needed to provide a complete picture.

(63) Before we compare the value of mobility in our case with the mobility of graphene or thin-film Si we should note that semiconductors such as carbon nanotubes or graphene nanoribbons mostly follow the general trend of decreasing mobility with increasing band gap..sup.22 Even though graphene has a high room temperature mobility of 120000 cm.sup.2/Vs, this value relates to large-area, gapless graphene..sup.6 On the other hand, measurements on 10 nm wide graphene nanoribbons with Eg400 mV indicate mobility lower than 200 cm.sup.2/Vs,.sup.9 in good agreement with theoretical models that predict decreased mobility in small-width GNR due to electron-phonon scattering..sup.13 This is comparable to mobility of 250 cm.sup.2/Vs found in 2 nm thin strained Si films..sup.42 Our MoS.sub.2 monolayer has similar mobility but higher band gap than graphene nanoribbons.sup.9 and a smaller thickness than thinnest Si films fabricated to date..sup.42

(64) One of the crucial requirements for building integrated circuits based on single layers of MoS.sub.2 is the ability to control charge density in a local manner, independently of a global back gate. We can do this by applying a voltage V.sub.tg to the top gate, separated from the monolayer MoS.sub.2 by 30 nm of HfO.sub.2, FIG. 5a, while keeping the substrate grounded. The corresponding transfer characteristic is shown on FIG. 6a. For a bias of 10 mV we observe an on current of 150 nA (37 nA/), current on/off ratio I.sub.on/I.sub.off>10.sup.6 for the 4 V range of V.sub.tg, an off state current that is smaller than 100 fA (25 fA/m) and gate leakage lower than 2 pA/m.sup.2. The observed current variation for different values of V.sub.tg indicates that the field-effect behavior of our transistor is dominated by the MoS.sub.2 channel and not the contacts.

(65) At the bias voltage V.sub.ds=500 mV, the maximal measured on current is 10 A (2.5 A/m), with I.sub.on/I.sub.off higher than 10.sup.8 for the 4 V range of V.sub.tg. The device transconductance defined as g.sub.m=dI.sub.ds/dV.sub.tg at V.sub.ds=500 mV is 4 S (1 S/m), similar to values obtained for high performance CdS nanoribbon array transistors (2.5 S/m at V.sub.ds=1 V)..sup.43 High-performance top-gated graphene transistors can have normalized transconductane values as high as 1.27 mS/m..sup.44 The large degree of current control in our device is also clearly illustrated on FIG. 6b. where we plot the drain-source current versus drain-source bias for different values of voltage applied to the local gate. From the channel current dependence on top-gate voltage, we deduce a subthreshold slope for the transition between the on and off states of 74 mV/dec for a bias V.sub.ds=500 mV. Being a direct gap semiconductor, single layers of MoS.sub.2 offer the intriguing possibility for the realization of an interband tunnel FETs which is characterized by turn-on sharper than the theoretical limit of 60 mV/dec for classical transistors and consequently smaller power dissipation. This feat has remained difficult in case of silicon, an indirect gap semiconductor, because interband transitions there require phonons and recombination centers.

(66) To summarize, we have realized a field-effect transistor with a single, two-dimensional layer of a semiconductor MoS.sub.2 as a conductive channel and hafnium dioxide as a gate insulator. The conductive channel in our device is only 6.5 thick. Our transistor exhibits a room temperature current on/off ratio exceeding 110.sup.8 and mobility of 200 cm.sup.2/Vs, comparable to mobility achieved in thin silicon films.sup.42 or graphene nanoribbons..sup.9 Such a transistor could form the backbone of future electronics based on layered materials where MoS.sub.2 transistors could be fabricated on insulating boron-nitride substrates..sup.40 Our results provide an important step towards the realization of electronics and low stand-by power integrated circuits based on two-dimensional materials. Being a thin, transparent semiconducting material, MoS.sub.2 monolayers also present a wealth of new opportunities in areas that include mesoscopic physics, optoelectronics and energy harvesting. With the possibility to fabricate large areas circuits using solution-based processing, our finding could be important for producing electronic devices that could combine the ease of processing associated with organic conductors with performance figures commonly associated with Si-based electronics.

(67) Materials and Methods

(68) Single layers of MoS.sub.2 are exfoliated from commercially available crystals of molybdenite (SPI Supplies Brand Moly Disulfide) using the scotch-tape micromechanical cleavage technique method pioneered for the production of graphene..sup.1 AFM imaging is performed using the Asylum Research Cypher AFM. After Au contact deposition, devices are annealed in 100 sccm of Ar and 10 sccm H.sub.2 flow at 200 C for 2 h..sup.30 ALD is performed in a home-built reactor using a reaction of H.sub.2O with tetrakis(dimethylamido)hafnium (Sigma Aldrich). Electrical characterization is carried out using Agilent E5270B parameter analyzer and a home-built shielded probe station with micromanipulated probes.

REFERENCES TO EXAMPLE 1

(69) 1 Novoselov, K. S. et al. Electric Field Effect in Atomically Thin Carbon Films. Science 306, 666-669, (2004). 2 Berger, C. et al. Ultrathin Epitaxial Graphite: 2D Electron Gas Properties and a Route toward Graphene-based Nanoelectronics. J. Phys. Chem. B 108, 19912-19916, (2004). 3 Novoselov, K. S. et al. Two-dimensional gas of massless Dirac fermions in graphene. Nature 438, 197-200, (2005). 4 Zhang, Y., Tan, Y.-W., Stormer, H. L. & Kim, P. Experimental observation of the quantum Hall effect and Berry's phase in graphene. Nature 438, 201-204, (2005). 5 Du, X., Skachko, I., Duerr, F., Luican, A. & Andrei, E. Y. Fractional quantum Hall effect and insulating phase of Dirac electrons in graphene. Nature 462, 192-195, (2009). 6 Bolotin, K. I. et al. Ultrahigh electron mobility in suspended graphene. Solid State Communications 146, 351-355, (2008). 7 The International Technology Roadmap for Semiconductors. (2009). 8 Han, M. Y., Ozyilmaz, B., Zhang, Y. & Kim, P. Energy Band-Gap Engineering of Graphene Nanoribbons. Phys. Rev. Lett. 98, 206805, (2007). 9 Li, X., Wang, X., Zhang, L., Lee, S. & Dai, H. Chemically Derived, Ultrasmooth Graphene Nanoribbon Semiconductors. Science 319, 1229-1232, (2008). 10 Jiao, L., Zhang, L., Wang, X., Diankov, G. & Dai, H. Narrow graphene nanoribbons from carbon nanotubes. Nature 458, 877-880, (2009). 11 Sols, F., Guinea, F. & Neto, A. H. C. Coulomb Blockade in Graphene Nanoribbons. Phys. Rev. Lett. 99, 166803, (2007). 12 Yoon, Y. & Guo, J. Effect of edge roughness in graphene nanoribbon transistors. Appl. Phys. Lett. 91, 073103, (2007). 13 Obradovic, B. et al. Analysis of graphene nanoribbons as a channel material for field-effect transistors. Appl. Phys. Lett. 88, 142102, (2006). 14 Zhang, Y. et al. Direct observation of a widely tunable bandgap in bilayer graphene. Nature 459, 820-823, (2009). 15 Xia, F., Farmer, D. B., Lin, Y.-M. & Avouris, P. Graphene Field-Effect Transistors with High On/Off Current Ratio and Large Transport Band Gap at Room Temperature. Nano Lett. 10, 715-718, (2010). 16 Mak, K. F., Lee, C., Hone, J., Shan, J. & Heinz, T. F. Atomically Thin MoS2: A New Direct-Gap Semiconductor. Phys. Rev. Lett. 105, 136805, (2010). 17 Novoselov, K. S. et al. Two-dimensional atomic crystals. PNAS 102, 10451-10453, (2005). 18 Splendiani, A. et al. Emerging Photoluminescence in Monolayer MoS2. Nano Lett. 10, 1271-1275, (2010). 19 Banerjee, S., Richardson, W., Coleman, J. & Chatterjee, A. A new three-terminal tunnel device. El. Dev. Lett., IEEE 8, 347-349, (1987). 20 Han, M. Y., Ozyilmaz, B., Zhang, Y. B. & Kim, P. Energy band-gap engineering of graphene nanoribbons. Phys. Rev. Lett. 98, 206805, (2007). 21 Xia, F., Farmer, D. B., Lin, Y.-M. & Avouris, P. Graphene Field-Effect Transistors with High On/Off Current Ratio and Large Transport Band Gap at Room Temperature. Nano Lett. 10, 715-718, (2010). 22 Schwierz, F. Graphene transistors. Nature Nanotech. 5, 487-496, (2010). 23 Frindt, R. F. Single Crystals of MoS2 Several Molecular Layers Thick. J. App. Phys. 37, 1928-1929, (1966). 24 Joensen, P., Frindt, R. F. & Morrison, S. R. Single-Layer MoS2. Mat. Res. Bull. 21, 457-461, (1986). 25 Schumacher, A., Scandella, L., Kruse, N. & Prins, R. Single-layer MoS2 on mica: studies by means of scanning force microscopy. Surf. Sci. Lett. 289, L595-L598, (1993). 26 Kam, K. K. & Parkinson, B. A. Detailed photocurrent spectroscopy of the semiconducting group VIB transition metal dichalcogenides. J. Phys. Chem. 86, 463-467, (1982). 27 Feldman, Y., Wasserman, E., Srolovitz, D. J. & Tenne, R. High-Rate, Gas-phase grwth of MoS2 nested inorganic fullerenes and nanotubes. Science 267, 222-225, (1995). 28 Remskar, M. et al. Self-Assembly of Subnanometer-Diameter Single-Wall MoS2 Nanotubes. Science 292, 479-481, (2001). 29 Benameur, M., Radisavljevic, B., Sahoo, S., Berger, H. & Kis, A. Visibility of dichalcogenide nanolayers. Cond-mat, 1006.1048, (2010). 30 Ishigami, M., Chen, J. H., Cullen, W. G., Fuhrer, M. S. & Williams, E. D. Atomic Structure of Graphene on SiO2. Nano Lett. 7, 1643-1648, (2007). 31 Ayari, A., Cobas, E., Ogundadegbe, O. & Fuhrer, M. S. Realization and electrical characterization of ultrathin crystals of layered transition-metal dichalcogenides. J. App. Phys. 101, 014507, (2007). 32 Fivaz, R. & Mooser, E. Mobility of Charge Carriers in Semiconducting Layer Structures. Physical Review 163, 743-755, (1967). 33 Debdeep, J. & Aniruddha, K. Enhancement of Carrier Mobility in Semiconductor Nanostructures by Dielectric Engineering. Phys. Rev. Lett. 98, 136805, (2007). 34 Chen, F., Xia, J., Ferry, D. K. & Tao, N. Dielectric Screening Enhanced Performance in Graphene FET. Nano Lett. 9, 2571-2574, (2009). 35 Bohr, M. T., Chau, R. S., Ghani, T. & Mistry, K. The High-k Solution. IEEE Spectrum 44, 29-35, (October 2007). 36 Mistry, K. et al. A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging. Tech. Dig. IEDM, 247-250, (IEEE, 2007). 37 Lemme, M. C. A graphene field-effect device. IEEE El. Dev. Lett. 28, 282, (2007). 38 Fonoberov, V. A. & Balandin, A. A. Giant Enhancement of the Carrier Mobility in Silicon Nanowires with Diamond Coating. Nano Lett. 6, 2442-2446, (2006). 39 Bolotin, K. I. Ultrahigh electron mobility in suspended graphene. Solid State Commun. 146, 351-355, (2008). 40 Dean, C. R. et al. Boron nitride substrates for high-quality graphene electronics. Nature Nanotech. 5, 722-726, (2010). 41 Moser, J., Barreiro, A. & Bachtold, A. Current-induced cleaning of graphene. Appl. Phys. Lett. 91, 163513, (2007). 42 Gomez, L., Aberg, I. & Hoyt, J. L. Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm. El. Dev. Lett., IEEE 28, 285-287, (2007). 43 Duan, X. et al. High-performance thin-film transistors using semiconductor nanowires and nanoribbons. Nature 425, 274, (2003). 44 Liao, L. et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature 467, 305-308, (2010).

Example 2

Integrated Circuits, Inverters and Logic Operations Based on a Single 2-Dimensional Layer of MoS2

(70) Logic circuits and the ability to amplify electrical signals form the functional back-bone of electronics along with the possibility to integrate multiple elements on the same chip. Here, we demonstrate that single-layer MoS.sub.2, a two-dimensional semiconductor with a direct band gap of 1.8 eV (ref 13), has the capability to amplify signals and perform basic logic operations in simple integrated circuits composed of two MoS.sub.2 transistors..sup.3 Our integrated circuit is composed of two n-type transistors realized on the same two-dimensional crystal of monolayer MoS.sub.2, as schematically depicted on FIGS. 7(a) and (b).

(71) Single-layer MoS.sub.2 is a typical two-dimensional semiconductor from the layered transition metal dichalcogenide family. Single layers, 6.5 thick, can be extracted from bulk crystals using the micromechanical cleavage technique commonly associated with the production of graphene,.sup.1, 14 lithium-based intercalation.sup.15-16 or liquid phase exfoliation.sup.17 and used as ready-made blocks for electronics..sup.3 Decreasing the number of layers in mesoscopic MoS.sub.2 structures leads to a transformation from an indirect band gap semiconductor with a band gap of 1.2 eV (ref 18) into a direct gap semiconductor,.sup.13, 19-21 with a band gap of 1.8 eV (ref 13) due to quantum confinement..sup.21 Being an ultrathin direct gap semiconductor, single-layer MoS.sub.2 is very interesting as a material complementary to graphene which does not have a band gap in its pristine form. This makes it very difficult to fabricate logic circuits.sup.22-23 or amplifiers.sup.24 that would operate at room temperature with a voltage gain>1 which is necessary for incorporating such structures in electronic circuits. The presence of band-gap in single-layer MoS.sub.2 on the other hand allows the realization of field-effect transistors with room-temperature on/off ratios that can exceed 10.sup.8 (ref. 3) which makes them interesting for building logic devices with low power dissipation. Recent simulations also predict that short channel single-layer MoS.sub.2 devices could have higher on-current density than those based on Si,.sup.25 26 current on/off ratio higher than 10.sup.10, high degree of immunity to short channel effects.sup.2, 27 and abrupt switching..sup.26 All these properties show that MoS.sub.2 could be an interesting material for future applications in nanoelectronics.

(72) We begin our integrated circuit fabrication by exfoliating single-layer MoS.sub.2, FIG. 8(b), from bulk crystals using scotch-tape based micromechanical exfoliation,.sup.1, 4 commonly used for the production of graphene. Monolayers of MoS.sub.2 are deposited on degenerately doped Si substrates covered with 270 nm thick SiO.sub.2, resulting in optimal contrast for optical detection of single-layers..sup.28 Three electrical leads are first fabricated using standard electron-beam lithography, followed by deposition of 90 nm thick Au electrodes and annealing in Ar/H.sub.2 mixture.sup.29 in order to remove resist residue and decrease contact resistance. The device is then covered by atomic layer deposition of 30 nm HfO.sub.2, a high- material commonly used as a gate dielectric..sup.30-31 Finally, local top gates are deposited in the final round of e-beam lithography and metal deposition resulting in an integrated circuit such as the one shown on FIG. 8(b), composed of two single-layer transistors connected in series. The channel width of the transistors in our integrated circuit is 4.2 m, lead spacing is 1.6 m and top gate length is 1.3 m.

(73) Both transistors in our integrated circuit can be independently controlled by applying a voltage V.sub.tg to the corresponding top gate which is one of the crucial requirements for constructing integrated circuits composed of multiple transistors realized on the same substrate. We characterize both transistors in our integrated circuit at room temperature by connecting a pair of neighboring leads to the source and ground terminals of a semiconductor parameter analyzer and a voltage V.sub.tg to the corresponding top gate. The substrate is grounded throughout the measurements. The transfer characteristic for the transistor on the right side of the integrated circuit is shown on FIG. 8(c), and is typical of n-type field-effect transistors. By changing the top gate voltage V.sub.tg from 4V to +4V we can modify the current through the device over several orders of magnitude thanks to the high current on/off ratio of our transistor, higher than 10.sup.6 in this range of top-gate voltage V.sub.tg. The on-resistance is 24 k for V.sub.ds=100 mV and V.sub.tg=4 V. The linear and symmetric I.sub.ds vs V.sub.ds characteristics shown on FIG. 8(d) indicates that the contacts are ohmic. From back-gating characteristics, shown in the inset of FIG. 8(c), we estimate the two-contact low-field field effect mobility of 320 cm.sup.2/Vs. At the bias voltage V.sub.ds=500 mV, the maximal measured on current is 22 A (4.6 A/m), with I.sub.on/I.sub.off higher than 10.sup.6 for the 4 V range of V.sub.tg and an I.sub.off400 A/m.

(74) The device transconductance defined as g.sub.m=dI.sub.ds/dV.sub.tg is 12 S (2.6 S/m) for V.sub.ds=500 mV and is comparable to CdS nanoribbon array transistors (2.5 S/m at V.sub.ds=1 V)..sup.32 High-performance top-gated graphene transistors can have normalized transconductance values.sup.33 as high as 1.27 mS/m while carbon nanotubes can reach transconductance of 2.3 mS/m..sup.34 We expect that by lowering the channel length will reduce the number of scattering centers and increase the on current in MoS.sub.2-based transistors. Theoretical models predict that MoS.sub.2 transistors with a gate length of 15 nm would operate in the ballistic regime.sup.25-26 with a maximum ON current as high as 1.6 mA/m and a transconductance of 4 mS/um, both for V.sub.g=0.6 V and a bias V.sub.ds=0.5 V..sup.26

(75) The efficient channel switching for small voltages exhibited by our device is also clearly illustrated on Fig. (d) where we show the source-drain current I.sub.ds dependence on source-drain voltage V.sub.ds for different values of top gate voltage V.sub.tg. This large degree of control at room-temperature is necessary for realizing logic operations with large voltage gain. For development of logic circuits based on new materials, a voltage gain >1 is necessary so that the output of one logic gate could be used to drive the input of the next gate without the need for signal restoration.

(76) We proceed by demonstrating that our single-layer MoS.sub.2 integrated circuit can operate as the most basic logic gate: a logic inverter, capable of converting a logical 0 (low input voltage) into logical 1 (high output voltage). We connect the middle lead to one of the local gates in a configuration depicted in the inset of FIG. 9(a), commonly used in logic circuits based on only one type (n or p) of transistors. In this configuration, the lower transistor acts as a switch while the upper one acts as an active load. Input voltage V.sub.in is applied to the local gate of the switch transistor while the supply voltage V.sub.dd=2V is applied to the drain electrode of the load transistor. The output voltage and transfer characteristic of the inverter as a function of the input voltage V.sub.in is shown on FIG. 9(a).

(77) For input voltages corresponding to logic 0, the switch transistor has a higher resistance than the load transistor and is effectively turned off. This results in a constant voltage at the output terminal which is close to the supply voltage of V.sub.dd=2V applied to the load drain electrode. By increasing the input voltage above 1V, the lower FET becomes more conductive and the output voltage V.sub.out is now in the low range.

(78) In the input voltage range of 0.3 V, the output of the inverter is changing faster than the input, indicating that our device is capable of amplifying signals. The voltage gain defined as the negative of dV.sub.out/dV.sub.in and plotted on FIG. 9(b) is higher than 4. For successful implementation of digital logic in electronic circuits based on any new nanomaterial, a voltage gain>1 is needed so that the output of one inverter could drive the input of the next inverter in the cascade. Our inverter has a voltage gain higher than 4 and is therefore suitable for integration in arrays of logic gates. This could involve level shifters because the input and output logic levels are not the same. Increasing the threshold voltage of MoS.sub.2 transistors using for example substrate functionalization could also bring input and output voltages to the same level.

(79) We note that to the best of our knowledge the maximal voltage gain for graphene-based inverters.sup.22 demonstrated so far is 2-7 but at the temperature of 80K,.sup.23,35 due to the low bandgap (<100 meV) in bilayer graphene which prohibits the use of such devices at room temperature.

(80) Our monolayer MoS.sub.2 transistors can also be used to perform logic operations involving two operands. By connecting two transistors in parallel and using an external resistor as load, we can construct a NOR gate, shown on the inset of FIG. 10, where we show the output voltage for all the possible input states of the NOR gate. When either one or both of the transistors are in the on state (corresponding to V.sub.in=2V), the output is 0V, corresponding to logical 0. Only when both transistors are in the off state, does the output become logical 1 (V.sub.outV.sub.dd=2V). NOR operation forms a functionally complete set of binary operations: every possibly logic operation (AND, OR, NAND etc.) can be realized using a network of NOR gates.

CONCLUSIONS

(81) We have demonstrated here that single-layer MoS.sub.2, a new two-dimensional semiconductor, can be used as the material basis for fabrication of integrated circuits and for performing logic operations with room-temperature characteristic suitable for integration. Our work represents the critical first step in the implementation of digital logic in two-dimensional materials at room temperature. Together with the possibility of large-scale liquid-based processing of MoS.sub.2 and related 2D materials,.sup.17 our finding could open the way to using MoS.sub.2 for applications in flexible electronics. Single-layer MoS.sub.2 also has advantages over conventional silicon: it is thinner than state of the art silicon films that are 2 nm thick.sup.36 and has a smaller dielectric constant (=7, ref. 37) than silicon (=11.9), implying that using single-layer MoS.sub.2 could reduce short channel effects.sup.26 and result in smaller and less power-hungry transistors than those based on silicon technology. Several difficulties however need to be solved before MoS.sub.2 could become a mainstream electronic material for the semiconductor industry. A method for large-scale growth of continuous monolayers of MoS.sub.2 or a similar 2D semiconductor will be needed to fabricate more complex integrated circuits with a large number of elements.

MATERIALS AND METHODS

(82) Single layers of MoS.sub.2 are exfoliated from commercially available crystals of molybdenite (SPI Supplies Brand Moly Disulfide) using the scotch-tape micromechanical cleavage technique method pioneered for the production of graphene. AFM imaging is performed using the Asylum Research Cypher AFM. After Au contact deposition, devices are annealed in 100 sccm of Ar and 10 sccm H.sub.2 flow at 200 C for 2 h..sup.29 ALD is performed in a commercially available system (Beneq) using a reaction of H.sub.2O with tetrakis(ethyl-methylamido)hafnium. Electrical characterization is carried out using National Instruments DAQ cards and a home-built shielded probe station with micromanipulated probes.

REFERENCES TO EXAMPLE 2

(83) 1. Novoselov, K. S.; Jiang, D.; Schedin, F.; Booth, T. J.; Khotkevich, V. V.; Morozov, S. V.; Geim, A. K., Two-Dimensional Atomic Crystals. PNAS 2005, 102, 10451-10453. 2. Schwierz, F., Graphene Transistors. Nature Nanotech. 2010, 5, 487-496. 3. Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A., Single-Layer MoS.sub.2 Transistors. Nature Nanotech. 2011, 6, 147-150. 4. Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A., Electric Field Effect in Atomically Thin Carbon Films. Science 2004, 306, 666-669. 5. Bolotin, K. I.; Sikes, K. J.; Jiang, Z.; Klima, M.; Fudenberg, G.; Hone, J.; Kim, P.; Stormer, H. L., Ultrahigh Electron Mobility in Suspended Graphene. Solid State Communications 2008, 146, 351-355. 6. Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Katsnelson, M. I.; Grigorieva, I. V.; Dubonos, S. V.; Firsov, A. A., Two-Dimensional Gas of Massless Dirac Fermions in Graphene. Nature 2005, 438, 197-200. 7. Du, X.; Skachko, I.; Duerr, F.; Luican, A.; Andrei, E. Y., Fractional Quantum Hall Effect and Insulating Phase of Dirac Electrons in Graphene. Nature 2009, 462, 192-195. 8. Han, M. Y.; Ozyilmaz, B.; Zhang, Y. B.; Kim, P., Energy Band-Gap Engineering of Graphene Nanoribbons. Phys. Rev. Lett. 2007, 98, 206805. 9. Li, X.; Wang, X.; Zhang, L.; Lee, S.; Dai, H., Chemically Derived, Ultrasmooth Graphene Nanoribbon Semiconductors. Science 2008, 319, 1229-1232. 10. Zhang, Y.; Tang, T.-T.; Girit, C.; Hao, Z.; Martin, M. C.; Zettl, A.; Crommie, M. F.; Shen, Y. R.; Wang, F., Direct Observation of a Widely Tunable Bandgap in Bilayer Graphene. Nature 2009, 459, 820-823. 11. Xia, F.; Farmer, D. B.; Lin, Y.-m.; Avouris, P., Graphene Field-Effect Transistors with High on/Off Current Ratio and Large Transport Band Gap at Room Temperature. Nano Lett. 2010, 10, 715-718. 12. Sols, F.; Guinea, F.; Neto, A. H. C., Coulomb Blockade in Graphene Nanoribbons. Phys. Rev. Lett. 2007, 99, 166803. 13. Mak, K. F.; Lee, C.; Hone, J.; Shan, J.; Heinz, T. F., Atomically Thin MoS.sub.2: A New Direct-Gap Semiconductor. Phys. Rev. Lett. 2010, 105, 136805. 14. Frindt, R. F., Single Crystals of MoS.sub.2 Several Molecular Layers Thick. J. App. Phys. 1966, 37, 1928-1929. 15. Joensen, P.; Frindt, R. F.; Morrison, S. R., Single-Layer Mos.sub.2. Mat. Res. Bull. 1986, 21, 457-461. 16. Schumacher, A.; Scandella, L.; Kruse, N.; Prins, R., Single-Layer MoS.sub.2 on Mica: Studies by Means of Scanning Force Microscopy. Surf Sci. Lett. 1993, 289, L595-L598. 17. Coleman, J. N.; Lotya, M.; O'Neill, A.; Bergin, S. D.; King, P. J.; Khan, U.; Young, K.; Gaucher, A.; De, S.; Smith, R. J., et al., Two-Dimensional Nanosheets Produced by Liquid Exfoliation of Layered Materials. Science 2011, 331, 568-571. 18. Kam, K. K.; Parkinson, B. A., Detailed Photocurrent Spectroscopy of the Semiconducting Group Vib Transition Metal Dichalcogenides. J. Phys. Chem. 1982, 86, 463-467. 19. Lebegue, S.; Eriksson, O., Electronic Structure of Two-Dimensional Crystals from Ab Initio Theory. Phys. Rev. B 2009, 79, 115409. 20. Splendiani, A.; Sun, L.; Zhang, Y.; Li, T.; Kim, J.; Chim, C.-Y.; Galli, G.; Wang, F., Emerging Photoluminescence in Monolayer MoS.sub.2. Nano Lett. 2010, 10, 1271-1275. 21. Kuc, A.; Zibouche, N.; Heine, T., How Does Quantum Confinement Influence the Electronic Structure of Transition Metal Sulfides Tms.sub.2. Cond-mat 2011, 1104.3670. 22. Traversi, F.; Russo, V.; Sordan, R., Integrated Complementary Graphene Inverter. Appl. Phys. Lett. 2009, 94, 223312. 23. Li, S.-L.; Miyazaki, H.; Kumatani, A.; Kanda, A.; Tsukagoshi, K., Low Operating Bias and Matched Input-Output Characteristics in Graphene Logic Inverters. Nano Lett. 2010, 10, 2357-2362. 24. Yang, X.; Liu, G.; Balandin, A. A.; Mohanram, K., Triple-Mode Single-Transistor Graphene Amplifier and Its Applications. ACS Nano 2010, 4, 5532-5538. 25. Liu, L.; Kumar, S. B.; Ouyang, Y.; Guo, J., Performance Limits of Monolayer Transition Metal Dichalcogenide Transistors. IEEE Trans. El. Dev. 2011, 58, 3042-3047. 26. Yoon, Y.; Ganapathi, K.; Salahuddin, S., How Good Can Monolayer MoS.sub.2 Transistors Be? Nano Lett. 2011, 11, 3768-3773. 27. Schwierz, F., Nanoelectronics: Flat Transistors Get Off the Ground. Nature Nanotech. 2011, 6, 135-136. 28. Benameur, M. M.; Radisavljevic, B.; Heron, J. S.; Sahoo, S.; Berger, H.; Kis, A., Visibility of Dichalcogenide Nanolayers. Nanotechnology 2011, 22, 125706. 29. Ishigami, M.; Chen, J. H.; Cullen, W. G.; Fuhrer, M. S.; Williams, E. D., Atomic Structure of Graphene on Sio2. Nano Lett. 2007, 7, 1643-1648. 30. Bohr, M. T.; Chau, R. S.; Ghani, T.; Mistry, K., The High-K Solution. IEEE Spectrum October 2007, 44, 29-35. 31. Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, A.; Chau, R., et al., A 45 nm Logic Technology with High-K+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-Free Packaging. Tech. Dig. IEDM 2007, 247-250. 32. Duan, X.; Niu, C.; Sahi, V.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L., High-Performance Thin-Film Transistors Using Semiconductor Nanowires and Nanoribbons. Nature 2003, 425, 274-278. 33. Liao, L.; Lin, Y.-C.; Bao, M.; Cheng, R.; Bai, J.; Liu, Y.; Qu, Y.; Wang, K. L.; Huang, Y.; Duan, X., High-Speed Graphene Transistors with a Self-Aligned Nanowire Gate. Nature 2010, 467, 305-308. 34. Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, P., Vertical Scaling of Carbon Nanotube Field-Effect Transistors Using Top Gate Electrodes. Appl. Phys. Lett. 2002, 80, 3817. 35. Li, S.-L.; Miyazaki, H.; Lee, M. V.; Liu, C.; Kanda, A.; Tsukagoshi, K., Complementary-Like Graphene Logic Gates Controlled by Electrostatic Doping. Small 2011. 36. Gomez, L.; Aberg, I.; Hoyt, J. L., Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body N-Mosfets with Body Thickness Ranging from 2 to 25 Nm. El. Dev. Lett., IEEE 2007, 28, 285-287. 37. Frindt, R. F.; Yoffe, A. D., Physical Properties of Layer Structures: Optical Properties and Photoconductivity of Thin Crystals of Molybdenum Disulphide. Proceedings of the Royal Society of London. Series A. Mathematical and Physical Sciences 1963, 273, 69-83.