Enhanced lateral cavity etch

Abstract

A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.

Claims

1. A method of forming a cavity in a substrate comprising: forming a masking layer on the substrate; forming an opening in the masking layer; performing a first cavity etch through the opening to form a cavity under the opening wherein the first cavity etch etches both laterally and vertically; depositing a polymer through the opening onto the bottom and sidewalls of the cavity wherein the polymer is thicker on the bottom of the cavity than on the sidewalls of the first cavity; removing the polymer from the sidewalls of the first cavity; performing a second cavity etch through the opening and etching the sidewalls of the cavity to increase a width of the cavity without increasing a depth of the cavity, wherein the depth of the cavity is non-uniform across the width; and removing the polymer from the cavity.

2. The method of claim 1, further comprising; repeating a cycle of the depositing the polymer, performing the second cavity etch, and removing the polymer processes until the cavity reaches a target cavity width.

3. The method of claim 1, wherein the substrate is single crystal silicon and wherein the masking layer is a layer of silicon nitride overlying a layer of silicon dioxide.

4. The method of claim 1, wherein the first cavity etch comprises a plasma etch using SF.sub.6 and the polymer deposition comprises a plasma polymer deposition using a fluorocarbon.

5. The method of claim 1, wherein the step of removing the polymer comprises a plasma ash containing oxygen.

6. A method of forming a cavity in an integrated circuit substrate comprising: forming a masking layer on the substrate; forming an opening in the masking layer; performing a first cavity etch using a SF.sub.6 plasma through the opening to form a cavity under the opening in the masking layer wherein the first cavity etch etches both laterally and vertically; and repeating the following processes until the width of the cavity reaches a target cavity width: depositing a polymer on the bottom and sidewalls of the cavity using a fluorocarbon plasma wherein the polymer is thicker on the bottom of the cavity under the opening in the masking layer and wherein the polymer is thinner on the sidewalls of the cavity; removing the polymer from the sidewalls of the cavity; performing a second cavity etch using a SF.sub.6 plasma through the opening and etching the sidewalls of the cavity to increase the width of the cavity, wherein the polymer on the bottom of the cavity blocks the second cavity etch from increasing the depth of the cavity; and removing the polymer from the first and second cavity; wherein when the width of the cavity reaches the target cavity width, the width is greater than the depth of the cavity and the depth of the cavity is non-uniform across the width of the cavity.

7. The method of claim 6, wherein removing the polymer comprises a plasma ash containing oxygen.

8. The method of claim 7, wherein the fluorocarbon is selected from the group consisting of CH.sub.4, CHF.sub.3, CH.sub.2F.sub.2, C.sub.2F.sub.6, C.sub.3F.sub.6, and C.sub.4F.sub.8.

9. The method of claim 8, wherein the masking layer is comprised of a layer of silicon nitride on top of a layer of silicon dioxide.

Description

DESCRIPTION OF THE VIEWS OF THE DRAWINGS

(1) FIG. 1A through FIG. 1J are cross sections illustrating the formation of a cavity in an integrated circuit in successive stages of fabrication according to principles of the invention.

(2) FIG. 2 is flow diagram for the steps in a process of forming a cavity in a substrate according to principles of the invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(3) The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.

(4) A structure with a cavity that is etched according to embodiments is illustrated in FIG. 1F. The cavity is etched into the substrate 100 using an etch that is substantially isotropic. The cavity is wider than it is deep. The cavity depth is non uniform across the width of the cavity. The cavity is deepest under the opening through which the cavity is etched.

(5) The method for forming a cavity wherein the width of the cavity is substantially wider than the depth of the cavity is described in the process flow in FIG. 2 and in the cross sections in FIGS. 1A through 1J.

(6) FIG. 1A shows a substrate 100 that may be etched using an etchant that etches substantially isotropically, that is, etches laterally as well as vertically. A hard mask (layers 102 and 104) overlies the substrate. The etchant may be introduced through an opening 106 in the hard mask 102/104 to etch a cavity in the substrate 100 (step 200 in FIG. 2). In an example embodiment, the substrate 100 is single crystal silicon and the hard mask is comprised of a layer of silicon nitride 104 which overlies a layer of silicon dioxide 102. One layer of masking material (silicon dioxide for example) may alternatively be used. Other masking materials and other substrates may also be used. The opening 106 in the example embodiment may be in the range of less than a micron to many microns wide depending upon the details of the device being manufactured. In an example embodiment opening 106 is about 25 microns wide.

(7) In first cavity etch step 202 of FIG. 2, etchant is introduced through opening 106 and etches the substrate 100 both vertically and laterally to form a cavity with first cavity etch sidewalls 108 as shown in FIG. 1B. In an example embodiment the silicon substrate 100 is etched in a substantially isotropic manner using a SF.sub.6 plasma etch. In the example embodiment, the SF.sub.6 etches the silicon approximately twice as fast vertically as laterally through the opening 106.

(8) Example cavity etch process conditions are 225 mT pressure, 4000 Watts source power, 0 Watts bias power, 1000 sccm SF.sub.6, and a temperature of 15 C.

(9) In step 204 of FIG. 2 polymer 110 is formed on the bottom and sidewalls 108 of the first etched cavity as shown in FIG. 1C. Typically the polymer 110 is thicker on the bottom of the cavity under the opening 106 and gets thinner on the sidewalls 108 of the cavity away from under the opening 106. The polymer deposition step is typically performed using a plasma with a fluorocarbon gas, C.sub.xH.sub.yF.sub.z, such as CH.sub.4, CHF.sub.3, CH.sub.2F.sub.2, C.sub.2F.sub.6, C.sub.3F.sub.6, and C.sub.4F.sub.8.

(10) Example polymer deposition process conditions are 10 mT pressure, 3800 Watts source power, 0 Watts bias power, 200 sccm C.sub.4F.sub.8, and a temperature of 15 C.

(11) In step 206 of FIG. 2 an optional ashing step may be performed to remove the polymer from the sidewalls 108 of the cavity where the polymer is thin as shown in FIG. 1D. In some cases so little polymer may be formed in the sidewalls that a separate ashing step is unnecessary. Instead a breakthrough etch step to remove minor amounts of polymer may be performed at the beginning of the subsequent SF.sub.6 silicon etch. In the example embodiment a plasma ashing step with oxygen is used.

(12) Example ashing process conditions are 30 mT pressure, 2500 Watts source power, 0 Watts bias power, 200 sccm oxygen, and a temperature of 15 C.

(13) In step 208 of FIG. 2, a second cavity etch is performed as shown in FIG. 1E. The polymer 110 covering the bottom of the trench prevents the cavity from being etched deeper into the substrate. The etchant enlarges the cavity laterally forming second cavity etch walls 112 that are spaced at a greater lateral distance from the opening than the lateral walls 108 of the first cavity etch (step 202).

(14) In step 210 of FIG. 2 the polymer may be removed from the cavity using an ashing step, as shown in FIG. 1F. This step is optional if the final trench width has not been achieved. In the example embodiment a plasma ashing step containing oxygen is used. The ashing conditions are described previously.

(15) In step 212 of FIG. 2, a determination may be made to see if the target cavity width has been achieved. If the target cavity width is achieved the wafers may be sent on to the next process step in the manufacturing flow (step 214 in FIG. 2).

(16) If, however, the target cavity width is not achieved, the wafers may be returned to step 204 in FIG. 2 and the process of polymer deposition followed by another cavity etch step may be repeated until the target width is achieved.

(17) A second polymer deposition step followed by a third cavity etch is illustrated in FIG. 1G through FIG. 1J. More than three cycles of polymer deposition, cavity etch, and polymer removal may be performed to achieve the desired cavity width without etching the cavity deeper.

(18) In FIG. 1G (step 204 of FIG. 2), polymer is deposited onto the cavity sidewalls 108 and 112.

(19) In FIG. 1H (step 206 of FIG. 2), an optional ashing step is performed to remove the polymer 114 from the lateral sidewalls 112 of the cavity if it is needed.

(20) In FIG. 1I (step 208 of FIG. 2), a third cavity etch is performed. The polymer 114 on the bottom of the cavity walls 108 and 112 prevents the cavity from being etched deeper into the silicon. The exposed second cavity etch walls 112 are etched laterally away from the opening 106 to form third etch cavity walls 116.

(21) In FIG. 1J, (step 210 of FIG. 2) the polymer is removed from the cavity by ashing. As shown in FIG. 1J, the width of the cavity is substantially wider than the depth of the cavity. As an example, the width may be approximately twice the depth or more. This cavity is formed without the addition of an etch stop layer in the substrate which may add significant complexity and cost to the manufacturing flow. Cavities formed when an etch stop layer is used typically have a uniform depth across the width of the cavity. The depth of the cavity formed using the embodiment process is not uniform in depth across the width of the cavity as is illustrated in FIG. 1F and FIG. 1J.

(22) While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.